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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 397 records · Page 22
All sourcesNASA NTRSDOE OSTI
NASA NTRS2013

Memory Circuit Fault Simulator

Spacecraft are known to experience significant memory part-related failures and problems, both pre- and postlaunch. These memory parts include both static and dynamic memories (SRAM and DRAM). These failures manifest themselves in a variety of ways, such as pattern-sensitive failures, timingsensitive failures, etc. Because of the mission critical nature memory devices play in spacecraft architecture and operation, understanding their failure modes is vital to successful mission operation. To support this need, a generic simulation tool that can model different data patterns in conjunction with variable write and read conditions was developed. This tool is a mathematical and graphical way to embed pattern, electrical, and physical information to perform what-if analysis as part of a root cause failure analysis effort.

Sheldon, Douglas J.↗
NASA NTRS2018

Error Characterization and Mitigation for 16Nm MLC NAND Flash Memory Under Total Ionizing Dose Effect

A data device includes a memory having a plurality of memory cells configured to store data values in accordance with a predetermined rank modulation scheme that is optional and a memory controller that receives a current error count from an error decoder of the data device for one or more data operations of the flash memory device and selects an operating mode for data scrubbing in accordance with the received error count and a program cycles count.

Li, Yue↗
NASA NTRS2004

Potential bio-medical and commercial applications of cold hibernated elastic memory (CHEM) self-deployable foam structures

A cold hibernated elastic memory (CHEM) foam structure is one of the most recent results of the quest for simple, reliable and low-cost expandable space structures. The CHEM technology utilizes shape memory polymers in open cellular (foam) structure or sandwich structures made of shape memory polymer foam cores and polymeric composite skins. It takes advantage of the polymer’s heat activated shape memory in addition to the foam’s elastic recovery to deploy a compacted structure. The glass transition temperature, Tg is tailored to rigidize the structure in the fully deployed configuration.

Sokolowski, Witold↗
NASA NTRS2009

Flash memory reliability NEPP 2008 task final report

This is the preliminary report which is based on the flash memory reliability studies conducted during the first year (2008) of the multi-year NEPP task. The report outlines the technology and reliability challenges for advanced flash memory technologies, summarizes the test results and analyses of reliability characterizations performed on the selected flash memory devices during 2008, and provides the preliminary thoughts on the risk mitigation approaches on using advanced flash memory technologies for space applications.

Chen, Yuan↗
NASA NTRS2010

NEPP non-volatile memory : FY09 summary report

This report documents the activities and results of the fiscal year 2009 (FY09) funding for the NASA Electronic Parts and Packaging (NEPP) program for non-volatile memory (NVM) devices. The FY09 task was divided into two main efforts: 1. Development of in-house measurement capability for flash devices 2. Reliability characterization of multi-level vs. single-level flash devices The FY09 NEPP Non Volatile Memory study was organized into these two sections in recognition of the continued and increasing importance of NVM to NASA. All NASA missions use NVM for boot code storage and some limited data archiving. Space-grade NVM has lagged commercial NVM development by many orders of magnitude, however. This gap in density only continues to increase as space-grade memories remain constant in the 1–16 Mbit levels, while commercial flash-based devices shrink in size and double in capacity every 18 months. Commercial flash devices are now at the 32 Gbit level, 10,000 times denser than current NASA NVM. This FY marks the beginning of a significant technological transition in NVM for NASA. The aggressive scaling of commercial NVMs has, as a by-product, made some of the flash devices radiation-tolerant enough to be at least considered for low-level radiation environment missions [Irom 2008]. This NEPP task is focused on understanding the reliability and potential future applications of such highly scaled flash memories.

Heidecker, Jason↗
NASA NTRS2009

Radiation tests of highly scaled high density commercial nonvolatile NAND flash memories update 2009

Heavy ion single-event measurements on a variety of high density commercial NAND flash memories are reported. Three single event effect (SEE) phenomena are examined: single effect upsets (SEUs), single event functional interrupts (SEFIs), and catastrophic loss of ability to erase and program the device. Also, radiation results of multilevel flash technology are compared with results from single-level flash technology. These commercial high density memories appear to be much less susceptible to SEE and have better TID response compared to older generations of flash memories. The single-level devices are less sensitive to SEUs than multi-level devices. The charge pump in this study survived up to 600 krads. A new high current phenomenon in high density NAND flash memories is also discussed.

Nguyen, Duc N.↗
NASA NTRS2018

Radiation Performance of Memory Technologies for Space Applications

MRAM and DRAM memory technologies identified for possible radiation hardening were investigated for memory-array- and controller-level radiation sensitivity. TID and SEE performance of memory arrays and associated cells is good, but with some questions about viability of hardening of problematic control circuitry. Control-circuitry-related SEE problems are highlighted. TID data are focused on memory arrays only.

Some, Raphael↗
NASA NTRS2020

Comparing Cumulative Flight Thermal Fatigue to Ground Test Results for Memory Components on the Mars Curiosity Rover

This paper explores the methods used to examine Mars Curiosity Rover’s flight temperature data to the Package Qualification and Verification (PQV) accelerated thermal cycle life test data in response to flight anomalies. The redundant Rover Compute Element (RCE-A, B) has experienced an inability to mount the flash memory several times. The leading cause of these anomalies is likely the loss of electrical connectivity, which is theorized to be due to cracks on the memory component solder joints by thermal cycle fatigue. To investigate this theory, the number of thermal cycles accumulated in flight was compared to PQV accelerated thermal cycle life test data. The goal of this study was to inform mission operations of the risk associated with thermal cycling damage on the RCE. However, since the RCE-B does not have continuous temperature data from the Platinum Resistance Thermometer (PRT) closest to the flash memory, a model was made to correlate continuous data from two other nearby sensors on the RCE-B to the noncontiguous sensor. Using the Rainflow Counting Algorithm, the reconstituted data was converted into the number of equivalent thermal cycles. The Coffin-Manson Equation was used to compare flight thermal cycles to the PQV test. The accelerated life test showed cracking on the memory component solder joints after 500 cycles of 80°C temperature excursions. This study found that the RCE-A and RCE-B have undergone an equivalent of 144 and 430 cycles of 80°C temperature excursions during flight, respectively.

Berger, Lindsey N↗
NASA NTRS2021

R-Hope: Development Approach to Extreme Non-volatile Memory Reuse Onboard the Curiosity Rover

The MSL Curiosity rover landed on Mars on August~5, 2012. Over time, one of its two computers experienced critical hardware memory failure. This non-volatile NAND flash memory held file system partitions and tunable parameters needed for running rover flight software. The project assembled a design and development team to re-purpose a NOR flash memory hardware chip, only 1.5\% of the size of the NAND, to hold the file systems and parameters. The usable NOR memory required major software changes to accommodate the new limitations of slower access speeds, vastly different physical layout, and smaller size. This presentation discusses the approach, challenges, and outcomes of restoring function to the computer so it can act as a ``lifeboat'' in event of problems with the primary computer.

Peper, Nick↗
NASA NTRS2021

Comparing Cumulative Flight Thermal Fatigue to Ground Test Results for Memory Components on the Mars Curiosity Rover

This paper explores the methods used to examine Mars Curiosity Rover’s flight temperature data in relation to the Package Qualification and Verification (PQV) accelerated thermal cycle life test data in response to flight anomalies. The redundant Rover Compute Element (RCE-A, B) has experienced an inability to mount the flash memory several times. The leading cause of these anomalies is likely the loss of electrical connectivity, which is theorized to be due to cracks on the memory component solder joints by thermal cycle fatigue. To investigate this theory, the number of thermal cycles accumulated in flight was compared to PQV accelerated thermal cycle life test data. The goal of this study was to inform mission operations of the risk associated with thermal cycling damage on the RCE. However, since the RCE-B does not have continuous temperature data from the Platinum Resistance Thermometer (PRT) closest to the flash memory, a model was made to correlate continuous data from two other nearby sensors on the RCE-B to the noncontiguous sensor. Using the Rainflow Counting Algorithm, the reconstituted data was converted into the number of equivalent thermal cycles. The Coffin-Manson Equation was used to compare flight thermal cycles to the PQV test. The accelerated life test showed cracking on the memory component solder joints after 500 cycles of 80°C temperature excursions. This study found that the RCE-A and RCE-B have undergone an equivalent of 144 and 430 cycles of 80°C temperature excursions during flight, respectively.

Bell, Charles↗
DOE OSTI2021

Caching data from remote memories

An approach is disclosed that caches distant memories within the storage a local node. The approach provides a memory caching infrastructure that supports virtual addressing by utilizing memory in the local node as a cache of distant memories for data granules. The data granules are accessed along with metadata and an ECC associated with the data granule. The metadata is updated to indicate storage of the selected data granule in the cache.

Johns, Charles Ray↗
DOE OSTI2022

Dynamic voltage frequency scaling based on active memory barriers

A processing unit includes compute units partitioned into one or islands that are provided with operating voltages and clock signals having clock frequencies independent of providing operating voltages or clock signals to other islands of compute units. The processing unit also includes dynamic voltage and frequency scaling (DVFS) hardware configured to compute one or more numbers of active memory barriers in the one or more islands. The DVFS hardware is also configured to modify the operating voltages or clock frequencies provided to the one or more islands in response to a change in numbers of active memory barriers in the one or more islands. In some cases, the operating voltage or clock frequency provided to an island is increased in response to the number of active memory barriers in the island decreasing. The operating voltage or clock frequency provided to the island is decreased in response to the number of active memory barriers in the island increasing.

Bharadwaj, Vedula Venkata Srikant↗
DOE OSTI2022

Bias control for a memory device

Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Method and apparatus for front end gather/scatter memory coalescing

A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Method and apparatus for back end gather/scatter memory coalescing

A system for processing gather and scatter instructions can implement a front-end subsystem, a back-end subsystem, or both. The front-end subsystem includes a prediction unit configured to determine a predicted quantity of coalesced memory access operations required by an instruction. A decode unit converts the instruction into a plurality of access operations based on the predicted quantity, and transmits the plurality of access operations and an indication of the predicted quantity to an issue queue. The back-end subsystem includes a load-store unit that receives a plurality of access operations corresponding to an instruction, determines a subset of the plurality of access operations that can be coalesced, and forms a coalesced memory access operation from the subset. A queue stores multiple memory addresses for a given load-store entry to provide for execution of coalesced memory accesses.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Bias control for a memory device

Methods, systems, and devices for bias control for a memory device are described. A memory system may store indication of whether data is coherent. In some examples, the indication may be stored as metadata, where a first value indicates that the data is not coherent and a second value or a third value indicate that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.

Walker, Dean↗
DOE OSTI2022

Device-Centric Ransomware Detection using Machine Learning-Based Memory Forensics for Smart Inverters

Ransomware attacks are the fastest-growing form of cyberattacks worldwide. Recently, ransomware attacks have targeted industrial control systems (ICSs), including power grids. Lessons learned from recent incidents in ICSs show that ransomware groups can deliver ransomware into not only the organization’s control servers, but also the operational technology (OT) devices such as smart inverters and smart grid devices. This paper proposes a machine learning (ML)- based memory forensics method enabling the detection of ransomware binaries stored in the memory of a commercial smart inverter. Device firmware binary files are extracted from a Serial Peripheral Interface (SPI) flash memory, and samples of both benign and ransomware binaries are generated by a binary manipulation method and a real-world ransomware encryption, separately. A deep transfer learning (DTL) method is used to retrain a convolutional neural network (CNN)-based ransomware detection algorithm using the generated samples. The experimental result validates that the proposed ML-based memory forensics method can accurately detect ransomware files.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Nanoporous Dielectric Resistive Memories Using Sequential Infiltration Synthesis

Resistance switching in metal–insulator–metal structures has been extensively studied in recent years for use as synaptic elements for neuromorphic computing and as nonvolatile memory elements. However, high switching power requirements, device variabilities, and considerable trade-offs between low operating voltages, high on/off ratios, and low leakage have limited their utility. Here, we have addressed these issues by demonstrating the use of ultraporous dielectrics as a pathway for high-performance resistive memory devices. Using a modified atomic layer deposition based technique known as sequential infiltration synthesis, which was developed originally for improving polymer properties such as enhanced etch resistance of electron-beam resists and for the creation of films for filtration and oleophilic applications, we are able to create ~15 nm thick ultraporous (pore size ~5 nm) oxide dielectrics with up to 73% porosity as the medium for filament formation. We show, using the Ag/Al 2 O 3 system, that the ultraporous films result in ultrahigh on/off ratio (>10 9 ) at ultralow switching voltages (~±600 mV) that are 10× smaller than those for the bulk case. In addition, the devices demonstrate fast switching, pulsed endurance up to 1 million cycles. and high temperature (125 °C) retention up to 10 4 s, making this approach highly promising for large-scale neuromorphic and memory applications. Additionally, this synthesis methodology provides a compatible, inexpensive route that is scalable and compatible with existing semiconductor nanofabrication methods and materials.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗