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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 397 records · Page 22
All sourcesNASA NTRSDOE OSTI
NASA NTRS1991

Range estimation techniques in single-station thunderstorm warning sensors based upon gated, wideband, magnetic direction finder technology

Gated, wideband, magnetic direction finders (DFs) were originally designed to measure the bearing of cloud-to-ground lightning relative to the sensor. A recent addition to this device uses proprietary waveform discrimination logic to select return stroke signatures and certain range dependent features in the waveform to provide an estimate of range of flashes within 50 kms. The enhanced ranging techniques are discussed which were designed and developed for use in single station thunderstorm warning sensor. Included are the results of on-going evaluations being conducted under a variety of meteorological and geographic conditions.

Pifer, Alburt E.↗
DOE OSTI2022

100 Gb/s High Throughput Serial Protocol (HTSP) for data acquisition systems with interleaved streaming

Demands on Field-Programmable Gate Array (FPGA) data transport have been increasing over the years as frame sizes and refresh rates increase. As the bandwidths requirements increase the ability to implement data transport protocol layers using "soft" programmable logic becomes harder and start to require harden IP blocks implementation. To reduce the number of physical links and interconnects, it is common for data acquisition systems to require interleaving of streams on the same link (e.g. streaming data and streaming register access). Further, this paper presents a way to leverage existing FPGA harden IP blocks to achieve a robust, low latency 100 Gb/s point-to-point link with minimal programmable logic overhead geared towards the needs of data acquisition systems with interleaved streaming requirements.

47 OTHER INSTRUMENTATION↗
DOE OSTI2024

Growth and characterization of ferromagnetic Ga 2 O 3 :(Cr, Mn)

The goal of this Exploratory Express project was to explore the possibility of tunable ferromagnetism in Mn or Cr incorporated epitaxial Ga 2 O 3 films. Tunability of magnetic properties can enable novel applications in spintronics, quantum computing, and magnetism-based logics by allowing control of magnetism down to the nanoscale. Carriers (electrons or holes) mediated ferromagnetic ordering in semiconductor can lead to tunable ferromagnetism by leveraging the tunability of carrier density with doping level, gate electric field, or optical pumping of the carriers. The magnetic ions (Cr or Mn) in Ga 2 O 3 act as localized spin centers which can potentially be magnetically coupled through conduction electrons to enable ferromagnetic ordering. Here we investigated tunable ferromagnetism in beta Ga 2 O 3 semiconductor host with various n-doping levels by incorporating 2.4 atomic percent Mn or Cr. The R&D approach involved growth of epitaxial Ga 2 O 3 film on sapphire or Ga 2 O 3 substrate, implantation of Mn or Cr ions, annealing of the samples post implantation, and magnetic measurements. We studied magnetic behavior of Mn:Ga 2 O 3 as a function of different n-doping levels and various annealing temperatures. The vibrating sample magnetometry (VSM) measurement exhibited strong ferromagnetic signals from the annealed Mn:Ga 2 O 3 sample with n-doping level of 5E19 cm -3 . This ferromagnetic behavior disappears from Mn:Ga 2 O 3 when the n-doping level is reduced to 5E16 cm -3 . Although these results are to be further verified by other measurement schemes due to the observation of background ferromagnetism from the growth substrate, these results indicate the possibility of tunable ferromagnetism in Mn:Ga 2 O 3 mediated by conduction electrons.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
NASA NTRS1995

Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.

Russinoff, David M.↗
NASA NTRS2016

R2U2 in Space: System and Software Health Management for Small Satellites

In order for small but complex systems like rovers, SmallSats, or Unmanned Aircraft (UAS) to operate autonomously, they must have a real-time solution for assessing their own system health. System and Software Health Management (SHM) enables better detection of faulty sensors and software problems, and enables better fault management including mitigation of unpredicted fault scenarios in the absence of a human on-board. In recent work, we have developed a Responsive, Realizable, Unobtrusive Unit (R2U2) for on-board SHM of autonomous UAS and demonstrated its ability to detect faults during flight time. These faults, from sensor failures, to software problems, to malicious security attacks, can present as transient temporal faults that even humans are challenged to find. An R2U2 congfiuration is a modular combination of multiple types of temporal logic runtime observers with fault-specic Bayesian Nets and sensor filters. R2U2 reasons about both on-board hardware and software components; R2U2 itself can be instantiated as an independent FPGA (Field-Programmable Gate Array)-based conguration or as a software component running independently from other software on-board. Small satellites, such as CubeSats, also require on-board SHM and failure mitigation, as limited telemetry bandwidth does not allow the transmission of the entire system state for ground-based health management. However, the autonomous operation of satellites brings a set of challenges different from UAS, including the effects of radiation on non-rad-hard, low-cost components, and the harsher environment of space. We surmise that a new extension of R2U2 could be adapted to help better detect, for example, radiation errors in cheaper COTS (Commercial Off the Shelf) (not rad-hard) components often used in small space systems. Since small satellites often operate in coordination, we will also examine new ways of distributed monitoring of their communication and cooperation and real-time detection of off-nominal situations utilizing multiple satellites. This talk will discuss preliminary work and ideas for building on terrestrial success of system and software health management for the harsher, and differently challenging, environment of space.

Runtime Verification & Validation↗
NASA NTRS1990

GaAs VLSI for aerospace electronics

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Larue, G.↗
NASA NTRS2008

Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Reinhart, Richard C.↗
NASA NTRS2013

Towards Real-time, On-board, Hardware-Supported Sensor and Software Health Management for Unmanned Aerial Systems

Unmanned aerial systems (UASs) can only be deployed if they can effectively complete their missions and respond to failures and uncertain environmental conditions while maintaining safety with respect to other aircraft as well as humans and property on the ground. In this paper, we design a real-time, on-board system health management (SHM) capability to continuously monitor sensors, software, and hardware components for detection and diagnosis of failures and violations of safety or performance rules during the flight of a UAS. Our approach to SHM is three-pronged, providing: (1) real-time monitoring of sensor and/or software signals; (2) signal analysis, preprocessing, and advanced on the- fly temporal and Bayesian probabilistic fault diagnosis; (3) an unobtrusive, lightweight, read-only, low-power realization using Field Programmable Gate Arrays (FPGAs) that avoids overburdening limited computing resources or costly re-certification of flight software due to instrumentation. Our implementation provides a novel approach of combining modular building blocks, integrating responsive runtime monitoring of temporal logic system safety requirements with model-based diagnosis and Bayesian network-based probabilistic analysis. We demonstrate this approach using actual data from the NASA Swift UAS, an experimental all-electric aircraft.

System & Software Health Management↗
DOE OSTI2022

Experimental demonstration of continuous quantum error correction

The storage and processing of quantum information are susceptible to external noise, resulting in computational errors. A powerful method to suppress these effects is quantum error correction. Typically, quantum error correction is executed in discrete rounds, using entangling gates and projective measurement on ancillary qubits to complete each round of error correction. Here we use direct parity measurements to implement a continuous quantum bit-flip correction code in a resource-efficient manner, eliminating entangling gates, ancillary qubits, and their associated errors. An FPGA controller actively corrects errors as they are detected, achieving an average bit-flip detection efficiency of up to 91%. Furthermore, the protocol increases the relaxation time of the protected logical qubit by a factor of 2.7 over the relaxation times of the bare comprising qubits. Our results showcase resource-efficient stabilizer measurements in a multi-qubit architecture and demonstrate how continuous error correction codes can address challenges in realizing a fault-tolerant system.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
NASA NTRS1982

High temperature LSI

Integrated injection logic (1,2) technology for reliable operation under a -55 C to +300 C, temperature range is discussed. Experimental measurements indicate that an 80 mv signal swing is available at 300 C with 100 micro A injection current per gate. In addition, modeling results predict how large gate fan-ins can decrease the maximum thermal operational limits. These operational limits and the longterm reliability factors associated with device metallization are evaluated via specialized test mask.

Dening, D. C.↗
DOE OSTI2019

Methods for diagnosing and quantifying double pulsing in a Uranium Neutron Collar system using shift register logic

Double pulsing in neutron coincidence counters is the result of a pulse processing chain-3He proportional counter timing incompatibility known to nondestructive assay system designers. It is not currently widely acknowledged, or accounted for, in the user community. However, it is gaining attention as list mode data acquisition and analysis becomes more commonly used for system diagnostics, revealing features that have been overlooked by historic timing gate selection using traditional shift register data acquisition methods. Double pulsing increases the apparent number of measured neutron events from a source. Therefore, it may contribute to a falsely increased count rate if present at the operational high voltage used when assaying samples, even with set predelays. The authors have previously studied the effects of double pulsing, using list mode data acquisition and analysis on neutron pulse trains in three common neutron coincidence counting systems used in routine measurements for international safeguards: a Canberra Industries JCC-71 Neutron Coincidence Collar, a variant on the Canberra Industries JCC-51 Active Well Neutron Coincidence Counter (the Large Volume Active Well Neutron Coincidence Counter), and an AnTech Inc. N2071 Neutron Coincidence Collar. We find that this non-ideal behavior was isolated to the Amptek A111 Charge Sensitive Preamplifier & Discriminator chip used in both the Canberra Industries and Antech systems. The double pulsing fraction was calculated in post-analysis for various high voltage settings in these A111-based systems, assuming no predelay settings. In this work, the authors expand upon this identification and analysis to make it more translatable between list mode data acquisition and analysis and shift register-based analysis. By investigating the double pulsing fractions in a JCC-71 Uranium Neutron Collar as a function of predelay settings, as well as describing and performing alternative tests and analyses to diagnose and quantify the double pulsing using shift register logic, this work hopes to complete the picture of double pulsing identification and analysis.

Safeguards↗
NASA NTRS1986

Ulysses: A functional description and simulation software system

Current design tools for digital circuits and systems are not well-integrated among the behavioral, gate, and transistor levels of design. Ulysses is a prototype software system that consists of a description language, a description compiler, and a simulator that make no distinction among these levels. The language is uniform over the entire range of logical descriptions, the description is hierarchical with no fundamental restrictions on depth or mixing of levels, and the simulator is fully integrated with the description. The structure of the language, compiler, and simulator are described in terms of their relationships to the abstractions of physical systems that are made in order to create logical descriptions and models of behavior.

Griswold, T. W.↗
DOE OSTI2023

Wafer-scale growth of two-dimensional, phase-pure InSe

Two-dimensional (2D) indium monoselenide (InSe) has attracted significant attention as an ultrathin III–VI semiconductor with a combination of favorable attributes that are comparable to those of III–V semiconductors and van der Waals 2D transition-metal dichalcogenides. Nevertheless, there has been no demonstration of large-area synthesis of 2D InSe due to the complexity of the binary In-Se system and the difficulties in promoting lateral growth. Here, we report the polymorph-selective synthesis of epitaxial 2D InSe by metal-organic chemical vapor deposition (MOCVD) over 2-in wafers. We achieve polymorph-selective epitaxial growth of InSe on c-plane sapphire via flow modulation to control the Se/In ratio. The layer-by-layer growth allows thickness control with tunable optical properties comparable to those of bulk crystals. We also demonstrate gate-tunable electrical transport with a field-effect mobility comparable to that of single-crystalline flakes. Importantly, these results indicate that InSe grown by MOCVD could be an effective channel material for back-end-of-line integration in logic transistors.

2D materials↗
NASA NTRS1982

Electron lithography STAR design guidelines. Part 2: The design of a STAR for space applications

The STAR design system developed by NASA enables any user with a logic diagram to design a semicustom digital MOS integrated circuit. The system is comprised of a library of standard logic cells and computr programs to place, route, and display designs implemented with cells from the library. Also described is the development of a radiation-hard array designed for the STAR system. The design is based on the CMOS silicon gate technology developed by SANDIA National Laboratories. The design rules used are given as well as the model parameters developed for the basic array element. Library cells of the CMOS metal gate and CMOS silicon gate technologies were simulated using SPICE, and the results are shown and compared.

Trotter, J. D.↗
NASA NTRS2010

Flexible Peripheral Component Interconnect Input/Output Card

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Bigelow, Kirk K.↗
DOE OSTI2026

SAIL Field Campaign X-Band Precipitation Radar Seasonal Surface Hydrometeor Phase Classification Value-Added Product Report

The Surface Atmosphere Integrated Field Laboratory (SAIL) campaign generated an unprecedented, multisensory record of cold-season precipitation in the Upper Colorado River Basin (UCRB). To complement the Surface Quantitative Precipitation Estimation (SQUIRE) snow water equivalent (SWE) product derived from the Colorado State University (CSU) X-band radar, a hydrometeor phase classification data set was developed to systematically identify phase of the near-surface precipitation. The algorithm uses Corrected Moments in Antenna Coordinates (CMAC) fields with semi-supervised classification (SSC) and fuzzy-logic hydrometeor classification (FHC) methods and maps hydrometeor classes to a compact set of phase classes suitable for Quantitative Precipitation Estimation (QPE) and hydrologic applications. We used SQUIRE grid projections to mitigate beam-blockage issues by selecting the near-surface gates for each beam as well as to make it directly usable for the QPE products.

54 ENVIRONMENTAL SCIENCES↗
DOE OSTI2023

AlGaN High Electron Mobility Transistor for High-Temperature Logic

Here we report on AlGaN high electron mobility transistor (HEMT)-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature-dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data (from 30°C to 500°C) revealed the reference GaN-channel HEMT experienced a 6.9x reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200-nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.

42 ENGINEERING↗
NASA NTRS2008

Hardware Architecture Study for NASA's Space Software Defined Radios

This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Reinhart, Richard C.↗