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This presentation, part of the ADMS Test Bed Webinar Series, discusses how to accelerate industry adoption of ADMS to improve normal operations with high levels of distributed energy resources (DERs) and improve resilience and reliability.
The PIP-II timing system is planned to be a two-part system consisting of a global timing system (referred to as ACLK) that provides high level, event-based timing for the whole Fermilab accelerator complex while the second part is a RF synchronized clock system unique to the PIP-II Linac itself (referred to as LCLK). The ACLK System will make use of an external 10 MHz GPS based signal source as a reference for its 650 MHz phase lock as it is the reference frequency for the TCLK output of the system (needed to support legacy hardware around complex). The LCLK System will use a PIP-II Linac RF reference (162.5 MHz) from the Linac LLRF system to allow beam synchronized event placement. Both the ACLK and LCLK systems will have a clock output with a data frame of 16 event bits + 32 data bits with frames broadcast at 650 MHz, phase locked to the 10MHz reference in the case of ACLK and the PIP-II LLRF sourced 162.5 MHz reference in the case of LCLK.
Today’s data-driven analytics and machine learning workload have been largely driven by the General-PurposeGraphics Processing Units (GPGPUs). To accelerate dense matrix multiplications on the GPUs, Tensor Core Units (TCUs) have been introduced in recent years. In this paper, we study linear-algebra-based and vertex-centric algorithms for various graph kernels on the GPUs with an objective of applying this new hardware feature to graph applications. We identify the potential stages in these graph kernels that can be executed on the Tensor Core Units. In particular, we leverage the reformulation of the reduction and scan operations in terms of matrix multiplication [1]on the TCUs. We demonstrate that executing these operations on the TCUs, available inside different graph kernels, can assist in establishing an end-to-end pipeline on the GPGPUs without depending on hand-tuned external libraries and still can deliver comparable performance for various graph analytics.
Abstract Quantum kernel methods show promise for accelerating data analysis by efficiently learning relationships between input data points that have been encoded into an exponentially large Hilbert space. While this technique has been used successfully in small-scale experiments on synthetic datasets, the practical challenges of scaling to large circuits on noisy hardware have not been thoroughly addressed. Here, we present our findings from experimentally implementing a quantum kernel classifier on real high-dimensional data taken from the domain of cosmology using Google’s universal quantum processor, Sycamore. We construct a circuit ansatz that preserves kernel magnitudes that typically otherwise vanish due to an exponentially growing Hilbert space, and implement error mitigation specific to the task of computing quantum kernels on near-term hardware. Our experiment utilizes 17 qubits to classify uncompressed 67 dimensional data resulting in classification accuracy on a test set that is comparable to noiseless simulation.
FPGAs are increasingly common in modern applications, and cloud providers now support on-demand FPGA acceleration in datacenters. Applications in datacenters run on virtual infrastructure, where consolidation, multi-tenancy, and workload migration enable economies of scale that are fundamental to the provider's business. However, a general strategy for virtualizing FPGAs has yet to emerge. While manufacturers struggle with hardware-based approaches, we propose a compiler/runtime-based solution called Synergy. We show a compiler transformation for Verilog programs that produces code able to yield control to software atsub-clock-tickgranularity according to the semantics of the original program. Synergy uses this property to efficiently support core virtualization primitives: suspend and resume, program migration, and spatial/temporal multiplexing, on hardware which is availabletoday.We use Synergy to virtualize FPGA workloads across a cluster of Intel SoCs and Xilinx FPGAs on Amazon F1. The workloads require no modification, run within 3--4x of unvirtualized performance, and incur a modest increase in FPGA fabric usage.
Context: This webinar featured two presentations examining quantum computing and its complex implications across the energy, water, and materials sectors. Olivier Ezratty introduced quantum computing, its anticipated applications and added value, and the hardware required to support these systems. He also discussed their energy demands and the role of the Quantum Energy Initiative in developing an interdisciplinary research field focused on these challenges. David McCollum then explored the opportunities and multisectoral challenges associated with next-generation, quantum-accelerated data centers, including their potential energy and resource impacts and the infrastructure chokepoints that could emerge. Together, the presentations emphasized the need for long-term planning and cross-cutting research collaboration as quantum computing technologies continue to develop. Presenters: Olivier Ezratty (Quantum Energy Initiative); David McCollum (Oak Ridge National Laboratory) Moderator: Patrick M. Reed (MSD CoP Facilitation Team); Gokul Iyer (Pacific Northwest National Laboratory) This webinar was held on: July 9th, 2026 from 1:00–2:30 PM EDT.
As computing systems approach the limits of traditional silicon technology, the diminishing returns in performance per watt present a significant barrier to sustaining growth in HPC. From a large-scale scientific supercomputing facility point of view, we propose a multifaceted strategy toward specialized hardware and architectures that are optimized for energy efficiency in specific applications. We also emphasize the need for integrating energy-aware practices across all levels of HPC, from system design and software development to operational policies. We discuss strategic opportunities such as the adoption of application-specific accelerators, the development of energy-efficient algorithms, and the implementation of data-driven operational analytics. Our goal is to develop a comprehensive roadmap ensuring that future leadership systems at OLCF can meet scientific demands while operating within stringent energy budgets, thereby supporting sustainable computing growth.
Quantum readout and control is a fundamental aspect of quantum computing that requires accurate measurement of qubit states. Errors emerge in all stages, from initialization to readout, and identifying errors in post-processing necessitates resource-intensive statistical analysis. In our work, we use a lightweight fully-connected neural network (NN) to classify states of a transmon system with no prior processing. Our NN accelerator yields higher fidelities (92%) than the classical matched filter method (84%). By exploiting the natural parallelism of NNs and their placement near the source of data on field-programmable gate arrays (FPGAs), we can achieve ultra-low latency on the Quantum Instrumentation Control Kit (QICK). Integrating machine learning methods on QICK opens several pathways for efficient real-time processing of quantum circuits.
MLIR (Multi-Level Intermediate Representation), is an extensible compiler framework that supports high-level data structures and operation constructs. These higher-level code representations are particularly applicable to the artificial intelligence and machine learning (AI/ML) domain, allowing developers to more easily support upcoming heterogeneous AI/ML accelerators and develop flexible domain specific compilers/frameworks with higher-level intermediate representations (IRs) and advanced compiler optimizations. The result of using MLIR within the LLVM compiler framework is expected to yield significant improvement in the quality of generated machine code, which in turn will result in improved performance and hardware efficiency
Software repository for the Caspian neuromorphic system. In order to deploy small, low-power spiking neural networks at the edge, there needs to be 1) an FPGA design for an event simulator to evaluate these neural networks as well as 2) a high-performance cycle-accurate simulator for training these spiking neural networks. This software package solves these problems by providing the Caspian simulator and the µCaspian hardware design in SystemVerilog.
In high energy physics and nuclear physics experiments particularly the ones based on particle accelerator, the data rate from the detector is usually in the order of Terabytes per second. This high throughput data from detector front-end electronics need to be transmitted to the back-end computing farm for high level event selection and building. A Data Acquisition (DAQ) system with features of high-density, scalable, easily upgradeable is crucial to simplify the readout architecture of whole experiment. This paper will introduce the design of a generic high bandwidth PCIe card which can be used as the important input output card in a scalable DAQ system. It can factorize front-end electronics from data handling, and reduce amount of custom hardware in favor of scalable detectorindependent commercial hardware and software. Besides the 48 channels of bidirectional high speed fiber optical links with frontends, it also supports to synchronize with the experiment timing system, and to fanout the clock and trigger information with a fixed latency to the front-end electronics.
In recent years, applications of quantum simulation have been developed to study the properties of strongly interacting theories. This has been driven by two factors: on the one hand, needs from theorists to have access to physical observables that are prohibitively difficult to study using classical computing; on the other hand, quantum hardware becoming increasingly reliable and scalable to larger systems. In this work, we discuss the feasibility of using quantum optical simulation for studying scattering observables that are presently inaccessible via lattice QCD and are at the core of the experimental program at Jefferson Laboratory, the future Electron-Ion Collider, and other accelerator facilities. We show that recent progress in measurement-based photonic quantum computing can be leveraged to provide deterministic generation of required exotic gates and implementation in a single photonic quantum processor. Published by the American Physical Society 2024
As GPU-accelerated high-performance computing (HPC) systems approach exascale performance, controlling energy consumption without compromising throughput is essential. Architectures such as the AMD MI250X-based Frontier supercomputer provide runtime mechanisms like frequency and power capping, enabling energy tuning without modifying application code. Although both target energy reduction, they operate via distinct hardware control paths and influence workloads differently. We present a comprehensive evaluation of these strategies on a leadership-class system using diverse HPC proxy applications representative of production workloads. Our study analyzes performance–energy trade-offs across multiple capping levels, node counts (1 and 32), and application profiles. Results show that frequency capping generally achieves higher energy efficiency and scalability, with gains of up to 13.2% without performance loss, while power capping is more effective for single-node runs or bursty GPU utilization. We also provide practical guidelines to help system administrators and users balance energy efficiency and performance in large-scale scientific workloads.
Understanding parallel algorithms is crucial for accelerating scientific simulations on complex, distributed memory, high-performance computers. Modern algorithm classification approaches learn semantics directly from source code to differentiate between algorithms, however, accessing source code is not always possible. We can learn about parallel algorithms from observing their performance, as programs running the same algorithms and using the same hardware should exhibit similar performance characteristics. We present an approach to learn algorithm classes from parallel performance data directly in order to classify algorithms without access to the source code. We extend previous work to enable classifying parallel sorting algorithms using automatic instrumentation instead of requiring manual region annotations in the source code. In this work, we design and demonstrate a study for classification of parallel sorting algorithms using parallel performance data collected from automatic instrumentation, and evaluate the performance of our new methodology on classification. We leverage Caliper to collect the performance data, Thicket for our exploratory data analysis (EDA), and PyTorch and Scikit-learn to evaluate the effectiveness of random forests, support vector machines (SVMs), decision trees, neural networks, and logistic regressions on parallel performance data. Additionally, we study noise in parallel performance data, whether the removal of noise and pre-processing of the data is necessary to accurately classify parallel sorting algorithms, and determine the effectiveness of features created from performance data. In conclusion, we demonstrate classification accuracy for these five different models of up to 97.7% across four different parallel algorithm classes.
Self-driving laboratories (SDLs) promise an accelerated application of the scientific method. Through the automation of experimental workflows, along with autonomous experimental planning, SDLs hold the potential to greatly accelerate research in chemistry and materials discovery. This review provides an in-depth analysis of the state-of-the-art in SDL technology, its applications across various scientific disciplines, and the potential implications for research and industry. This review additionally provides an overview of the enabling technologies for SDLs, including their hardware, software, and integration with laboratory infrastructure. Most importantly, this review explores the diverse range of scientific domains where SDLs have made significant contributions, from drug discovery and materials science to genomics and chemistry. We provide a comprehensive review of existing real-world examples of SDLs, their different levels of automation, and the challenges and limitations associated with each domain.
The Jefferson Lab LLRF 3.0 system is being developed to replace legacy LLRF systems in the CEBAF accelerator. The new design builds upon 25 years of design and operational RF control experience, and our recent collaboration in the design of the LCLSII LLRF system. The new cavity control algorithm is a fully functional phase and amplitude locked Self Exciting Loop (SEL). This paper discusses the progress of the LLRF 3.0 hardware design, FPGA firmware development, User Datagram Protocol (UDP) operation, and recent LLRF 3.0 system tests on the CEBAF Booster cryomodule in the Upgrade Injector Test Facility (UITF).
Recent years have seen renewed interest and activities in developing SRF cavity materials based on thin film technologies. In this framework, considerable progress has been achieved in the development of high quality films and layered structures along with associated deposition techniques such as ECR, HiPIMS, and ALD. Beyond cavity applications, the developments in SRF thin film technologies find a variety of applications in the fields of superconducting metamaterials, electronics, sensors and quantum devices. High quality Nb films with high RRR open the way for enhanced coherence times for quantum qbits. Other SRF thin films such as NbTiN are developed for superconducting backend processes for future generations of computing hardware and radiation-hard sensors for nuclear and high-energy physics. The unifying theme across these technologies is that the same physics and material properties such as extreme low loss, stability, and manufacturability are required. This talk will present an overview of the emerging applications of SRF films and structures beyond accelerator cavities.
Polymer electrolyte membrane fuel cells (PEMFC) show substantial promise for their application in electric vehicles. For large-scale manufacturing of PEMFCs, roll-to-roll coated gas-diffusion-electrodes (GDE) offer certain advantages over other production pathways. Procedures including hot pressing and coating an ionomer overlayer may be necessary for this manufacturing pathway to enable a suitable catalyst layer/membrane interface. The same procedures may potentially introduce membrane irregularities, especially when thin membranes are used. Limited understanding exists regarding if and to what extent such irregularities impact PEMFC performance and lifetime, and therefore be considered defects. In this study, NREL's customized fuel cell hardware that enables quasi in-situ infrared (IR) thermography studies was utilized to visualize spatial hydrogen crossover and identify membrane irregularities that originated from the GDE-based MEA fabrication process. The structure of these membrane irregularities was investigated by scanning electron microscopy (SEM) and its impact on initial H2/air performance was determined. Accelerated stress testing (AST) revealed that these irregularities develop into failure point locations. These results were validated across many MEAs with identified process-induced membrane irregularities. By selecting specific gas diffusion media properties and by fine tuning the MEA hot pressing parameters, the formation of such membrane irregularities was mitigated.