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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 397 records · Page 22
All sourcesNASA NTRSDOE OSTI
NASA NTRS2015

Extreme Oxidative Durability of TBCs on Ti2AlC MAX Phases

APS and PS-PVD YSZ thermal barrier coatings, applied directly to oxidation resistant Ti2AlC substrates, were oxidized in interrupted furnace tests. Temperature was advanced in 50C intervals from 1100 to 1300C, each 500 h long with eleven cooling cycles. Damage only initiated on the APS coating at 1300C after 15 h, with complete delamination after 500 h. The PS-PVD coating survived all testing. Weight change and metallographic analyses indicate that the YSZ-Ti2AlC systems sustained alumina scale growth of 30-40 m. In comparison, widely used Pt-aluminide bondcoats on single crystal superalloy turbine blades exhibit TBC lives equivalent to alumina scale growth up to 7 m, equivalent to just 200 h at 1200C. It is demonstrated that 25x TBC life improvement (or 180C temperature increase) resulted from the close CTE match of Ti2AlC with those of alumina and YSZ.

protective coating↗
NASA NTRS2016

Atmosphere Processing Module Automation and Catalyst Durability Analysis for Mars ISRU Pathfinder

The Mars In-Situ Resource Utilization Pathfinder was designed to create fuel using components found in the planet’s atmosphere and regolith for an ascension vehicle to return a potential sample return or crew return vehicle from Mars. The Atmosphere Processing Module (APM), a subunit of the pathfinder, uses cryocoolers to isolate and collect carbon dioxide from Mars simulant gas. The carbon dioxide is fed with hydrogen into a Sabatier reactor where methane is produced. The APM is currently undergoing the final stages of testing at Kennedy Space Center prior to process integration testing with the other subunits of the pathfinder. The automation software for the APM cryocoolers was tested and found to perform nominally. The catalyst used for the Sabatier reactor was investigated to determine the factors contributing to catalyst failure. The results from the catalyst testing require further analysis, but it appears that the rapid change in temperature during reactor start up or the elevated operating temperature is responsible for the changes observed in the catalyst.

Atmosphere Processing Module↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 C

We have reported SiC integrated circuits (IC's) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 C [1, 2]. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 C [3]. However, this thermal ramp was not ended until a peak temperature of 880 C (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology. Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 C. In one test, the temperature was ramped and then held at 727 C, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 C before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 C (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 C.

JFET↗
NASA NTRS2016

Experimental Durability Testing of 4H SiC JFET Integrated Circuit Technology at 727 Degrees Centigrade

We have reported SiC integrated circuits (ICs) with two levels of metal interconnect that have demonstrated prolonged operation for thousands of hours at their intended peak ambient operational temperature of 500 degrees Centigrade. However, it is recognized that testing of semiconductor microelectronics at temperatures above their designed operating envelope is vital to qualification. Towards this end, we previously reported operation of a 4H-SiC JFET IC ring oscillator on an initial fast thermal ramp test through 727 degrees Centigrade. However, this thermal ramp was not ended until a peak temperature of 880 degrees Centigrade (well beyond failure) was attained. Further experiments are necessary to better understand failure mechanisms and upper temperature limit of this extreme-temperature capable 4H-SiC IC technology.Here we report on additional experimental testing of custom-packaged 4H-SiC JFET IC devices at temperatures above 500 degrees Centigrade. In one test, the temperature was ramped and then held at 727 degrees Centigrade, and the devices were periodically measured until electrical failure was observed. A 4H-SiC JFET on this chip electrically functioned with little change for around 25 hours at 727 degrees Centigrade before rapid increases in device resistance caused failure. In a second test, devices from our next generation 4H-SiC JFET ICs were ramped up and then held at 700 degrees Centigrade (which is below the maximum deposition temperature of the dielectrics). Three ring oscillators functioned for 8 hours at this temperature before degradation. In a third experiment, an alternative die attach of gold paste and package lid was used, and logic circuit operation was demonstrated for 143.5 hours at 700 degrees Centigrade.

Silicon Carbide↗
NASA NTRS2018

Insights into Space Solar Cell Durability Using SPICE Simulation Seeded by Current-Voltage Characteristics Parametrized Using the Lambert W Special Function

We developed and validated an automated routine for the fitting of I-V curve data to the single diode model according to an exact analytical solution. Our fitting routine was validated to show good noise immunity and high accuracy usingsimulated values from LTSPICE. We are thus able to automate parameter extraction from a dataset or arbitrary size. This parameterization allows for better simulation of performance of real cells and arrays and provides utility for a host of applications relevant to space arrays. We will use this methodology to determine the array performance of radiated cells over time, and simulate the performance of the arrays with bypass diodes and power electronics.

Solar Cell↗
NASA NTRS2018

Room Temperature Total-Ionizing Dose Testing of Glenn Research Center (GRC) 500 °C Durable 4H-SiC JFET IC Technology

The purpose of this testing was to obtain total ionizing dose (TID) information about custom-built research prototype silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) capable of prolonged operation in extremely high-temperature (500 degrees Centigrade) environments. The circuits included ring oscillators and operational amplifiers as well as individual n-channel JFETs. This technology is being considered for use in high temperature, high pressure applications such as Long-Lives Surface System Explorer (LLISSE). These devices were developed at NASA Glenn Research Center (GRC). Testing occurred from July 9th-July 13th, 2018.

Radiation↗
NASA NTRS2019

Room Temperature Radiation Testing of a 500 °C Durable 4H-SiC JFET Integrated Circuit Technology

Total ionizing dose (TID) and single-event effect (SEE) room-temperature radiation test results are presented for developmental prototype 4H-SiC junction field effect transistor (JFET) semiconductor integrated circuits (ICs) that have demonstrated prolonged operation in extremely high-temperature (500 °C) environments. The devices tested demonstrated over 7 Mrad(Si) TID tolerance and no destructive SEE susceptibility.

Lauenstein, Jean-Marie↗
NASA NTRS2019

Durability of YSZ Coated Ti2AlC in 1300°C Mach 0.3 Burner Rig Tests

A thermal barrier coating system survived burner rig testing at 1300°C for 500 h. A 160 µm thick YSZ coating was applied to a Ti2AlC MAX phase sample by PS-PVD and tested face-on in an atmospheric Mach 0.3 jet fuel burner, using 5-h thermal cycles. No TBC spallation or recession was observed, only a 2.4 mg/sq. cm mass gain. The modest weight gain precluded severe volatility losses under high velocity burner conditions. The coating surface exhibited colonies of (111) flourite fiber-textured columns separated by craze patterns, with no visible moisture attack. The metastable tetragonal t' YSZ phase was obtained initially, transitioning to teq and cubic YSZ, but with little detrimental monoclinic. The thickness of the alumina TGO was ~21-23 m under the heated YSZ face and ~13-15 m on the uncoated, cooler backside. The backside exhibited removal of initial transient TiO2 nodules and etching of the underlying Al2O3 scale by volatile hydroxides in high temperature, high velocity water vapor. Aerodynamic forces produced some bending of the cantilevered sample due to creep. The test indicated exceptional stability of YSZ coatings on Ti2AlC under turbine conditions.

Smialek, J.↗
NASA NTRS2021

Development and Characterization of Lightweight Durable Composite Conductor for Cables

Sustainable aviation in the form of electrified propulsion is likely to lead to an increase in the electrical assets contained within a single aircraft. As a result, it is desirable to design light weight conductor materials, thus reducing the payload of components like motor windings, low voltage signal cables, and transmission cables for data and power. One approach involves replacing pure Cu wiring with metalized CNT composites. This paper evaluates a framework for modeling overall conductivity and current sharing within such composites. Processing methods and parameters were refined. Select electroplated samples outperformed pure Cu in conductivity and had comparable ultimate tensile strengths. Tensile strengths are expected to improve with an additional densification step during processing. Acoustic emission data was used to predict the failure mechanism of the composite. Theories explaining improved intrinsic conductivity are discussed, with a focus on chemical and mechanical interactions at the Cu-CNT interface. These include Cu infiltration of CNT crevices, CNT oxidation, activity at defects in CNT walls, and the release of carbide-forming metals from CNT walls. Validating any or all these theories will require further work replicating data, collecting electron micrographs and conducting chemical analyses.

Metalized CNT↗
NASA NTRS2020

Durability of YSZ coated Ti2AlC in 1300°C high velocity burner rig tests

A thermal barrier coating system survived 500 h in cyclic burner rig tests at 1300°C, exceeding the life of all previous systems. An yttria stabilized zirconia (7YSZ) thermal barrier coating (TBC) was plasma sprayed on the oxidation resistant Ti2AlC MAX phase and tested in a jet fuel burner. No coating spallation or recession was observed, only a 2.4 mg/sq.cm mass gain due to typical cubic Al2O3 oxidation kinetics. The modest weight gain contrasted with large TBC spallation or oxide volatility losses that might occur under cyclic, high velocity (~100 m/s) burner conditions. The coating surface exhibited colonies of [111]flourite fiber-textured columns separated by craze crack patterns, but with no visible moisture attack. The thickness of the alumina scale under the YSZ face was >20 μm, more than twice that formed on TBC/superalloy systems at failure. TiO2 nodules, initially formed on the uncoated backside, were then removed as volatile hydroxides formed in high temperature, high velocity water vapor (~10%). Overall, the test indicated the exceptional stability of the YSZ/Ti2AlC system under turbine conditions, due in large part to good thermal expansion matching.

alumina, MAX phases, thermal barrier coatings (TBC↗
NASA NTRSDate not supplied

Early Burn-In Parasitic Conduction in 500 °C Durable SiC JFET ICs

All prior reports of long-term 500 °C operation of SiC JFET-R ICs have noted the existence of an initial “burn-in” period of changes in measured electrical characteristics for the first few hundred hours oven-testing. This work reports measurements of “burn-in parasitic MOSFET conduction” that can substantially impact the performance of some circuits during initial heat-up of JFET ICs, but then subsequently disappears after a few hours of operation at 500 °C. The behavior appears generally consistent with the known MOS phenomenon of bias-temperature driven redistribution of mobile ionic contamination. Approaches for further mitigating this initial burn-in conduction mechanism are discussed.

silicon carbide↗