Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “digital logic”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 397 records · Page 22
All sourcesNASA NTRSDOE OSTI
NASA NTRS1994

Cell Libraries

A NASA contract led to the development of faster and more energy efficient semiconductor materials for digital integrated circuits. Gallium arsenide (GaAs) conducts electrons 4-6 times faster than silicon and uses less power at frequencies above 100-150 megahertz. However, the material is expensive, brittle, fragile and has lacked computer automated engineering tools to solve this problem. Systems & Processes Engineering Corporation (SPEC) developed a series of GaAs cell libraries for cell layout, design rule checking, logic synthesis, placement and routing, simulation and chip assembly. The system is marketed by Compare Design Automation.

Source record↗
NASA NTRS1975

Space Shuttle flight control system

The Space Shuttle is a control stabilized vehicle with control provided by an all digital, fly-by-wire flight control system. This paper gives a description of the several modes of flight control which correspond to the Shuttle mission phases. These modes are ascent flight control (including open loop first stage steering, the use of four computers operating in parallel and inertial guidance sensors), on-orbit flight control (with a discussion of reaction control, phase plane switching logic, jet selection logic, state estimator logic and OMS thrust vector control), entry flight control and TAEM (terminal area energy management to landing). Also discussed are redundancy management and backup flight control.

Klinar, W. J.↗
NASA NTRS1978

Reconfigurable modular computer networks for spacecraft on-board processing

The core electronics subsystems on unmanned spacecraft, which have been sent over the last 20 years to investigate the moon, Mars, Venus, and Mercury, have progressed through an evolution from simple fixed controllers and analog computers in the 1960's to general-purpose digital computers in current designs. This evolution is now moving in the direction of distributed computer networks. Current Voyager spacecraft already use three on-board computers. One is used to store commands and provide overall spacecraft management. Another is used for instrument control and telemetry collection, and the third computer is used for attitude control and scientific instrument pointing. An examination of the control logic in the instruments shows that, for many, it is cost-effective to replace the sequencing logic with a microcomputer. The Unified Data System architecture considered consists of a set of standard microcomputers connected by several redundant buses. A typical self-checking computer module will contain 23 RAMs, two microprocessors, one memory interface, three bus interfaces, and one core building block.

Rennels, D. A.↗
NASA NTRS1991

Aid For Simulating Digital Flight Control Systems

DIVERS translator is computer program to convert descriptions of digital flight-control systems (DFCS) into computer program. Language developed to represent design charts of DFCS. Translator converts DIVERS source code into easily transportable language, while minimizing probability that results are affected by interpretation of programmer. Final translated program used as standard of comparison to verify operation of actual flight-control systems. Applicable to simulation of other control systems; for example, electrical circuits and logic processes. Written in C.

Hartman, Richard M.↗
NASA NTRS2005

Event-driven charge-coupled device design and applications therefor

An event-driven X-ray CCD imager device uses a floating-gate amplifier or other non-destructive readout device to non-destructively sense a charge level in a charge packet associated with a pixel. The output of the floating-gate amplifier is used to identify each pixel that has a charge level above a predetermined threshold. If the charge level is above a predetermined threshold the charge in the triggering charge packet and in the charge packets from neighboring pixels need to be measured accurately. A charge delay register is included in the event-driven X-ray CCD imager device to enable recovery of the charge packets from neighboring pixels for accurate measurement. When a charge packet reaches the end of the charge delay register, control logic either dumps the charge packet, or steers the charge packet to a charge FIFO to preserve it if the charge packet is determined to be a packet that needs accurate measurement. A floating-diffusion amplifier or other low-noise output stage device, which converts charge level to a voltage level with high precision, provides final measurement of the charge packets. The voltage level is eventually digitized by a high linearity ADC.

Doty, John P.↗
NASA NTRS1982

A new design approach to achieve a minimum impulse limit cycle in the presence of significant measurement uncertainties

A new design was developed for the Space Shuttle Transition Phase Digital Autopilot to reduce the impact of large measurement uncertainties in the rate signal during attitude control. The signal source, which was dictated by early computer constraints, is characterized by large quantization, noise, bias, and transport lag which produce a measurement uncertainty larger than the minimum impulse rate change. To ensure convergence to a minimum impulse limit cycle, the design employed bias and transport lag compensation and a switching logic with hysteresis, rate deadzone, and 'walking' switching line. The design background, the rate measurement uncertainties, and the design solution are documented.

Martin, M. W.↗
NASA NTRS1989

Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery.

Bunya, George K.↗
NASA NTRS2005

High-Performance Satellite/Terrestrial-Network Gateway

A gateway has been developed to enable digital communication between (1) the high-rate receiving equipment at NASA's White Sands complex and (2) a standard terrestrial digital communication network at data rates up to 622 Mb/s. The design of this gateway can also be adapted for use in commercial Earth/satellite and digital communication networks, and in terrestrial digital communication networks that include wireless subnetworks. Gateway as used here signifies an electronic circuit that serves as an interface between two electronic communication networks so that a computer (or other terminal) on one network can communicate with a terminal on the other network. The connection between this gateway and the high-rate receiving equipment is made via a synchronous serial data interface at the emitter-coupled-logic (ECL) level. The connection between this gateway and a standard asynchronous transfer mode (ATM) terrestrial communication network is made via a standard user network interface with a synchronous optical network (SONET) connector. The gateway contains circuitry that performs the conversion between the ECL and SONET interfaces. The data rate of the SONET interface can be either 155.52 or 622.08 Mb/s. The gateway derives its clock signal from a satellite modem in the high-rate receiving equipment and, hence, is agile in the sense that it adapts to the data rate of the serial interface.

Beering, David R.↗
NASA NTRS1982

Two-dimensional convolute integers for analytical instrumentation

As new analytical instruments and techniques emerge with increased dimensionality, a corresponding need is seen for data processing logic which can appropriately address the data. Two-dimensional measurements reveal enhanced unknown mixture analysis capability as a result of the greater spectral information content over two one-dimensional methods taken separately. It is noted that two-dimensional convolute integers are merely an extension of the work by Savitzky and Golay (1964). It is shown that these low-pass, high-pass and band-pass digital filters are truly two-dimensional and that they can be applied in a manner identical with their one-dimensional counterpart, that is, a weighted nearest-neighbor, moving average with zero phase shifting, convoluted integer (universal number) weighting coefficients.

Edwards, T. R.↗
NASA NTRS1986

A system for the functional testing and simulation of custom and semicustom VLSI chips

A system for the functional testing and simulation of custom and semicustom very large scale integrated (VLSI) chips that are designed using the integrated UNIX-based computer-aided design (CAD) system is described. The testing and simulation system consists of two parts. One of these is a special purpose hardware device that is capable of controlling the digital imputs and outputs on a custom chip. This device, the Digital Microcircuit Functionality Tester (DMFT) system, can be operated by itself or in conjunction with the VAX host computer on the CAD system. The DMFT is integrated into a microprobe station so that these signals can be injected or read from nodes inside the chip, as well as at the pins. The second part of the system is a software package that is installed on the VAX. This software package, logic, includes a full-screen editor for developing chip test sequences and drivers for both the DMFT and the esim logic simulator.

Olson, E. M.↗
NASA NTRS2007

Robust Fuzzy Controllers Using FPGAs

Electro-mechanical device controllers typically come in one of three forms, proportional (P), Proportional Derivative (PD), and Proportional Integral Derivative (PID). Two methods of control are discussed in this paper; they are (1) the classical technique that requires an in-depth mathematical use of poles and zeros, and (2) the fuzzy logic (FL) technique that is similar to the way humans think and make decisions. FL controllers are used in multiple industries; examples include control engineering, computer vision, pattern recognition, statistics, and data analysis. Presented is a study on the development of a PD motor controller written in very high speed hardware description language (VHDL), and implemented in FL. Four distinct abstractions compose the FL controller, they are the fuzzifier, the rule-base, the fuzzy inference system (FIS), and the defuzzifier. FL is similar to, but different from, Boolean logic; where the output value may be equal to 0 or 1, but it could also be equal to any decimal value between them. This controller is unique because of its VHDL implementation, which uses integer mathematics. To compensate for VHDL's inability to synthesis floating point numbers, a scale factor equal to 10(sup (N/4) is utilized; where N is equal to data word size. The scaling factor shifts the decimal digits to the left of the decimal point for increased precision. PD controllers are ideal for use with servo motors, where position control is effective. This paper discusses control methods for motion-base platforms where a constant velocity equivalent to a spectral resolution of 0.25 cm(exp -1) is required; however, the control capability of this controller extends to various other platforms.

Monroe, Author Gene S., Jr.↗
NASA NTRSDate not supplied

Lean Model-Based Systems Engineering on the NASA High-Density Vertiplex Subproject

The High Density Vertiplex (HDV) subproject of NASA’s Advanced Air Mobility (AAM) project adopted Model-Based Systems Engineering (MBSE)in July of 2020, prior to subproject formulation. A small and lean team of HDV Systems Engineers(SE) are utilizing MagicDraw to execute NASA SE processes via MBSE. The SEs learned how to use MagicDraw from scratch and HDV is the first project for which the SEs have utilized MagicDraw. This paper will demonstrate project technical execution via MBSE, utilizing the digital elements built into the SysML (Systems Modeling Language). SysML provides a model-centric means of carrying out the NASA SE common technical processes by providing tools for complete system modeling, including requirements and interface management and design capture. The authors also leverage and extend SysML to perform other SE tasks, such as Verification and Validation (V&V)tracking. MBSE has two main purposes for HDV: 1) documenting the subproject’s logical architecture for distribution outside of the subproject, 2) capturing the subproject’s physical architecture in a single-source-of-truth for use by the subproject’s members. This paper details the challenges, lessons learned, and solutions that were encountered in implementing MBSE in the first iteration on a multi-iteration, full-lifecycle design, build, fly project.

Demetrios Katsaduros↗
NASA NTRSDate not supplied

Lean Model-Based Systems Engineering on the NASA High-Density Vertiplex Subproject

The High Density Vertiplex (HDV) subproject of NASA’s Advanced Air Mobility (AAM) project adopted Model-Based Systems Engineering (MBSE) in July of 2020, prior to subproject formulation. A small and lean team of HDV Systems Engineers (SE) are utilizing MagicDraw to execute NASA SE processes via MBSE. The SEs learned how to use MagicDraw from scratch and HDV is the first project for which the SEs have utilized MagicDraw. This presentation will demonstrate project technical execution via MBSE, utilizing the digital elements built into the SysML (Systems Modeling Language). SysML provides a model-centric means of carrying out the NASA SE common technical processes by providing tools for complete system modeling, including requirements and interface management and design capture. The authors also leverage and extend SysML to perform other SE tasks, such as Verification and Validation (V&V) tracking. MBSE has two main purposes for HDV: 1) documenting the subproject’s logical architecture for distribution outside of the subproject, 2) capturing the subproject’s physical architecture in a single-source-of-truth for use by the subproject’s members. This presentation details the challenges, lessons learned, and solutions that were encountered in implementing MBSE in the first iteration on a multi-iteration, full-lifecycle design, build, fly project.

systems engineering↗
NASA NTRS1978

Studies in optical parallel processing

Threshold and A/D devices for converting a gray scale image into a binary one were investigated for all-optical and opto-electronic approaches to parallel processing. Integrated optical logic circuits (IOC) and optical parallel logic devices (OPA) were studied as an approach to processing optical binary signals. In the IOC logic scheme, a single row of an optical image is coupled into the IOC substrate at a time through an array of optical fibers. Parallel processing is carried out out, on each image element of these rows, in the IOC substrate and the resulting output exits via a second array of optical fibers. The OPAL system for parallel processing which uses a Fabry-Perot interferometer for image thresholding and analog-to-digital conversion, achieves a higher degree of parallel processing than is possible with IOC.

Lee, S. H.↗
NASA NTRS2005

Multifunctional Logic Gate Controlled by Temperature

A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.

Stoica, Adrian↗
NASA NTRS1984

Documentation for the machine-readable version of A Library of Stellar Spectra (Jacoby, Hunter and Christian 1984)

The machine readable library as it is currently being distributed from the Astronomical Data Center is described. The library contains digital spectral for 161 stars of spectral classes O through M and luminosity classes 1, 3 and 5 in the wavelength range 3510 A to 7427 A. The resolution is approximately 4.5 A, while the typical photometric uncertainty of each resolution element is approximately 1 percent and broadband variations are 3 percent. The documentation includes a format description, a table of the indigenous characteristics of the magnetic tape file, and a sample listing of logical records exactly as they are recorded on the tape.

Warren, W. H., Jr.↗
NASA NTRS2005

Multifunctional Logic Gate Controlled by Supply Voltage

A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).

Stoica, Adrian↗
NASA NTRS2003

Multiplexing Technology for Acoustic Emission Monitoring of Aerospace Vehicles

The initiation and propagation of damage mechanisms such as cracks and delaminations generate acoustic waves, which propagate through a structure. These waves can be detected and analyzed to provide the location and severity of damage as part of a structural health monitoring (SHM) system. This methodology of damage detection is commonly known as acoustic emission (AE) monitoring, and is widely used on a variety of applications on civil structures. AE has been widely considered for SHM of aerospace vehicles. Numerous successful ground and flight test demonstrations have been performed, which show the viability of the technology for damage monitoring in aerospace structures. However, one significant current limitation for application of AE techniques on aerospace vehicles is the large size, mass, and power requirements for the necessary monitoring instrumentation. To address this issue, a prototype multiplexing approach has been developed and demonstrated in this study, which reduces the amount of AE monitoring instrumentation required. Typical time division multiplexing techniques that are commonly used to monitor strain, pressure and temperature sensors are not applicable to AE monitoring because of the asynchronous and widely varying rates of AE signal occurrence. Thus, an event based multiplexing technique was developed. In the initial prototype circuit, inputs from eight sensors in a linear array were multiplexed into two data acquisition channels. The multiplexer rapidly switches, in less than one microsecond, allowing the signals from two sensors to be acquired by a digitizer. The two acquired signals are from the sensors on either side of the trigger sensor. This enables the capture of the first arrival of the waves, which cannot be accomplished with the signal from the trigger sensor. The propagation delay to the slightly more distant neighboring sensors makes this possible. The arrival time from this first arrival provides a more accurate source location determination. The multiplexer also identifies which channels are acquired by encoding TTL logic pulses onto the latter portion of the signals. This prototype system was demonstrated using pencil lead break (Hsu-Neilsen) sources on an aluminum plate. It performed as designed providing rapid low noise trigger based switching with encoded channel identification. this multiplexing approach is not limited to linear arrays, but can be easily extended to monitor sensors in planar ot three dimensional arrays. A 32 channel multiplexing system is under development that will allow arbitrary sensor placement. Another benefit of this multiplexing system is the reduction in the expense of data acquisition hardware. In addition, the reduced weight and power requirements are of extreme importance for proposed AE systems on aerospace vehicles.

Prosser, William↗