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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 397 records · Page 22
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

A low-volume, low-mass, low-power UHF proximity micro-transceiver for Mars Exploration

UHF half-duplex micro-transceiver measuring 1 cubic centimeter, weighing less than 10 grams, and operating at 40 mW on receive and 50mW, 300mW, or 3W on transmit is described. The micro-transceiver is being designed for future Mars exploration missions, but can be adapted for other proximity links. It supports transmission rates up to 256 ksps and higher in BPSK or QPSK format for data return and receives command/control instructions at up to 8 ksps. In addition to its low mass/power features, temperature compensated circuit and system design and radiation tolerance allow operation outside of large shielded enclosures, further reducing the mass and complexity of exploration vehicles.

Silicon-on-Sapphire (SOS)↗
NASA NTRS1992

Robot Serviced Space Facility

A robot serviced space facility includes multiple modules which are identical in physical structure, but selectively differing in function. and purpose. Each module includes multiple like attachment points which are identically placed on each module so as to permit interconnection with immediately adjacent modules. Connection is made through like outwardly extending flange assemblies having identical male and female configurations for interconnecting to and locking to a complementary side of another flange. Multiple rows of interconnected modules permit force, fluid, data and power transfer to be accomplished by redundant circuit paths. Redundant modules of critical subsystems are included. Redundancy of modules and of interconnections results in a space complex with any module being removable upon demand, either for module replacement or facility reconfiguration. without eliminating any vital functions of the complex. Module replacement and facility assembly or reconfiguration are accomplished by a computer controlled articulated walker type robotic manipulator arm assembly having two identical end-effectors in the form of male configurations which are identical to those on module flanges and which interconnect to female configurations on other flanges. The robotic arm assembly moves along a connected set or modules by successively disconnecting, moving and reconnecting alternate ends of itself to a succession of flanges in a walking type maneuver. To transport a module, the robot keeps the transported module attached to one of its end-effectors and uses another flange male configuration of the attached module as a substitute end-effector during walking.

Purves, Lloyd R.↗
NASA NTRS1991

Testing interconnected VLSI circuits in the Big Viterbi Decoder

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Onyszchuk, I. M.↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRSDate not supplied

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS2023

Recent Progress in Extreme Environment Durable SiC JFET-R Integrated Circuit Technology

This work updates recent progress made by NASA Glenn Research Center on further advancement of its uniquely durable silicon carbide junction field effect transistor and resistor (SiC JFET-R) integrated circuit (IC) technology since HiTEC 2021. Key fabrication process improvements compared to earlier NASA Glenn IC prototype runs have been ascertained via extensive “back end of line” (BEOL) processing experiments conducted on practice wafers over the past two years. The resulting changes to the BEOL process flow employed in the fabrication of “Generation 12” SiC JFET-R wafers are described. The NASA Glenn SiC JFET-R IC prototype “Generation 12” chipset design realizes significantly higher complexity digital and analog integrated ICs aimed at flexibly implementing a broad variety of mission-enabling extreme-environment electronics demonstrations. SPICE simulations have verified circuit designs ranging from simple amplification of analog sensor signals up through long-duration Venus lander operations and microprocessor-based of electric motor drive.

Silicon Carbide↗
NASA NTRS1996

A Formal Algorithm for Routing Traces on a Printed Circuit Board

This paper addresses the classical problem of printed circuit board routing: that is, the problem of automatic routing by a computer other than by brute force that causes the execution time to grow exponentially as a function of the complexity. Most of the present solutions are either inexpensive but not efficient and fast, or efficient and fast but very costly. Many solutions are proprietary, so not much is written or known about the actual algorithms upon which these solutions are based. This paper presents a formal algorithm for routing traces on a print- ed circuit board. The solution presented is very fast and efficient and for the first time speaks to the question eloquently by way of symbolic statements.

Hedgley, David R., Jr.↗
DOE OSTI2024

Extending the computational reach of a superconducting qutrit processor

Quantum computing with qudits is an emerging approach that exploits a larger, more connected computational space, providing advantages for many applications, including quantum simulation and quantum error correction. Nonetheless, qudits are typically afflicted by more complex errors and suffer greater noise sensitivity which renders their scaling difficult. In this work, we introduce techniques to tailor arbitrary qudit Markovian noise to stochastic Weyl–Heisenberg channels and mitigate noise that commutes with our Clifford and universal two-qudit gate in generic qudit circuits. We experimentally demonstrate these methods on a superconducting transmon qutrit processor, and benchmark their effectiveness for multipartite qutrit entanglement and random circuit sampling, obtaining up to 3× improvement in our results. To the best of our knowledge, this constitutes the first-ever error mitigation experiment performed on qutrits. Our work shows that despite the intrinsic complexity of manipulating higher-dimensional quantum systems, noise tailoring and error mitigation can significantly extend the computational reach of today’s qudit processors.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2020

Sandia National Laboratories FY20 Progress Report

The Energetic Neutrons campaign led by Sandia National Laboratories (SNL) had a successful year testing electronic devices and printed circuit boards (PCBs) under 14 MeV neutron irradiation at OMEGA. During FY20 the Energetic Neutrons campaign increased the number and complexity of experiments, continued collaborations with external organizations, and generated knowledge that supports SNL’s National Security mission. In FY20 the Energetic Neutrons campaign was executed by an early career team led by a new PI. The SNL team members were trained to take over new responsibilities during the shot day to increase the number and complexity of experiments in the campaigns. Also, in FY20 for the first time the Energetic Neutrons campaign had a graduate student contributing with pre and post-irradiation characterizations at SNL of the semiconductor devices irradiated at OMEGA. In FY20 SNL collaborated with the Air Force Nuclear Weapons Center (AFNWC) and supported experiments related to radiation effects in semiconductor devices. SNL also gave the opportunity to ride along to Los Alamos National Laboratory and multiple scientists from MIT and LLE. SNL continued using the last two generations of the Neutron Effects Diagnostics (NEDs) to field active and passive experiments but also redesigned the latest generation of the NEDs to accommodate larger components and improve the vacuum sealing as shown in figure 1a. The redesigned NEDs allowed SNL to perform active tests of a high voltage (HV) PCB for the first time at OMEGA; where signals before, during and after the irradiation were recorded. The HV PCB installed in one of the SNL NEDs is shown in figure 1b where a 3D-printed nosecone was used to check for mechanical and electrical interference. Passive irradiations of multiple components were followed up with leakage current, gain measurements and radiation-induced defect characterization.

42 ENGINEERING↗
NASA NTRS2000

JavaGenes and Condor: Cycle-Scavenging Genetic Algorithms

A genetic algorithm code, JavaGenes, was written in Java and used to evolve pharmaceutical drug molecules and digital circuits. JavaGenes was run under the Condor cycle-scavenging batch system managing 100-170 desktop SGI workstations. Genetic algorithms mimic biological evolution by evolving solutions to problems using crossover and mutation. While most genetic algorithms evolve strings or trees, JavaGenes evolves graphs representing (currently) molecules and circuits. Java was chosen as the implementation language because the genetic algorithm requires random splitting and recombining of graphs, a complex data structure manipulation with ample opportunities for memory leaks, loose pointers, out-of-bound indices, and other hard to find bugs. Java garbage-collection memory management, lack of pointer arithmetic, and array-bounds index checking prevents these bugs from occurring, substantially reducing development time. While a run-time performance penalty must be paid, the only unacceptable performance we encountered was using standard Java serialization to checkpoint and restart the code. This was fixed by a two-day implementation of custom checkpointing. JavaGenes is minimally integrated with Condor; in other words, JavaGenes must do its own checkpointing and I/O redirection. A prototype Java-aware version of Condor was developed using standard Java serialization for checkpointing. For the prototype to be useful, standard Java serialization must be significantly optimized. JavaGenes is approximately 8700 lines of code and a few thousand JavaGenes jobs have been run. Most jobs ran for a few days. Results include proof that genetic algorithms can evolve directed and undirected graphs, development of a novel crossover operator for graphs, a paper in the journal Nanotechnology, and another paper in preparation.

Globus, Al↗
NASA NTRS2001

The Need for Optical Means as an Alternative for Electronic Computing

An increasing demand for faster computers is rapidly growing to encounter the fast growing rate of Internet, space communication, and robotic industry. Unfortunately, the Very Large Scale Integration technology is approaching its fundamental limits beyond which the device will be unreliable. Optical interconnections and optical integrated circuits are strongly believed to provide the way out of the extreme limitations imposed on the growth of speed and complexity of nowadays computations by conventional electronics. This paper demonstrates two ultra-fast, all-optical logic gates and a high-density storage medium, which are essential components in building the future optical computer.

Adbeldayem, Hossin↗
NASA NTRS1961

A Polarization-Diversity Simultaneous-Lobing Angle-Tracking Receiver

This report describes a simultaneous-lobing angle-tracking receiver operating in the 225-260 milli-cycle-per-second telemetry band and employing polarization diversity. Its operation is considered primarily in the context of the Mercury range and tracking of the Mercury capsule. Several methods of providing diversity are briefly considered, and a number of ways of implementing the phase shifts required at one polarization for coherent signal addition are discussed. A prototype receiver is briefly described although circuitry which may be somewhat novel is covered in greater detail. No attempt has been made to include all of the sophistication one might expect in a receiver of this type; circuits have been simplified in some areas where, for example, a manual control can replace an automatic function and reduce complexity. Some conclusions are drawn as to how this receiver might perform in the Mercury environment.

Renhult, W. B.↗
NASA NTRS2021

Infrared Imaging using Sparse Microresonator Arrays and Compressed Sensing

In this work, we present an uncooled infrared (IR) thermal imager featuring a sparse array of resonant pixels that can be monolithically integrated with the readout electronics for long-term operation in high-temperature environments. Each of the detector pixels is made of an IR-sensitive GaN microresonator developed to be operated at up to 500 0C. The pixels are employed in sparse array configuration to allow for routing the signal carrying traces and to ease the routing from pixel to circuit, as well as to reduce the power consumption at the expense of moderate post-processing time and increased complexity to recover the image. Three 128 by 128 sparse resonator arrays with the array densities of 10%, 25% and 37.5% are designed, and used in conjunction with the Compressed Sensing (CS) method to reconstruct complex test images from highly incomplete data. Capabilities and performance metrics of the recovery technique are explored.

Rais-Zadeh, Mina↗
DOE OSTI2026

Recycling of Printed Circuit Boards to Recover Critical Materials

The printed circuit board (PCB), a central component of most electronic devices, represents a significant fraction of the electronic product waste stream. The complex composition of PCBs, consisting of metals, polymers, and fiberglass, requires specialized recovery steps to reclaim valuable and critical materials and the safe disposal of brominated compounds. In this review paper, we describe the current state of critical material recovery and traditional recycling technologies and identify key obstacles to large-scale implementation. Metals present at high concentrations, such as copper, lead, and iron, are conventionally recovered from PCBs using hydrometallurgical, pyrometallurgical, or electrometallurgical processes. Hydrometallurgical methods achieve high selectivity through chemical leaching but pose significant challenges for effluent and reagent recovery. Pyrometallurgical methods facilitate rapid metal separation through smelting but require substantial energy and may release harmful gases. Electrometallurgical techniques produce high-purity metals but are constrained by pretreatment requirements and the consumption of energy. The non-metallic fraction of PCB waste is recycled using thermochemical conversion, microwave-aided heating, and direct recycling of epoxy–fiberglass composites, enabling material or energy recovery. The recovered polymer from direct recycling may have reduced mechanical strength and poor compatibility with new polymer matrices, and the resulting products from the thermal conversion suffer from incomplete conversion, degradation of quality, and residual contamination, as compared to synthetic polymers. Recent process developments have focused on extracting rare earth and supply-critical materials present at lower concentrations in the waste stream. The literature on existing and emerging approaches for recycling PCB wastes is reviewed to identify sustainable, economically viable, and environmentally responsible strategies for the recovery and reuse of critical materials from waste streams.

36 MATERIALS SCIENCE↗
NASA NTRS1971

Efficient digital comparison technique for logic circuits

Tolerance compare technique indicates discompare only when numerical difference value exceeds prescribed limit. Algorithm involving binary number properties is defined, in lieu of arithmetic operation which requires relatively complex circuitry. Extension of algorithm may be made to encompass tolerances other than one unit.

Mccarthy, C. E.↗
NASA NTRS2024

EdgeCortix SAKURA-I Machine-Learning, PCIe Accelerator SEE Heavy Ion Test Report

To enable autonomy in space, machine-learning and computer vision applications become invaluable for sensor processing. However, these algorithms are computationally complex and unfeasible for many embedded central processing units (CPUs) and usually require external coprocessors, such as graphics processing units (GPUs) or accelerators specific to the application, including application specific integrated circuits (ASICs). In power-constrained systems, GPUs tend to consume more power than is acceptable (>40W), so lower-power accelerators have shown promise to provide the performance needed under spacecraft constraints. For radiation engineers, developing methodologies that can properly test CPUs, GPUs, and accelerators, and enable comparisons between them remains a necessary complication to solve as the devices become more complex. The methodology in this test aims to be a start in developing a baseline single-event effect (SEE) test for client-device machine learning accelerators. This category of devices do not host their own operating system. This testing campaign is a continuation of a previous 200 MeV proton test performed in January 2024. This report covers two heavy ion tests of the SAKURA-I card: one in April 2024, and one in June 2024. Additional data was needed after the April test due to ion-range issues experienced at higher linear-energy transfers (LETs). These range issues are described in more detail in Section 8. This experiment characterizes SEEs and data error susceptibility of the EdgeCortix SAKURA-I machine-learning accelerator under heavy ions. The device was monitored for single event upsets (SEUs) and single event functional interrupts (SEFIs) at the Lawrence Berkeley National Laboratory’s 88-inch cyclotron. The SAKURA-I board accelerates machine-learning inference applications on a host computer through a PCIex16 connection. For the purposes of devising an end to end automated analysis workflow for this experiment, the YOLO-V5 and SSD300 objection-detection models, and the ResNet-50, EfficientNet, and MobileNetV2 image classification models were used as a representative suite of analytical machine-learning models.

Seth S Roffe↗
NASA NTRS1985

Monolithic optical integrated control circuitry for GaAs MMIC-based phased arrays

Gallium arsenide (GaAs) monolithic microwave integrated circuits (MMIC's) show promise in phased-array antenna applications for future space communications systems. Their efficient usage will depend on the control of amplitude and phase signals for each MMIC element in the phased array and in the low-loss radiofrequency feed. For a phased array contining several MMIC elements a complex system is required to control and feed each element. The characteristics of GaAs MMIC's for 20/30-GHz phased-array systems are discussed. The optical/MMIC interface and the desired characteristics of optical integrated circuits (OIC's) for such an interface are described. Anticipated fabrication considerations for eventual full monolithic integration of optical integrated circuits with MMIC's on a GaAs substrate are presented.

Bhasin, K. B.↗