SEARCH · Engineering Papers
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.
Metal oxide semiconductor four-stage binary counter contains reset capability as well as four parallel-set inputs gated in by a logic signal. Parallel-set inputs permit setting the counter into any of sixteen possible states.
Complementary metal oxide semiconductor and bipolar transistors fabrication on same integrated circuit chip by C-squared technology
High energy electron irradiation effects on field effect transistors in integrated circuit devices
Analysis of radiation damage of MOSFET data from Explorer 34 (IMP-F), and radiation damage characteristics of MOSFET with boron diffused between a silicon semiconductor and silicon oxide are considered. The first subject is an interpretation of the discrepancy between the space data and the laboratory data. The second subject is an attempt to analyze the radiation damage characteristic of MOSFET when there is modification of electrical properties in the gate oxide region.
Technique can provide four-phase clock signal from single-phase clock and requires only one power supply voltage. This arrangement saves considerable power compared to circuits having load resistor between power supply and ground.
The current capabilities of LSI techniques for speed and reliability, plus the possibilities of assembling large configurations of LSI logic and storage elements, have demanded the study of multiprocessors and multiprocessing techniques, problems, and potentialities. Evaluated are three previous systems studies for a space ultrareliable modular computer multiprocessing system, and a new multiprocessing system is proposed that is flexibly configured with up to four central processors, four 1/0 processors, and 16 main memory units, plus auxiliary memory and peripheral devices. This multiprocessor system features a multilevel interrupt, qualified S/360 compatibility for ground-based generation of programs, virtual memory management of a storage hierarchy through 1/0 processors, and multiport access to multiple and shared memory units.
Explore the source record for details and available documents.
Technique using boron effectively protects metal-oxide semiconductor devices from ionizing radiation without using shielding materials. Boron is introduced into insulating gate oxide layer at semiconductor-insulator interface.
Method is simple and eliminates requirement for unreliable special etchants. Structure is graded in resistivity to prevent punch-through and has very narrow channel length to increase frequency response. Contacts are on top to permit planar integrated circuit structure. Polycrystalline shield will prevent creation of inversion layer in isolated region.
A gyrator circuit is described which is of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 phase reversal, in a circuit having medium Q composed of all field effect transistors of the same conductivity type. The current source to each gyrator amplifier comprises an amplifier which responds to changes in current, with the amplified signals feed back so as to limit current. The feedback amplifier has a large capacitor connected to bypass high frequency components, thereby stabilizing the output. The design makes possible fabrication of circuits with transistors of only one conductivity type, providing economies in manufacture and use.
The tunneling characteristics of Cr/SiO2/Si structures in the thickness range from 23 to 34 A are reported. The E-kappa dependence in the energy range extending 3.5 eV below the oxide conduction band is determined by the thickness dependence to be approximately of the Franz form with an effective mass ratio of 0.42. Tunneling into the indirect conduction band of silicon is reduced by a thickness-independent factor which decreases approximately exponentially with the energy below the direct band edge.
Explore the source record for details and available documents.
An output device for optimizing propagation delay and minimizing chip area is described. An optimum means of tapering the output stages to minimize propagation delay is determined. The minimum delay is a function of the capacitive load to node ratio, the number of output stages, and the interstage propagation delay. The effects on area are also presented. A figure of merit which is a function of area and propagation time is defined which is of use in designing output stages. An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area. Data are also presented which allow a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.
Explore the source record for details and available documents.
It is pointed out that the reported measurements are useful in a study of interface charge distributions. Measurements of surface-state density at the SiO2 interface given information concerning the effect of the layer thickness on the flat-band interface charge. Other measurements provide data for a determination of the silicon-silica flat-band interface charge, the metal-silica interface charge, and the difference in barrier energies at the interfaces. Measurements of Fowler-Nordheim currents as a function of oxide thickness can be used for the determination of charge distribution in the area next to the metal-silica interface. The investigation shows that the silicon-silica interface is independent of thickness down to thicknesses as low as 40 A.
Method allows flatband voltage measurement of capacitors to be taken quickly and precisely while capacitor is subject to desired conditions.
Design of low-cost, microcomputer-based navigation receivers, and the assembler are described. The development of computer software for microprocessors is materially aided by the assembler program using mnemonic variable names. The flexibility of the environment provided by the IBM's Virtual Machine Facility and the Conversational Monitor System, make possible the convenient assembler access. The implementation of the assembler for the microprocessor chip serves a part of the present need and forms a model for support of other microprocessors.
The complete sequence used to manufacture complementary metal oxide semiconductor (CMOS) integrated circuits is described. The fixed-gate array concept is presented as a means of obtaining CMOS integrated circuits in a fast and reliable fashion. Examples of CMOS circuits fabricated by both the conventional method and the fixed-gate array method are included. The electrical parameter specifications and characteristics are given along with typical values used to produce CMOS circuits. Temperature-bias stressing data illustrating the thermal stability of devices manufactured by this process are presented. Results of a preliminary study on the radiation sensitivity of circuits manufactured by this process are discussed. Some process modifications are given which have improved the radiation hardness of our CMOS devices. A formula description of the chemicals and gases along with the gas flow rates is also included.