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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 397 records · Page 22
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

The Computational Capacity of Mem-LRC Reservoirs

Reservoir computing has a emerged as a powerful tool in data-driven time series analysis. The possibility of utilizing hardware reservoirs as specialized co-processors has generated interest in the properties of electronic reservoirs, especially those based on memristors as the nonlinearity of these devices should translate to an improved nonlinear computational capacity of the reservoir. However, designing these reservoirs requires a detailed understanding of how memristive networks process information which has thus far been lacking. In this work, we derive an equation for general memristor-inductor-resistor-capacitor (MEM-LRC) reservoirs that includes all network and dynamical constraints explicitly. Utilizing this we undertake a study of the computational capacity of these reservoirs. We demonstrate that hardware reservoirs may be constructed with extensive memory capacity and that the presence of memristors enacts a tradeoff between memory capacity and nonlinear computational capacity. Here, using these principles, we design reservoirs to tackle problems in signal processing, paving the way for applying hardware reservoirs to high-dimensional spatiotemporal systems.

Circuits with memory↗
DOE OSTI2024

Dispatching Grid-Forming Inverters in Grid-Connected and Islanded Mode

This paper explores the dispatchability of grid-forming (GFM) inverters in grid-connected and islanded mode. GFM inverters usually use droop control to automatically share power with other GFM sources (inverters and synchronous generators) and follow the change in the load demand; however, they can be dispatched like their grid-following (GFL) counterparts to output the target active and reactive power. This will help grid operators better manage their inverter-based resources (IBRs) to improve operation efficiency and reliability; therefore, this paper proposes an innovative concept of dispatching GFM sources (inverters and synchronous generators) to output the target power in both grid-connected and islanded mode by adjusting their droop intercepts. The fundamental principle is that the GFM inverter's active and reactive power is dictated by its frequency and voltage, and thus dispatching the active and reactve power of a GFM inverter can be achieved through dispatching its frequency and voltage. Moreover, the concept distinguishes the dispatch rules for grid-connected and islanded mode. Finally, the concept is validated with an example microgrid system with two GFM inverters, one diesel generator, one GFL inverter, and the load in both grid-connected and islanded mode. This pioneering work results in practical guidance for the development of energy management systems for future electric grids with GFM and GFL inverters.

dispatching↗
NASA NTRS1993

A multiarchitecture parallel-processing development environment

A description is given of the hardware and software of a multiprocessor test bed - the second generation Hypercluster system. The Hypercluster architecture consists of a standard hypercube distributed-memory topology, with multiprocessor shared-memory nodes. By using standard, off-the-shelf hardware, the system can be upgraded to use rapidly improving computer technology. The Hypercluster's multiarchitecture nature makes it suitable for researching parallel algorithms in computational field simulation applications (e.g., computational fluid dynamics). The dedicated test-bed environment of the Hypercluster and its custom-built software allows experiments with various parallel-processing concepts such as message passing algorithms, debugging tools, and computational 'steering'. Such research would be difficult, if not impossible, to achieve on shared, commercial systems.

Townsend, Scott↗
DOE OSTI2020

Decomposition Algorithms for Solving NP-hard Problems on a Quantum Annealer

NP-hard problems such as the maximum clique or minimum vertex cover problems, two of Karp’s 21 NP-hard problems, have several applications in computational chemistry, biochemistry and computer network security. Adiabatic quantum annealers can search for the optimum value of such NP-hard optimization problems, given the problem can be embedded on their hardware. However, this is often not possible due to certain limitations of the hardware connectivity structure of the annealer. This paper studies a general framework for a decomposition algorithm for NP-hard graph problems aiming to identify an optimal set of vertices. Our generic algorithm allows us to recursively divide an instance until the generated subproblems can be embedded on the quantum annealer hardware and subsequently solved. Furthermore, the framework is applied to the maximum clique and minimum vertex cover problems, and we propose several pruning and reduction techniques to speed up the recursive decomposition. The performance of both algorithms is assessed in a detailed simulation study.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1998

Experimental Results and Issues on Equalization for Nonlinear Memory Channel: Pre-Cursor Enhanced Ram-DFE Canceler

This thesis investigates the effects of the High Power Amplifier (HPA) and the filters over a satellite or telemetry channel. The Volterra series expression is presented for the nonlinear channel with memory, and the algorithm is based on the finite-state machine model. A RAM-based algorithm operating on the receiver side, Pre-cursor Enhanced RAM-FSE Canceler (PERC) is developed. A high order modulation scheme , 16-QAM is used for simulation, the results show that PERC provides an efficient and reliable method to transmit data on the bandlimited nonlinear channel. The contribution of PERC algorithm is that it includes both pre-cursors and post-cursors as the RAM address lines, and suggests a new way to make decision on the pre-addresses. Compared with the RAM-DFE structure that only includes post- addresses, the BER versus Eb/NO performance of PERC is substantially enhanced. Experiments are performed for PERC algorithms with different parameters on AWGN channels, and the results are compared and analyzed. The investigation of this thesis includes software simulation and hardware verification. Hardware is setup to collect actual TWT data. Simulation on both the software-generated data and the real-world data are performed. Practical limitations are considered for the hardware collected data. Simulation results verified the reliability of the PERC algorithm. This work was conducted at NMSU in the Center for Space Telemetering and Telecommunications Systems in the Klipsch School of Electrical and Computer Engineering Department.

Yuan, Lu↗
DOE OSTI2025

TRIM: AI Guided Random Number Generation for Resource-Constrained IoT Systems

Random numbers often serve as the backbone for many security solutions in diverse domains such as cryptography, side channel leakage prevention, and moving target defense. However, generating true random numbers requires a physical source of entropy (e.g. hardware, quantum, environmental phenomenon) making it difficult to realize at a large scale and at a low cost. On the flip side, pseudorandom number generators (easy to implement) following a specific distribution (e.g. Gaussian) can be easily compromised given a sufficient amount of traces. In this work, we have developed a machine learning-guided generative approach that can be used to create portable, resource-efficient, and cost-effective random number generators with high throughput and true randomness characteristics. We implement the proposed approach as a highly parameterized framework and perform extensive evaluation for different settings. The framework was able to learn from true random sources such as irrational numbers and environmental audio noise and imitate those sources towards generating new good quality random numbers on demand. We have generated more than 1 billion bits and observed robust performance in terms of true randomness metrics obtained from NIST SP 800-22 and FIPS 140-1 randomness test suites achieving a throughput of up to 142.85 Mbps. Compared to the state-of-the-art (SOTA) technique, the iso-cost setup of our framework can achieve more than 500 Mbps in a distributed setting. We have evaluated the efficacy of running the true randomness imitation AI models on target edge devices such as Raspberry Pi 4 (Model B), Nvidia Jetson Nano, Nvidia Jetson Orin Nano and Nvidia Jetson Xavier. We have also looked at the security of the TRIM framework itself against different adversarial threat models.

Cybersecurity↗
NASA NTRS2013

Distributed Engine Control Empirical/Analytical Verification Tools

NASA's vision for an intelligent engine will be realized with the development of a truly distributed control system featuring highly reliable, modular, and dependable components capable of both surviving the harsh engine operating environment and decentralized functionality. A set of control system verification tools was developed and applied to a C-MAPSS40K engine model, and metrics were established to assess the stability and performance of these control systems on the same platform. A software tool was developed that allows designers to assemble easily a distributed control system in software and immediately assess the overall impacts of the system on the target (simulated) platform, allowing control system designers to converge rapidly on acceptable architectures with consideration to all required hardware elements. The software developed in this program will be installed on a distributed hardware-in-the-loop (DHIL) simulation tool to assist NASA and the Distributed Engine Control Working Group (DECWG) in integrating DCS (distributed engine control systems) components onto existing and next-generation engines.The distributed engine control simulator blockset for MATLAB/Simulink and hardware simulator provides the capability to simulate virtual subcomponents, as well as swap actual subcomponents for hardware-in-the-loop (HIL) analysis. Subcomponents can be the communication network, smart sensor or actuator nodes, or a centralized control system. The distributed engine control blockset for MATLAB/Simulink is a software development tool. The software includes an engine simulation, a communication network simulation, control algorithms, and analysis algorithms set up in a modular environment for rapid simulation of different network architectures; the hardware consists of an embedded device running parts of the CMAPSS engine simulator and controlled through Simulink. The distributed engine control simulation, evaluation, and analysis technology provides unique capabilities to study the effects of a given change to the control system in the context of the distributed paradigm. The simulation tool can support treatment of all components within the control system, both virtual and real; these include communication data network, smart sensor and actuator nodes, centralized control system (FADEC full authority digital engine control), and the aircraft engine itself. The DECsim tool can allow simulation-based prototyping of control laws, control architectures, and decentralization strategies before hardware is integrated into the system. With the configuration specified, the simulator allows a variety of key factors to be systematically assessed. Such factors include control system performance, reliability, weight, and bandwidth utilization.

DeCastro, Jonathan↗
DOE OSTI2023

Performance Evaluation of Next-Generation Grid Automation and Controls with High PV Penetration

This paper presents a hardware-in-the-loop (BIL) simulation to evaluate the performance of an advanced grid automation architecture, referred to as data-enhanced hierarchical control (DEHC), in achieving voltage regulation and conservation voltage reduction (CVR) in distribution networks with very high photovoltaic (PV) generation. This architecture comprises an advanced distribution management system (ADMS), a distributed energy resource management system (DERMS), and grid-edge devices working synergistically to provide the grid benefits. The HIL setup used for the evaluation includes ADMS, DERMS, and grid-edge devices. The DEHC performance is evaluated in two representative scenarios considering loose and tight constraints of the power factor at the substation. The results show that the DEHC architecture is effective in achieving voltage regulation and CVR and thus enables the grid integration of high levels of PV generation.

ADMS↗
NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing (DSP) functions. Such capability also makes and FPGA a suitable platform for the digital implementation of closed loop controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance in a compact form-factor. Other researchers have presented the notion that a second order digital filter with proportional-integral-derivative (PID) control functionality can be implemented in an FPGA. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSF) devices. Our goal is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. Meeting our goals requires alternative compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching these goals.

Gwaltney, David A.↗
NASA NTRS2010

Composite Overwrapped Pressure Vessels (COPV): Developing Flight Rationale for the Space Shuttle Program

Introducing composite vessels into the Space Shuttle Program represented a significant technical achievement. Each Orbiter vehicle contains 24 (nominally) Kevlar tanks for storage of pressurized helium (for propulsion) and nitrogen (for life support). The use of composite cylinders saved 752 pounds per Orbiter vehicle compared with all-metal tanks. The weight savings is significant considering each Shuttle flight can deliver 54,000 pounds of payload to the International Space Station. In the wake of the Columbia accident and the ensuing Return to Flight activities, the Space Shuttle Program, in 2005, re-examined COPV hardware certification. Incorporating COPV data that had been generated over the last 30 years and recognizing differences between initial Shuttle Program requirements and current operation, a new failure mode was identified, as composite stress rupture was deemed credible. The Orbiter Project undertook a comprehensive investigation to quantify and mitigate this risk. First, the engineering team considered and later deemed as unfeasible the option to replace existing all flight tanks. Second, operational improvements to flight procedures were instituted to reduce the flight risk and the danger to personnel. Third, an Orbiter reliability model was developed to quantify flight risk. Laser profilometry inspection of several flight COPVs identified deep (up to 20 mil) depressions on the tank interior. A comprehensive analysis was performed and it confirmed that these observed depressions were far less than the criterion which was established as necessary to lead to liner buckling. Existing fleet vessels were exonerated from this failure mechanism. Because full validation of the Orbiter Reliability Model was not possible given limited hardware resources, an Accelerated Stress Rupture Test of a flown flight vessel was performed to provide increased confidence. A Bayesian statistical approach was developed to evaluate possible test results with respect to the model credibility and thus flight rationale for continued operation of the Space Shuttle with existing flight hardware. A non-destructive evaluation (NDE) technique utilizing Raman Spectroscopy was developed to directly measure the overwrap residual stress state. Preliminary results provide optimistic results that patterns of fluctuation in fiber elastic strains over the outside vessel surface could be directly correlated with increased fiber stress ratios and thus reduced reliability.

Kezirian, Michael T.↗
NASA NTRS2019

Model Based Engineering for Software Assurance

NASA's successful development of next generation space vehicles, habitats, and robotic systems will require reliable hardware and software systems. The aim of this initiative is to develop modeling methodology and tools to support Model-Based Systems Engineering (MBSE) for software assurance and reliability analysis. This effort expands the Unified Modeling Language (UML) software design models to include fault data for the extraction of Failure Modes and Effects Criticality Analysis (FMECA) and Fault Tree Analysis (FTA) for software. We explored different modeling approaches to integrate the UML software design models with the Systems Modeling Language (SysML) system models to generate an integrated model and reliability tools that take into account software and hardware interfaces.The benefits of this concept directly affect the safety community with quick turnarounds to produce software assurance and reliability analysis artifacts and the ability to visualize failure effects, both hardware and software. The result is enhanced system design integrity and early identification of system risks. This initiative will enable software assurance activities early in the system design lifecycle, facilitating the discovery of design weaknesses and enhancing the capability to produce safe, hazard-free systems

Wang, Lui↗
NASA NTRS2010

The J-2X Upper Stage Engine: From Design to Hardware

NASA is well on its way toward developing a new generation of launch vehicles to support of national space policy to retire the Space Shuttle fleet, complete the International Space Station, and return to the Moon as the first step in resuming this nation s exploration of deep space. The Constellation Program is developing the launch vehicles, spacecraft, surface systems, and ground systems to support those plans. Two launch vehicles will support those ambitious plans the Ares I and Ares V. (Figure 1) The J-2X Upper Stage Engine is a critical element of both of these new launchers. This paper will provide an overview of the J-2X design background, progress to date in design, testing, and manufacturing. The Ares I crew launch vehicle will lift the Orion crew exploration vehicle and up to four astronauts into low Earth orbit (LEO) to rendezvous with the space station or the first leg of mission to the Moon. The Ares V cargo launch vehicle is designed to lift a lunar lander into Earth orbit where it will be docked with the Orion spacecraft, and provide the thrust for the trans-lunar journey. While these vehicles bear some visual resemblance to the 1960s-era Saturn vehicles that carried astronauts to the Moon, the Ares vehicles are designed to carry more crew and more cargo to more places to carry out more ambitious tasks than the vehicles they succeed. The government/industry team designing the Ares rockets is mining a rich history of technology and expertise from the Shuttle, Saturn and other programs and seeking commonality where feasible between the Ares crew and cargo rockets as a way to minimize risk, shorten development times, and live within the budget constraints of its original guidance.

Byrd, Thomas↗
NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of FPGA's (Field Programmable Gate Arrays) in the hardware implementation of fast digital signal processing. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used proportional-integral-derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM-based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a DSP (Digital Signal Processor) or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using digital signal processor (DSP) devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, pulse width modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive control algorithm approaches. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacecraft. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Gwaltney, David A.↗
NASA NTRS2002

Implementation of Adaptive Digital Controllers on Programmable Logic Devices

Much has been made of the capabilities of Field Programmable Gate Arrays (FPGA's) in the hardware implementation of fast digital signal processing functions. Such capability also makes an FPGA a suitable platform for the digital implementation of closed loop controllers. Other researchers have implemented a variety of closed-loop digital controllers on FPGA's. Some of these controllers include the widely used Proportional-Integral-Derivative (PID) controller, state space controllers, neural network and fuzzy logic based controllers. There are myriad advantages to utilizing an FPGA for discrete-time control functions which include the capability for reconfiguration when SRAM- based FPGA's are employed, fast parallel implementation of multiple control loops and implementations that can meet space level radiation tolerance requirements in a compact form-factor. Generally, a software implementation on a Digital Signal Processor (DSP) device or microcontroller is used to implement digital controllers. At Marshall Space Flight Center, the Control Electronics Group has been studying adaptive discrete-time control of motor driven actuator systems using DSP devices. While small form factor, commercial DSP devices are now available with event capture, data conversion, Pulse Width Modulated (PWM) outputs and communication peripherals, these devices are not currently available in designs and packages which meet space level radiation requirements. In general, very few DSP devices are produced that are designed to meet any level of radiation tolerance or hardness. An alternative is required for compact implementation of such functionality to withstand the harsh environment encountered on spacemap. The goal of this effort is to create a fully digital, flight ready controller design that utilizes an FPGA for implementation of signal conditioning for control feedback signals, generation of commands to the controlled system, and hardware insertion of adaptive-control algorithm approaches. Radiation tolerant FPGA's are a feasible option for reaching this goal.

Gwaltney, David A.↗
NASA NTRS1988

Independent Orbiter Assessment (IOA): Assessment of the reaction control system, volume 2

The results of the Independent Orbiter Assessment (IOA) of the Failure Modes and Effects Analysis (FMEA) and Critical Items List (CIL) are presented. The IOA effort first completed an analysis of the aft and forward Reaction Control System (RCS) hardware and Electrical Power Distribution and Control (EPD and C), generating draft failure modes and potential critical items. The IOA results were then compared to the proposed Post 51-L NASA FMEA/CIL baseline. This report documents the results of that comparison for the Orbiter RCS hardware and EPD and C systems. Volume 2 continues the presentation of IOA worksheets.

Prust, Chet D.↗
NASA NTRS1988

Independent Orbiter Assessment (IOA): Assessment of the reaction control system, volume 3

The results of the Independent Orbiter Assessment (IOA) of the Failure Modes and Effects Analysis (FMEA) and Critical Items List (CIL) are presented. The IOA effort first completed an analysis of the aft and forward Reaction Control System (RCS) hardware and Electrical Power Distribution and Control (EPD and C), generating draft failure modes and potential critical items. The IOA results were then compared to the proposed Post 51-L NASA FMEA/CIL baseline. This report documents the results of that comparison for the Orbiter RCS hardware and EPD and C systems. Volume 3 continues the presentation of IOA worksheets.

Prust, Chet D.↗
NASA NTRS1988

Independent Orbiter Assessment (IOA): Assessment of the reaction control system, volume 4

The results of the Independent Orbiter Assessment (IOA) of the Failure Modes and Effects Analysis (FMEA) and Critical Items List (CIL) are presented. The IOA effort first completed an analysis of the aft and forward Reaction Control System (RCS) hardware and Electrical Power Distribution and Control (EPD and C), generating draft failure modes and potential critical items. The IOA results were then compared to the proposed Post 51-L NASA FMEA/CIL baseline. This report documents the results of that comparison for the Orbiter RCS hardware and EPD and C systems. Volume 4 continues the presentation of IOA worksheets and contains the potential critical items list.

Prust, Chet D.↗
NASA NTRS1988

Independent Orbiter Assessment (IOA): Assessment of the reaction control system, volume 5

The results of the Independent Orbiter Assessment (IOA) of the Failure Modes and Effects Analysis (FMEA) and Critical Items List (CIL) are presented. The IOA effort first completed an analysis of the aft and forward Reaction Control System (RCS) hardware and Electrical Power Distribution and Control (EPD and C), generating draft failure modes and potential critical items. The IOA results were then compared to the proposed Post 51-L NASA FMEA/CIL baseline. This report documents the results of that comparison for the Orbiter RCS hardware and EPD and C systems. Volume 5 contains detailed analysis and superseded analysis worksheets and the NASA FMEA to IOA worksheet cross reference and recommendations.

Prust, Chet D.↗