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A novel analog muliplier using SOI four-gate transistors (G4-FETs) is presented. Thanks to the multiple inputs of the G4-FET that may be biased independently, the number of transistors in the proposed circuit is dramatically reduced, compared to conventional single-gate MOSFET based multipliers.
A front-illuminated CCD of relative high quantum efficiency (QE) and high charge transfer efficiency (CTE) utilizes an open-phase region for receiving photons and two-phase gate regions (.phi..sub.1 and .phi..sub.2) for transferring electrons collected in one pixel to the next. The open-phase region is implanted with additional n-type elements (phosphorus) in order to increase the potential of the CCD channel in the open-phase region for collection of electrons and additionally implanted with concentrated and very shallow p-type elements (boron) to pin the surface of the n-channel in the open-phase region to OV, while gate region .phi..sub.1 and .phi..sub.2 are biased to -3.5V and driven to +10V by a two-phase transfer clock. The open pinned-phase (OPP) region thus permits two-phase transfer clocking and optimum reception of photons during the integration periods between transfer clock pulses.
A circuit topography is presented which is used to create usable digital logic gates using N (negatively doped) channel Junction Field Effect Transistors (JFETs) and load resistors, level shifting resistors, and supply rails whose values are based on the direct current (DC) parametric distributions of those JFETs. This method has direct application to the current state of the art in high temperature, for example 300.degree. C. to 500.degree. C. and higher, silicon carbide (SiC) device production. The ability to produce inverting and combinatorial logic enables the production of pulse and edge triggered latches. This scale of logic synthesis would bring digital logic and state machine capabilities to devices operating in extremely hot environments, such as the surface of Venus, near hydrothermal vents, within nuclear reactors (SiC is inherently radiation hardened), and within internal combustion engines. The basic logic gate can be configured as a driver for oscillator circuits allowing for time bases and simple digitizers for resistive or reactive sensors. The basic structure of this innovation, the inverter, can be reconfigured into various analog circuit topographies through the use of feedback structures.
A complementary metal oxide/semiconductor (CMOS) electronic circuit has been designed to function as a NAND gate at a temperature between 0 and 80 deg C and as a NOR gate at temperatures from 120 to 200 C. In the intermediate temperature range of 80 to 120 C, this circuit is expected to perform a function intermediate between NAND and NOR with degraded noise margin. The process of designing the circuit and the planned fabrication and testing of the circuit are parts of demonstration of polymorphic electronics a technological discipline that emphasizes designing the same circuit to perform different analog and/or digital functions under different conditions. In this case, the different conditions are different temperatures.
A complementary metal oxide/semiconductor (CMOS) electronic circuit functions as a NAND gate at a power-supply potential (V(sub dd)) of 3.3 V and as NOR gate for V(sub dd) = 1.8 V. In the intermediate V(sub dd) range of 1.8 to 3.3 V, this circuit performs a function intermediate between NAND and NOR with degraded noise margin. Like the circuit of the immediately preceding article, this circuit serves as a demonstration of the evolutionary approach to design of polymorphic electronics -- a technological discipline that emphasizes evolution of the design of a circuit to perform different analog and/or digital functions under different conditions. In this instance, the different conditions are different values of V(sub dd).
We describe an architecture for spontaneous Raman scattering utilizing a frame-transfer CCD sensor operating in a subframe burst-gating mode to realize time-resolved combustion diagnostics. The technique permits all-electronic optical gating with microsecond shutter speeds 5 J.Ls) without compromising optical throughput or image fidelity. When used in conjunction with a pair of orthogonally polarized excitation lasers, the technique measures single-shot vibrational Raman scattering that is minimally contaminated by problematic optical background noise.
The NASA Dust Management Project (DMP) was established to provide technologies (to TRL 6 development level) required to address adverse effects of lunar dust to humans and to exploration systems and equipment, which will reduce life cycle cost and risk, and will increase the probability of sustainable and successful lunar missions. The technology portfolio of DMP consisted of different categories of technologies whose final product is either a technology solution in itself, or one that contributes toward a dust mitigation strategy for a particular application. A Decision Gate Process (DGP) was developed to assess and validate the achievement and priority of the dust mitigation technologies as the technologies progress through the development cycle. The DGP was part of continuous technology assessment and was a critical element of DMP risk management. At the core of the process were technology-specific criteria developed to measure the success of each DMP technology in attaining the technology readiness levels assigned to each decision gate. The DGP accounts for both categories of technologies and qualifies the technology progression from technology development tasks to application areas. The process provided opportunities to validate performance, as well as to identify non-performance in time to adjust resources and direction. This paper describes the overall philosophy of the DGP and the methodology for implementation for DMP, and describes the method for defining the technology evaluation criteria. The process is illustrated by example of an application to a specific DMP technology.
The NASA Dust Management Project (DMP) was established to provide technologies (to Technology Readiness Level (TRL) 6) required to address adverse effects of lunar dust to humans and to exploration systems and equipment, to reduce life cycle cost and risk, and to increase the probability of sustainable and successful lunar missions. The technology portfolio of DMP consisted of different categories of technologies whose final product was either a technology solution in itself, or one that contributes toward a dust mitigation strategy for a particular application. A Decision Gate Process (DGP) was developed to assess and validate the achievement and priority of the dust mitigation technologies as the technologies progress through the development cycle. The DGP was part of continuous technology assessment and was a critical element of DMP risk management. At the core of the process were technology-specific criteria developed to measure the success of each DMP technology in attaining the technology readiness levels assigned to each decision gate. The DGP accounts for both categories of technologies and qualifies the technology progression from technology development tasks to application areas. The process provided opportunities to validate performance, as well as to identify non-performance in time to adjust resources and direction. This paper describes the overall philosophy of the DGP and the methodology for implementation for DMP, and describes the method for defining the technology evaluation criteria. The process is illustrated by example of an application to a specific DMP technology.
Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.
Systems and methods in accordance with embodiments of the invention implement microscale digital vacuum electronic gates. In one embodiment, a microscale digital vacuum electronic gate includes: a microscale field emitter that can emit electrons and that is a microscale cathode; and a microscale anode; where the microscale field emitter and the microscale anode are disposed within at least a partial vacuum; where the microscale field emitter and the microscale anode are separated by a gap; and where the potential difference between the microscale field emitter and the microscale anode is controllable such that the flow of electrons between the microscale field emitter and the microscale anode is thereby controllable; where when the microscale anode receives a flow of electrons, a first logic state is defined; and where when the microscale anode does not receive a flow of electrons, a second logic state is defined.
Point-to-point laser metrology systems can be used to stabilize large structures at the nanometer levels required for precision optical systems. Existing sensors are large and intrusive, however, with optical heads that consist of several optical elements and require multiple optical fiber connections. The use of point-to-point laser metrology has therefore been limited to applications where only a few gauges are needed and there is sufficient space to accommodate them. Range-Gated Metrology is a signal processing technique that preserves nanometer-level or better performance while enabling: (1) a greatly simplified optical head - a single fiber optic collimator - that can be made very compact, and (2) a single optical fiber connection that is readily multiplexed. This combination of features means that it will be straightforward and cost-effective to embed tens or hundreds of compact metrology gauges to stabilize a large structure. In this paper we describe the concept behind Range-Gated Metrology, demonstrate the performance in a laboratory environment, and give examples of how such a sensor system might be deployed.
Many of the most challenging computational problems arising in practical applications are tackled by heuristic algorithms which have not been rigorously proven to outperform other approaches but rather have been empirically demonstrated to be effective. While quantum heuristics have been proposed since the early days of quantum computing, true empirical evaluation of the real-world performance of these algorithms is only becoming possible now as increasingly powerful quantum gate-model devices continue to come online.In this talk, I will give an overview of the NASA QuAIL team's ongoing investigation into quantum gate-model heuristic algorithms for exact and approximate optimization. In particular, we consider the performance of the Quantum Approximate Optimization Algorithm on NP-hard optimization problems, and describe algorithm parameter setting strategies for real-world quantum hardware. We then show a generalization of QAOA circuits, the Quantum Alternating Operator Ansatz, especially suitable for low-resource implementations of QAOA for problems with hard (feasibility) constraints. The talk will conclude with a discussion of research challenges, particularly for optimization and sampling applications of QAOA, and the potential of more general quantum heuristics to give advantages over classical computers.
We present the design of a four-photomultiplier tube (PMT) assembly for measuring light generation in theBoronated Scintillator Detector (BSD) of the Cosmic Ray Energetics And Mass experiment for the InternationalSpace Station (ISS-CREAM). The light produced in the scintillator includes a contribution from the captureof thermalized neutrons produced in cosmic ray interactions, as well as delayed fluorescence, in the range ofseveral microseconds following the incident cosmic ray impact. The BSD is held in an insensitive state until acosmic-ray trigger causes a rapid turn on of the PMTs to detect late light signals, several microseconds afterthe trigger. The design includes two pulsed high-voltage supplies, which serve to gate the first two dynodesof the Hamamatsu R1924A PMTs used in the assembly. When the dynode gates are held in the "off" state,this scheme is shown to suppress >105 photons from injection into the tube's multiplier stage, while beingcapable of rapid switching into a stable operating mode in less than 1 s. This mitigates any backgroundsfrom afterpulsing that might otherwise be present in the PMT response following the cosmic ray incidence.
The modern day National Airspace System (NAS) is powered by System Wide Information Management (SWIM) which is a real-time digital data sharing infrastructure that provides a high fidelity view of the lifecycle of a flight. The newly available data within the SWIM feeds can be leveraged to help drive efficiencies in the NAS. In this talk, we investigate the gate conflict prediction problem as a concrete use case which could help drive efficiencies. We begin with a high level description of NASA's Airspace Technology Demonstration 2 which is built upon the real-time SWIM feeds and produces the data used in our investigation. We model gate conflicts as a regression problem and describe the iterative process of model building, model validation, and evaluation used to assess the efficacy of our approach.
Commercially available, chemical vapor deposition grown, graphene has been used to realizevoltage-gate tunable, microwave power detectors. Corbino disc structures with chrome/gold contacts havebeen fabricated on top of graphene deposited on P-type silicon substrates with silicon dioxide gate oxides.Devices of varying sizes were used to detect a 433.92 MHz signal. These test structures exhibited a peak power detection sensitivity of 3.25 mV/mW at 292 K and 5.43 mV/mW at 80 K. The improved graphene detectors exceed the sensitivity of previously reported graphene detectors, 0.86 mV/mW, as well as previously explored carbon nanotube bolometers, 0.36 mV/mW
K.E. Martus,O.J. Orient,A Three-mesh gate is used in a time-of-flight(TOF) apparatus to analyze the Velocity of positive ions. Test results and a theoretical description are presented of an effect arising from trapping ions between meshes of a two gate TOF velocity analyzer. The entrapped ions produce a side peak in the TOF spectra corresponding to faster ions.
The present disclosure is directed to various mechanical logic gates. In one example a mechanical logic NOT gate system is formed which has a first pair of bi-stable buckling structures each being operatively connected at a first connection point thereof to one another, and also to a first rigid structure at second connection points, the first rigid structure being held stationary. A second pair of bi-stable buckling flexures is each operatively connected at first connection points thereof to each other and at second connection points thereof to a second rigid structure being held stationary. An output element is coupled a first one of each of the first and second pairs of bi-stable buckling structures. An input element is coupled to a second one of each of the first and second pairs of bi-stable buckling structures. The output element moves from a logic 1 position to a logic 0 position in response to movement of the input element from a logic 0 position to a logic 1 positions, respectively.
A wide range of utility applications require controllable switches with features such as high-voltage (HV) blocking and high-current carrying capacity especially at high pulse width modulation (PWM) frequency. Low and medium voltage utility applications such as motor drives and flexible AC transmission systems (FACTS) as well as solid state transformers (SST) could also benefit from a low-cost HV switching module. Wide band gap (WBG) semiconductors such as SiC and GaN MOSFETs are considered to be the present and next generation device choices, although they have their own limitations. For relatively HV applications with demanding thermal management, SiC is still the only choice, and GaN dominates the low voltage regime. This manuscript proposes a new half bridge power MOSFET module that is suitable for conventional H-bridge of multilevel configurations used in HV applications. Constructed from bare SiC dies, this half bridge module takes advantage of (1) optimized MOSFET placement inside the module, (2) customized heat exchanger, manifold and cooling, (3) integrated gate driver module with PWM over wi-fi to eliminate the need for low voltage signals, (4) wireless power transfer (WPT) enabled gate driver and other ancillary circuits, (5) and the option to incorporate an onboard state of health (SOH) estimator module onboard. The entire architecture has been designed and built at National Renewable Energy Laboratory (NREL), Golden, CO.