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At least 397 records · Page 22
All sourcesNASA NTRSDOE OSTI
NASA NTRSDate not supplied

Testing of A Photon-Counting Optical Ground Receiver With Emulated Space-to-Ground Link Effects

The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) developed and previously characterized a photon-counting optical ground receiver system. The receiver is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications Coding and Synchronization High Photon Efficiency (HPE) Standard. The standard will be used on the Optical Artemis-2 Orion (O2O) communications demonstration and the Deep Space Optical Communication (DSOC) project aboard the Psyche spacecraft. The receiver system consists of a fiber interconnect, up to sixteen superconducting nanowire single-photon detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. Previously, the receiver system architecture was described and test results without emulated link effects were presented. SNSPD device properties, which impact detection jitter and time delay, can limit the receiver dynamic range, especially when operating with varying flux rates (>10 dB) between detectors. Codeword error-rate curves with and without simulated clock drifts attributed to Doppler shift and space transmitter clock differences are presented. Results with ±66 ppm clock differences show minimal performance impact (<0.2 dB). Test results show that the receiver dynamic range (>28 dB) is limited by changing SNSPD detection delays at high photon flux rates.

optical communications↗
NASA NTRS2023

A System to Provide Deterministic Flight Software Operation and Maximize Multicore Processing Performance: The Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) Datapath

A method and design are described for a system that processes multiple data streams, utilizing a multicore asymmetric processing architecture, that eliminates data interrupts to the application processors. The design supports a deterministic environment for flight software in NASA’s Safe and Precise Landing – Integrated Capabilities Evolution (SPLICE) project. The SPLICE project develops sensor, algorithm, and compute technologies for Precision Landing and Hazard Avoidance (PL&HA) capabilities. The compute technology for SPLICE is the Descent and Landing Computer (DLC). The DLC hosts several SPLICE algorithms with high computational resource requirements that must be executed in a real-time and deterministic manner. The software runs on a custom Single Board Computer (SBC), with a Xilinx Ultrascale+ Multiprocessor System-on-a-Chip (MPSoC). Input data for the flight software is from a variety of sensors, unique with respect to data rate and packet size. A data path between the SPLICE sensors and algorithms is designed to efficiently deliver this data to the flight software using the MPSoC asymmetric processing cores and Field Programmable Gate Array (FPGA) fabric. This is implemented in a manner that isolates the application processors running the flight software from interrupts associated with the input data. By leveraging real-time processors on the MPSoC, and a structure with the appropriate interfaces in the shared memory on the SBC, the flight software can use the full set of application processors. The available utilization for each processor in this set is also maximized for the SPLICE applications, providing a sufficiently deterministic execution environment without the cost and overhead of a real-time operating system.

David K. Rutishauser↗
NASA NTRSDate not supplied

Testing of A Photon-Counting Optical Ground Receiver With Emulated Space-to-Ground Link Effects

The National Aeronautics and Space Administration (NASA) Glenn Research Center (GRC) developed and previously characterized a photon-counting optical ground receiver system. The receiver is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications Coding and Synchronization High Photon Efficiency (HPE) Standard. The standard will be used on the Optical Artemis-2 Orion (O2O) communications demonstration and the Deep Space Optical Communication (DSOC) project aboard the Psyche spacecraft. The receiver system consists of a fiber interconnect, up to sixteen superconducting nanowire single-photon detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. Previously, the receiver system architecture was described and test results without emulated link effects were presented. SNSPD device properties, which impact detection jitter and time delay, can limit the receiver dynamic range, especially when operating with varying flux rates (>10 dB) between detectors. Codeword error-rate curves with and without simulated clock drifts attributed to Doppler shift and space transmitter clock differences are presented. Results with ±66 ppm clock differences show minimal performance impact (<0.2 dB). Test results show that the receiver dynamic range (>28 dB) is limited by changing SNSPD detection delays at high photon flux rates.

optical communications↗
NASA NTRSDate not supplied

A Photon Counting Ground Receiver for Free-Space Optical Communications

The National Aeronautics and Space Administration is developing a photon counting ground receiver for free-space optical communications. The receiver consists of a fiber interconnect, superconducting nanowire single photon counting detectors (SNSPDs), and a field programmable gate array (FPGA) based receive modem. This receiver is compliant with the Consultative Committee for Space Data Systems (CCSDS) Optical Communications High Photon Efficiency standard, which is used in the low photon flux communications regime, including on the upcoming Optical Artemis-2 Orion communications demonstration. The receiver architecture is modular, can be scaled for data rate, and is designed with primarily commercial-off-the-shelf technology. Two fiber interconnect and detector architectures are being prototyped. The first uses a few-mode-fiber coupled to a 16-channel SNSPD array and the second architecture uses a photonic lantern coupled to 7 single-pixel SNSPDs. Photon counting, symbol timing recovery, demodulation and decoding is done using several FPGA cards. This presentation describes the unique features of the ground receiver, performance test results, and challenges with using commercial SNSPDs in free-space optical communications.

Jennifer N Downey↗
NASA NTRS2024

Final Technical Report for CMSC 838L

This paper describes Rahul Vishnoi’s final project supporting in his Graduate School curriculum CMSC 838L, Advanced Topics in Programming Languages and Computer Architecture. This project was selected to intersect with his work as a Pathways Intern supporting Code 583, the Ground Software Systems Branch, at NASA’s Goddard Space Flight Center (GSFC). In this project, Field Programmable Gate Array (FPGA) hardware from Xilinx is used to replace and offload processor and memory-intensive computations from a microcontroller/Processing System (PS) to the FPGA Programmable Logic (PL). An interface between the PL and PS in the form of a C library allows for this bridging of capability.

Microcontroller, FPGA, Embedded Development, Xilin↗
NASA NTRSDate not supplied

Leveraging High-Level Synthesis to Migrate Motor Control Algorithms From Microcontroller to FPGA

As motor control algorithms become increasingly complex, traditional microcontroller-based implementations are reaching computational limits that prevent the controller from operating at the required speed. This paper presents a novel workflow leveraging High-Level Synthesis (HLS) to migrate motor control algorithms from a microcontroller implementation to a Field-Programmable Gate Array (FPGA) implementation. The proposed approach utilizes the free Vitis HLS software to automatically convert Embedded Coder-generated C code from a Simulink model into Hardware Description Language (HDL) code suitable for FPGA deployment.

FPGA↗
NASA NTRSDate not supplied

Leveraging High-Level Synthesis to Migrate Motor Control Algorithms From Microcontroller to FPGA

As motor control algorithms become increasingly complex, traditional microcontroller-based implementations are reaching computational limits that prevent the controller from operating at the required speed. This paper presents a novel workflow leveraging High-Level Synthesis (HLS) to migrate motor control algorithms from a microcontroller implementation to a Field-Programmable Gate Array (FPGA) implementation. The proposed approach utilizes the free Vitis HLS software to automatically convert Embedded Coder-generated C code from a Simulink model into Hardware Description Language (HDL) code suitable for FPGA deployment.

FPGA↗
NASA NTRS2002

The wide swath ocean altimeter: radar interferometry for global ocean mapping with centimetric accuracy

We have developed an instrument concept that combines a conventional nadir altimeter with a radar interferometer to meet the above requirements. In this paper, we describe the overall mission concept and the interferometric radar design. We also describe several new technology developments that facilitate the inclusion of this instrument on a small, inexpensive spacecraft bus. Those include ultra-light, deployable reflectarray antennas for the radar interferometer; a novel five frequency feed horn for the radiometer and altimeter; a lightweight, low power integrated three frequency radiometer; and a field programmable gate array-based onboard data processor. Finally, we discuss recent algorithm developments for the onboard date processing, and present the expected instatements performance improvements over previously reported results.

interferometry↗