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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 397 records · Page 22
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

High Power Amplifier and Power Supply

A document discusses the creation of a high-voltage power supply (HVPS) that is able to contain voltages up to -20 kV, keep electrical field strengths to below 200 V/mil (approximately equal to 7.87 kV/mm), and can provide a 200-nanosecond rise/fall time focus modulator swinging between cathode potential of 16.3 kV and -19.3 kV. This HVPS can protect the 95-GHz, pulsed extended interaction klystron (EIK) from arcs/discharges from all sources, including those from within the EIK fs vacuum envelope. This innovation has a multi-winding pulse transformer design, which uses new winding techniques to provide the same delays and rise/fall times (less than 10 nanoseconds) at different potential levels ranging from -20 kV to -16 kV. Another feature involves a high-voltage printed-wiring board that was corona-free at -20 kV DC with a 3- kV AC swing. The corona-free multilayer high-voltage board is used to simulate fields of less than 200 V/mil (approximately equal to 7.87 kV/mm) at 20 kV DC. Drive techniques for the modulator FETs (field-effect transistors) (four to 10 in a series) were created to change states (3,000-V swing) without abrupt steps, while still maintaining required delays and transition times. The packing scheme includes a potting mold to house a ten-stage modulator in the space that, in the past, only housed a four-stage modulator. Problems keeping heat down were solved using aluminum oxide substrate in the high-voltage section to limit temperature rise to less than 10 while withstanding -20 kV DC voltage and remaining corona-free.

Duong, Johnny↗
NASA NTRS2009

Zinc Alloys for the Fabrication of Semiconductor Devices

ZnBeO and ZnCdSeO alloys have been disclosed as materials for the improvement in performance, function, and capability of semiconductor devices. The alloys can be used alone or in combination to form active photonic layers that can emit over a range of wavelength values. Materials with both larger and smaller band gaps would allow for the fabrication of semiconductor heterostructures that have increased function in the ultraviolet (UV) region of the spectrum. ZnO is a wide band-gap material possessing good radiation-resistance properties. It is desirable to modify the energy band gap of ZnO to smaller values than that for ZnO and to larger values than that for ZnO for use in semiconductor devices. A material with band gap energy larger than that of ZnO would allow for the emission at shorter wavelengths for LED (light emitting diode) and LD (laser diode) devices, while a material with band gap energy smaller than that of ZnO would allow for emission at longer wavelengths for LED and LD devices. The amount of Be in the ZnBeO alloy system can be varied to increase the energy bandgap of ZnO to values larger than that of ZnO. The amount of Cd and Se in the ZnCdSeO alloy system can be varied to decrease the energy band gap of ZnO to values smaller than that of ZnO. Each alloy formed can be undoped or can be p-type doped using selected dopant elements, or can be n-type doped using selected dopant elements. The layers and structures formed with both the ZnBeO and ZnCdSeO semiconductor alloys - including undoped, p-type-doped, and n-type-doped types - can be used for fabricating photonic and electronic semiconductor devices for use in photonic and electronic applications. These devices can be used in LEDs, LDs, FETs (field effect transistors), PN junctions, PIN junctions, Schottky barrier diodes, UV detectors and transmitters, and transistors and transparent transistors. They also can be used in applications for lightemitting display, backlighting for displays, UV and visible transmitters and detectors, high-frequency radar, biomedical imaging, chemical compound identification, molecular identification and structure, gas sensors, imaging systems, and for the fundamental studies of atoms, molecules, gases, vapors, and solids.

Ryu, Yungryel↗
NASA NTRS2009

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Phillips, Thomas A.↗
NASA NTRS2009

Analysis of the Measurement and Modeling of a Digital Inverter Based on a Ferroelectric Transistor

The use of ferroelectric materials for digital memory devices is widely researched and implemented, but ferroelectric devices also possess unique characteristics that make them have interesting and useful properties in digital circuits. Because ferroelectric transistors possess the properties of hysteresis and nonlinearity, a digital inverter containing a FeFET has very different characteristics than one with a traditional FET. This paper characterizes the properties of the measurement and modeling of a FeFET based digital inverter. The circuit was set up using discrete FeFETs. The purpose of this circuit was not to produce a practical integrated circuit that could be inserted directly into existing digital circuits, but to explore the properties and characteristics of such a device and to look at possible future uses. Input and output characteristics are presented, as well as timing measurements. Comparisons are made between the ferroelectric device and the properties of a standard digital inverter. Potential benefits and possible uses of such a device are presented.

MacLeod, Todd C.↗
NASA NTRS2009

Lattice-Matched Semiconductor Layers on Single Crystalline Sapphire Substrate

SiGe is an important semiconductor alloy for high-speed field effect transistors (FETs), high-temperature thermoelectric devices, photovoltaic solar cells, and photon detectors. The growth of SiGe layer is difficult because SiGe alloys have different lattice constants from those of the common Si wafers, which leads to a high density of defects, including dislocations, micro-twins, cracks, and delaminations. This innovation utilizes newly developed rhombohedral epitaxy of cubic semiconductors on trigonal substrates in order to solve the lattice mismatch problem of SiGe by using trigonal single crystals like sapphire (Al2O3) as substrate to give a unique growth-orientation to the SiGe layer, which is automatically controlled at the interface upon sapphire (0001). This technology is different from previous silicon on insulator (SOI) or SGOI (SiGe on insulator) technologies that use amorphous SiO2 as the growth plane. A cubic semiconductor crystal is a special case of a rhombohedron with the inter-planar angle, alpha = 90 deg. With a mathematical transformation, all rhombohedrons can be described by trigonal crystal lattice structures. Therefore, all cubic lattice constants and crystal planes (hkl) s can be transformed into those of trigonal crystal parameters. These unique alignments enable a new opportunity of perfect lattice matching conditions, which can eliminate misfit dislocations. Previously, these atomic alignments were thought to be impossible or very difficult. With the invention of a new x-ray diffraction measurement method here, growth of cubic semiconductors on trigonal crystals became possible. This epitaxy and lattice-matching condition can be applied not only to SiGe (111)/sapphire (0001) substrate relations, but also to other crystal structures and other materials, including similar crystal structures which have pointgroup rotational symmetries by 120 because the cubic (111) direction has 120 rotational symmetry. The use of slightly miscut (less than plus or minus 10 deg.) sapphire (0001) substrate can be used to improve epitaxial relationships better by providing attractive atomic steps in the epitaxial process.

Choi, Sang↗
NASA NTRS2007

Maintaining Stability During a Conducted-Ripple EMC Test

An improved technique, and electronic circuitry to implement the technique, have been developed for a military-standard electromagnetic-compatibility (EMC) test in which one analyzes susceptibility to low-frequency ripple conducted into the equipment under test via a DC power line. In the traditional technique for performing the particular test, the ripple is coupled onto the DC power line via a transformer. Depending upon some design details of the equipment under test, the inductance of the transformer can contribute a degree of instability that results in an oscillation of amplitude large enough to destroy the equipment. It is usually possible to suppress the oscillation by connecting a damping resistor to the primary terminals of the ripple-injection transformer. However, it is important to emphasize the usually in the preceding sentence: sometimes, the resistive damping becomes insufficient to suppress destructive oscillation. In addition, undesirably, the resistor contributes to power dissipation and power demand, and thereby also necessitates the use of a larger ripple voltage amplifier. Yet another disadvantage of the transformer-coupling technique is that the transformer introduces low-frequency distortion of the injected ripple voltage. The improved technique makes it possible to inject ripple with very low distortion at low frequency, without inducing oscillation. In this technique, a transformer is not used: Instead, power is fed to the equipment under test via series power field-effect transistors (FETs) controlled by a summing operational amplifier. One of the inputs to the amplifier controls the DC component of the power-line voltage; the other input, generated by an external oscillator, controls the ripple component. The circuitry for implementing this technique includes panel displays, an internal power supply for the operational amplifier and panel displays, and amplitude controls for the DC and ripple powerline voltage components.

Vorperian, Vatche↗
NASA NTRS2009

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

DeGregorio, Kelly↗
NASA NTRS2007

NASA Tech Briefs, July 2007

Topics covered include: Miniature Intelligent Sensor Module; "Smart" Sensor Module; Portable Apparatus for Electrochemical Sensing of Ethylene; Increasing Linear Dynamic Range of a CMOS Image Sensor; Flight Qualified Micro Sun Sensor; Norbornene-Based Polymer Electrolytes for Lithium Cells; Making Single-Source Precursors of Ternary Semiconductors; Water-Free Proton-Conducting Membranes for Fuel Cells; Mo/Ti Diffusion Bonding for Making Thermoelectric Devices; Photodetectors on Coronagraph Mask for Pointing Control; High-Energy-Density, Low-Temperature Li/CFx Primary Cells; G4-FETs as Universal and Programmable Logic Gates; Fabrication of Buried Nanochannels From Nanowire Patterns; Diamond Smoothing Tools; Infrared Imaging System for Studying Brain Function; Rarefying Spectra of Whispering-Gallery-Mode Resonators; Large-Area Permanent-Magnet ECR Plasma Source; Slot-Antenna/Permanent-Magnet Device for Generating Plasma; Fiber-Optic Strain Gauge With High Resolution And Update Rate; Broadband Achromatic Telecentric Lens; Temperature-Corrected Model of Turbulence in Hot Jet Flows; Enhanced Elliptic Grid Generation; Automated Knowledge Discovery From Simulators; Electro-Optical Modulator Bias Control Using Bipolar Pulses; Generative Representations for Automated Design of Robots; Mars-Approach Navigation Using In Situ Orbiters; Efficient Optimization of Low-Thrust Spacecraft Trajectories; Cylindrical Asymmetrical Capacitors for Use in Outer Space; Protecting Against Faults in JPL Spacecraft; Algorithm Optimally Allocates Actuation of a Spacecraft; and Radar Interferometer for Topographic Mapping of Glaciers and Ice Sheets.

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NASA NTRS2007

NASA Tech Briefs, August 2007

Topics include: Program Merges SAR Data on Terrain and Vegetation Heights; Using G(exp 4)FETs as a Data Router for In-Plane Crossing of Signal Paths; Two Algorithms for Processing Electronic Nose Data; Radiation-Tolerant Dual Data Bus; General-Purpose Front End for Real-Time Data Processing; Nanocomposite Photoelectrochemical Cells; Ultracapacitor-Powered Cordless Drill, Cumulative Timers for Microprocessors; Photocatalytic/Magnetic Composite Particles; Separation and Sealing of a Sample Container Using Brazing; Automated Aerial Refueling Hitches a Ride on AFF; Cobra Probes Containing Replaceable Thermocouples; High-Speed Noninvasive Eye-Tracking System; Detergent-Specific Membrane Protein Crystallization Screens; Evaporation-Cooled Protective Suits for Firefighters; Plasmonic Antenna Coupling for QWIPs; Electronic Tongue Containing Redox and Conductivity Sensors; Improved Heat-Stress Algorithm; A Method of Partly Automated Testing of Software; Rover Wheel-Actuated Tool Interface; and Second-Generation Electronic Nose.

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NASA NTRS2006

NASA Tech Briefs, June 2006

Topics covered include: Magnetic-Field-Response Measurement-Acquisition System; Platform for Testing Robotic Vehicles on Simulated Terrain; Interferometer for Low-Uncertainty Vector Metrology; Rayleigh Scattering for Measuring Flow in a Nozzle Testing Facility; "Virtual Feel" Capaciflectors; FETs Based on Doped Polyaniline/Polyethylene Oxide Fibers; Miniature Housings for Electronics With Standard Interfaces; Integrated Modeling Environment; Modified Recursive Hierarchical Segmentation of Data; Sizing Structures and Predicting Weight of a Spacecraft; Stress Testing of Data-Communication Networks; Framework for Flexible Security in Group Communications; Software for Collaborative Use of Large Interactive Displays; Microsphere Insulation Panels; Single-Wall Carbon Nanotube Anodes for Lithium Cells; Tantalum-Based Ceramics for Refractory Composites; Integral Flexure Mounts for Metal Mirrors for Cryogenic Use; Templates for Fabricating Nanowire/Nanoconduit- Based Devices; Measuring Vapors To Monitor the State of Cure of a Resin; Partial-Vacuum-Gasketed Electrochemical Corrosion Cell; Theodolite Ring Lights; Integrating Terrain Maps Into a Reactive Navigation Strategy; Reducing Centroid Error Through Model-Based Noise Reduction; Adaptive Modeling Language and Its Derivatives; Stable Satellite Orbits for Global Coverage of the Moon; and Low-Cost Propellant Launch From a Tethered Balloon

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NASA NTRS2006

NASA Tech Briefs, December 2006

Topic include: Inferring Gear Damage from Oil-Debris and Vibration Data; Forecasting of Storm-Surge Floods Using ADCIRC and Optimized DEMs; User Interactive Software for Analysis of Human Physiological Data; Representation of Serendipitous Scientific Data; Automatic Locking of Laser Frequency to an Absorption Peak; Self-Passivating Lithium/Solid Electrolyte/Iodine Cells; Four-Quadrant Analog Multipliers Using G4-FETs; Noise Source for Calibrating a Microwave Polarimeter; Hybrid Deployable Foam Antennas and Reflectors; Coating MCPs with AlN and GaN; Domed, 40-cm-Diameter Ion Optics for an Ion Thruster; Gesture-Controlled Interfaces for Self-Service Machines; Dynamically Alterable Arrays of Polymorphic Data Types; Identifying Trends in Deep Space Network Monitor Data; Predicting Lifetime of a Thermomechanically Loaded Component; Partial Automation of Requirements Tracing; Automated Synthesis of Architecture of Avionic Systems; SSRL Emergency Response Shore Tool; Wholly Aromatic Ether-Imides as n-Type Semiconductors; Carbon-Nanotube-Carpet Heat-Transfer Pads; Pulse-Flow Microencapsulation System; Automated Low-Gravitation Facility Would Make Optical Fibers; Alignment Cube with One Diffractive Face; Graphite Composite Booms with Integral Hinges; Tool for Sampling Permafrost on a Remote Planet; and Special Semaphore Scheme for UHF Spacecraft Communications.

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NASA NTRS2012

Radiation and Thermal Cycling Effects on EPC1001 Gallium Nitride Power Transistors

Electronics designed for use in NASA space missions are required to work efficiently and reliably under harsh environment conditions. These include radiation, extreme temperatures, and thermal cycling, to name a few. Information pertaining to performance of electronic parts and systems under hostile environments is very scarce, especially for new devices. Such data is very critical so that proper design is implemented in order to ensure mission success and to mitigate risks associated with exposure of on-board systems to the operational environment. In this work, newly-developed enhancement-mode field effect transistors (FET) based on gallium nitride (GaN) technology were exposed to various particles of ionizing radiation and to long-term thermal cycling over a wide temperature range. Data obtained on control (un-irradiated) and irradiated samples of these power transistors are presented and the results are discussed.

Patterson, Richard L.↗
NASA NTRS2013

NASA Tech Briefs, June 2013

Topics include: Cloud Absorption Radiometer Autonomous Navigation System - CANS, Software Method for Computed Tomography Cylinder Data Unwrapping, Re-slicing, and Analysis, Discrete Data Qualification System and Method Comprising Noise Series Fault Detection, Simple Laser Communications Terminal for Downlink from Earth Orbit at Rates Exceeding 10 Gb/s, Application Program Interface for the Orion Aerodynamics Database, Hyperspectral Imager-Tracker, Web Application Software for Ground Operations Planning Database (GOPDb) Management, Software Defined Radio with Parallelized Software Architecture, Compact Radar Transceiver with Included Calibration, Software Defined Radio with Parallelized Software Architecture, Phase Change Material Thermal Power Generator, The Thermal Hogan - A Means of Surviving the Lunar Night, Micromachined Active Magnetic Regenerator for Low-Temperature Magnetic Coolers, Nano-Ceramic Coated Plastics, Preparation of a Bimetal Using Mechanical Alloying for Environmental or Industrial Use, Phase Change Material for Temperature Control of Imager or Sounder on GOES Type Satellites in GEO, Dual-Compartment Inflatable Suitlock, Modular Connector Keying Concept, Genesis Ultrapure Water Megasonic Wafer Spin Cleaner, Piezoelectrically Initiated Pyrotechnic Igniter, Folding Elastic Thermal Surface - FETS, Multi-Pass Quadrupole Mass Analyzer, Lunar Sulfur Capture System, Environmental Qualification of a Single-Crystal Silicon Mirror for Spaceflight Use, Planar Superconducting Millimeter-Wave/Terahertz Channelizing Filter, Qualification of UHF Antenna for Extreme Martian Thermal Environments, Ensemble Eclipse: A Process for Prefab Development Environment for the Ensemble Project, ISS Live!, Space Operations Learning Center (SOLC) iPhone/iPad Application, Software to Compare NPP HDF5 Data Files, Planetary Data Systems (PDS) Imaging Node Atlas II, Automatic Calibration of an Airborne Imaging System to an Inertial Navigation Unit, Translating MAPGEN to ASPEN for MER, Support Routines for In Situ Image Processing, and Semi-Supervised Eigenbasis Novelty Detection.

Source record↗
NASA NTRS2017

Current Source Logic Gate

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Krasowski, Michael J.↗
NASA NTRS2018

Cryogenic Parametric Characterization of Gallium Nitride Switches

This report presents the parametric characterization results of four GaN field-effect transistor (FET) devices from three manufacturers, one of which is a cascode device, and compares those results to a Si power metal-oxide-semiconductor fieldeffect transistor (MOSFET) and a SiC power MOSFET. The devices were first characterized at ambient temperature, then at cryogenic temperatures down to -196 C (LN2 temperature), and finally at ambient temperature again in the event that the device parameters were permanently affected by the cryogenic temperatures. In general, the results indicate that the GaN devices show significant improvement overall at cryogenic temperatures in the parameters characterized, such as onresistance and leakage currents, compared to the Si and SiC devices. The results show that the SiC device tested should not be used at cryogenic temperatures due to the significant increase in on-resistance. The results also show that the GaN and Si parameters characterized were either not affected by the cryogenic temperatures or changed by no more than +/-20 percent post LN2 submersion. The device that exhibited the most parametric change post LN2 submersion was the SiC power MOSFET in its leakage currents.

Gonzalez, Marcelo C.↗
NASA NTRS2018

Current Source Logic Gate

A current source logic gate with depletion mode field effect transistor ("FET") transistors and resistors may include a current source, a current steering switch input stage, and a resistor divider level shifting output stage. The current source may include a transistor and a current source resistor. The current steering switch input stage may include a transistor to steer current to set an output stage bias point depending on an input logic signal state. The resistor divider level shifting output stage may include a first resistor and a second resistor to set the output stage point and produce valid output logic signal states. The transistor of the current steering switch input stage may function as a switch to provide at least two operating points.

Krasowski, Michael J.↗
NASA NTRSDate not supplied

Long Term Integration and Implementation of ATD-2 Phase 3 Capabilities

Topics include review of recommendations from an earlier Surface CDM (Collaborative Decision Making) Team (SCT) & Flow Evaluation Team (FET) meeting, support of alternative work flows, and software integration in operational systems. The briefing also identifies incorporation of ATD-2 Phase 3 capabilities into the alternative work flows.

ATD-2, IADS↗
NASA NTRSDate not supplied

Surface Meets TOS Update & Potential Future Work

This briefing for the Surface CDM (Collaborative Decision Making) Team (SCT) & Flow Evaluation Team (FET) discussed the foundational data/information quality needs to enable a collaborative TOS concept that includes surface. The primary goal of this briefing was on soliciting broad feedback from the operator community. This discusses the importance of the Earliest Off Block Time (EOBT) as a predictor for improving NAS demand predictions as well as possible areas where SCT/FET could contribute to uses of Trajectory Option Sets in future FAA systems.

ATD-2, IADS, SCT/FET↗