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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 397 records · Page 22
All sourcesNASA NTRSDOE OSTI
NASA NTRS2000

Advanced Atmospheric Water Vapor DIAL Detection System

Measurement of atmospheric water vapor is very important for understanding the Earth's climate and water cycle. The remote sensing Differential Absorption Lidar (DIAL) technique is a powerful method to perform such measurement from aircraft and space. This thesis describes a new advanced detection system, which incorporates major improvements regarding sensitivity and size. These improvements include a low noise advanced avalanche photodiode detector, a custom analog circuit, a 14-bit digitizer, a microcontroller for on board averaging and finally a fast computer interface. This thesis describes the design and validation of this new water vapor DIAL detection system which was integrated onto a small Printed Circuit Board (PCB) with minimal weight and power consumption. Comparing its measurements to an existing DIAL system for aerosol and water vapor profiling validated the detection system.

Refaat, Tamer F.↗
NASA NTRS2004

Silicon-Germanium Films Grown on Sapphire for Ka-Band Communications Applications

NASA's vision in the space communications area is to develop a broadband data network in which there is a high degree of interconnectivity among the various satellite systems, ground stations, and wired systems. To accomplish this goal, we will need complex electronic circuits integrating analog and digital data handling at the Ka-band (26 to 40 GHz). The purpose of this project is to show the feasibility of a new technology for Ka-band communications applications, namely silicon germanium (SiGe) on sapphire. This new technology will have several advantages in comparison to the existing silicon-substrate- based circuits. The main advantages are extremely low parasitic reactances that enable much higher quality active and passive components, better device isolation, higher radiation tolerance, and the integration of digital and analog circuitry on a single chip.

Alterovitz, Samuel A.↗
NASA NTRS2011

GEOSTAR-II: A Prototype Water Vapor Imager/Sounder for the Path Mission

We describe the development and progress of the GeoSTAR-II risk reduction activity for the NASA Earth Science Decadal Survey PATH Mission. The activity directly addresses areas of technical risk including the system design, low noise receiver production, sub-array development, signal distribution and digital signal processing.

Monolithic Microwave Integrated Circuit (MMIC)↗
NASA NTRS1979

Digital phase shifter

Device requiring only TTL integrated circuits and single 5-volt power supply, varies phase shift of digital input over approximate range of 15 to 165 deg.

Perry, M. G.↗
NASA NTRS1983

Flight test validation of a design procedure for digital autopilots

Commercially available general aviation autopilots are currently in transition from an analogue circuit system to a computer implemented digital flight control system. Well known advantages of the digital autopilot include enhanced modes, self-test capacity, fault detection, and greater computational capacity. A digital autopilot's computational capacity can be used to full advantage by increasing the sophistication of the digital autopilot's chief function, stability and control. NASA's Langley Research Center has been pursuing the development of direct digital design tools for aircraft stabilization systems for several years. This effort has most recently been directed towards the development and realization of multi-mode digital autopilots for GA aircraft, conducted under a SPIFR-related program called the General Aviation Terminal Operations Research (GATOR) Program. This presentation focuses on the implementation and testing of a candidate multi-mode autopilot designed using these newly developed tools.

Bryant, W. H.↗
DOE OSTI2025

Event-driven readout development: testing of the EDWARD65P1 chip with integrated event generators

Building on a prototype readout integrated circuit for segmented silicon sensors with the EDWARD event-driven readout architecture, the front-end in each pixel was replaced by a hardware generator to verify readout performance, ensuring no data loss, consistent priority handling, and speed verification. Here, this generator produces Poisson-distributed readout requests with individually tunable rates per pixel via a digitally controlled oscillator. The resulting EDWARD65P1 test ASIC is a 32×32 pixel matrix with a 100 μm pitch, equipped with digital event generators simulating radiation hits at user-defined rates. Test results for this new design are presented.

47 OTHER INSTRUMENTATION↗
NASA NTRS1991

HYMOSS signal processing for pushbroom spectral imaging

The objective of the Pushbroom Spectral Imaging Program was to develop on-focal plane electronics which compensate for detector array non-uniformities. The approach taken was to implement a simple two point calibration algorithm on focal plane which allows for offset and linear gain correction. The key on focal plane features which made this technique feasible was the use of a high quality transimpedance amplifier (TIA) and an analog-to-digital converter for each detector channel. Gain compensation is accomplished by varying the feedback capacitance of the integrate and dump TIA. Offset correction is performed by storing offsets in a special on focal plane offset register and digitally subtracting the offsets from the readout data during the multiplexing operation. A custom integrated circuit was designed, fabricated, and tested on this program which proved that nonuniformity compensated, analog-to-digital converting circuits may be used to read out infrared detectors. Irvine Sensors Corporation (ISC) successfully demonstrated the following innovative on-focal-plane functions that allow for correction of detector non-uniformities. Most of the circuit functions demonstrated on this program are finding their way onto future IC's because of their impact on reduced downstream processing, increased focal plane performance, simplified focal plane control, reduced number of dewar connections, as well as the noise immunity of a digital interface dewar. The potential commercial applications for this integrated circuit are primarily in imaging systems. These imaging systems may be used for: security monitoring systems, manufacturing process monitoring, robotics, and for spectral imaging when used in analytical instrumentation.

Ludwig, David E.↗
NASA NTRS2001

Synchronized Docking System

A synchronized target subsystem for use in an automated docking system for docking a chase vehicle with a target vehicle wherein the chase vehicle is provided with a video camera for feeding digitized frames to an image processing unit which feeds signals to a control circuit. The control circuit turns on the video camera to digitize a background frame which will include the target vehicle. After the camera grabs the background frame the control circuit turns on a light, which is carried by carried on the chase vehicle and aimed at the target vehicle, and signals the video camera to digitize a foreground frame. A light sensing circuit on the target vehicle receives the light from the chase vehicle and connects a power supply to lights on the target vehicle such that when the foreground frame is digitized the Lights on the target vehicle will show in the foreground frame. Die image processing unit subtracts the background frame from the foreground frame and provides a docking signal.

Richard T Howard↗
NASA NTRS1984

Programmable scan/read circuitry for charge coupled device imaging detectors

A circuit for scanning and outputting the induced charges in a solid state charge coupled device (CCD) image detector is disclosed in an image detection system for use in a spacecraft attitude control system. The image detection system includes timing control circuitry for selectively controlling the output of the CCD detector so that video outputs are provided only with respect to induced charges corresponding to predetermined sensing element lines of the CCD detector. The timing control circuit and the analog to digital converter are controlled by a programmed microprocessor which defines the video outputs to be converted and further controls the timing control circuit so that no video outputs are provided during the delay associated with analog to digital conversion.

Salomon, P. M.↗
NASA NTRS1993

Packet Controller For Wireless Headset

Packet-message controller implements communications protocol of network of wireless headsets. Designed for headset application, readily adapted to other uses; slight modification enables controller to implement Integrated Services Digital Network (ISDN) X.25 protocol, giving far-reaching applications in telecommunications. Circuit converts continuous voice signals into digital packets of data and vice versa. Operates in master or slave mode. Controller reduced to single complementary metal oxide/semiconductor integrated-circuit chip. Occupies minimal space in headset and consumes little power, extending life of headset battery.

Christensen, Kurt K.↗
NASA NTRS2001

Synchronized Autonomous Docking System

A synchronized target subsystem for use in an automated docking system for docking a chase vehicle with a target vehicle wherein the chase vehicle is provided with a video camera for feeding digitized frames to an image processing unit which controls a timing circuit. 'Me timing circuit turns on the video camera to digitize a foreground frame and at the same time turns on a transmitter on the chase vehicle. A power generating antenna on the target vehicle receives the transmitted signal from the transmitter and actuates lights on the chase vehicle so that these lights appear in the foreground frame. After the foreground frame has been grabbed, the timing circuit turns the transmitter off and signals the video camera to digitize a background frame. The image processing unit subtracts the background frame from the foreground frame and provides a docking signal.

Richard T Howard↗
NASA NTRS1975

Development of a breadboard design of a high-performance, high-reliability switching regulator

A comparison of two potential conversion methods, the series inverter and the inductive energy transfer (IET) conversion technique, is presented. The investigations showed that a characteristic of the series inverter circuit (high equalizing current values in each half cycle) could not be accomplished with available components, and the investigations continued with the IET circuit only. An IET circuit system was built with the use of computer-aided design in a 2, 4, and 8 stage configuration, and these stages were staggered 180, 90, and 45 degrees, respectively. All stages were pulsewidth modulated to regulate over an input voltage range from 200 to 400 volts dc at a regulated output voltage of 56 volts. The output power capability was 100 to 500 watts for the 2 and 8 stage configuration and 50 to 250 watts for the 4 stage configuration. Equal control of up to eight 45 degree staggered stages was accomplished through the use of a digital-to-analog control circuit. Equal power sharing of all stages was achieved through a new technique using an inductively coupled balancing circuit. Conclusions are listed.

Lindena, S. J.↗
NASA NTRS1978

Transient response to three-phase faults on a wind turbine generator

In order to obtain a measure of its responses to short circuits a large horizontal axis wind turbine generator was modeled and its performance was simulated on a digital computer. Simulation of short circuit faults on the synchronous alternator of a wind turbine generator, without resort to the classical assumptions generally made for that analysis, indicates that maximum clearing times for the system tied to an infinite bus are longer than the typical clearing times for equivalent capacity conventional machines. Also, maximum clearing times are independent of tower shadow and wind shear. Variation of circuit conditions produce the modifications in the transient response predicted by analysis.

Gilbert, L. J.↗
NASA NTRS1967

Advanced transducers Final report

Design of digital adapter with limit storage for transducers for use in multichannel digital data acquisition system

INTEGRATED CIRCUIT↗
NASA NTRS2005

Characteristics Of Ferroelectric Logic Gates Using a Spice-Based Model

A SPICE-based model of an n-channel ferroelectric field effect transistor has been developed based on both theoretical and empirical data. This model was used to generate the I-V characteristic of several logic gates. The use of ferroelectric field effect transistors in memory circuits is being developed by several organizations. The use of FFETs in other circuits, both analog and digital needs to be better understood. The ability of FFETs to have different characteristics depending on the initial polarization can be used to create logic gates. These gates can have properties not available to standard CMOS logic gates, such as memory, reconfigurability and memory. This paper investigates basic properties of FFET logic gates. It models FFET inverter, NAND gate and multi-input NAND gate. The I-V characteristics of the gates are presented as well as transfer characteristics and timing. The model used is a SPICE-based model developed from empirical data from actual Ferroelectric transistors. It simulates all major characteristics of the ferroelectric transistor, including polarization, hysteresis and decay. Contrasts are made of the differences between FFET logic gates and CMOS logic gates. FFET parameters are varied to show the effect on the overall gate. A recodigurable gate is investigated which is not possible with CMOS circuits. The paper concludes that FFETs can be used in logic gates and have several advantages over standard CMOS gates.

MacLeod, Todd C.↗
NASA NTRS1973

Space shuttle main engine controller assembly, phase C-D

System design and system analysis and simulation are slightly behind schedule, while design verification testing has improved. Input/output circuit design has improved, but digital computer unit (DCU) and mechanical design continue to lag. Part procurement was impacted by delays in printed circuit board, assembly drawing releases. These are the result of problems in generating suitable printed circuit artwork for the very complex and high density multilayer boards.

Source record↗
NASA NTRSDate not supplied

Radiation-Hard Parallel Readout Circuit for Low-Frequency Voltage Signal Measurements

NASA Goddard Space Flight Center (GSFC) has successfully developed and tested a custom-designed low-noise multi-channel digitizer (MCD) application specific integrated circuit (ASIC) for operation in harsh radiation environments. The MCD-ASIC is optimized for low-frequency and low-voltage signal measurements from sensors and transducers. It has 20 input channels where each channel is comprised of auto-zeroed chopper variable-gain amplifier, post amplifier, and a second order ∑∆ modulator. ∑∆ analog-to-digital converter (ADC) relies on oversampling and noise shaping to achieve high-resolution conversion. However, the MCD-ASIC requires digital filtering and decimation to convert the output single bit streams from the ADC to useful data words. A parallel digital platform such as a field-programmable-gate-array (FPGA) is highly suitable to fully leverage the capabilities of the MCD-ASIC. The FPGA controls the MCD-ASIC via serial peripheral interface (SPI) protocol and acquires data from it. A Python-script communicates with the FPGA board through a USB interface on a cross operating platform. Using this architecture, the system is capable of monitoring up to 20 voltage readout channels simultaneously in a real-time manner. Each channel’s parameters can be programmed independently allowing maximum user versatility. In this paper, we present analysis of the analog front-end, the implementation of the digital processing unit on the FPGA, and provide noise performance results from the MCD-ASIC readout.

ASIC↗
NASA NTRS1990

Statistical circuit design for yield improvement in CMOS circuits

This paper addresses the statistical design of CMOS integrated circuits for improved parametric yield. The work uses the Monte Carlo technique of circuit simulation to obtain an unbiased estimation of the yield. A simple graphical analysis tool, the yield factor histogram, is presented. The yield factor histograms are generated by a new computer program called SPICENTER. Using the yield factor histograms, the most sensitive circuit parameters are noted, and their nominal values are changed to improve the yield. Two basic CMOS example circuits, one analog and one digital, are chosen and their designs are 'centered' to illustrate the use of the yield factor histograms for statistical circuit design.

Kamath, H. J.↗