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At least 379 records · Page 21
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Innovative recycling of high purity silver from silicon solar cells by acid leaching and ultrasonication

Precious and scarce silver (Ag) is used as a front electrical contact in silicon solar panels. With massive amounts of solar panel waste coming to end-of-life, it is imperative to recover all the Ag from these modules. In this paper, we propose a novel method to easily reclaim Ag from end-of-life silicon solar cells using low concentration sulfuric acid (H 2 SO 4 ) leaching followed by ultrasonication. Our process simplifies the Ag recycling procedure by directly recovering the Ag contacts from solar cells, eliminating the need for secondary precipitation/electrodeposition. First, scanning electron microscopy (SEM) with energy dispersive X-ray spectroscopy (EDX) and X-ray photoelectron spectroscopy (XPS) was used to study the leaching and ultrasonication process on rejected solar wafers. Next, a solar panel from landfill was heated in a furnace to burn off the polymer encapsulant. The silicon wafers were then collected from the burning process and leached in 2 M H 2 SO 4 at two different shaking speeds for 48 hours at room temperature. Finally, the end-of-life silicon wafer pieces were collected, sonicated in water, and then the sonication water was centrifuged to show a proof-of-concept to recover the Ag contacts. Inductively coupled plasma optical emission spectroscopy (ICPOES) is used to monitor dissolved elements in the leachate as a function of time and shaking speed. XPS is used to evaluate the composition of the silicon cell wafer surface before and after H 2 SO 4 leaching. SEM is used to image the recovered Ag contacts morphology and EDX confirms the recovered particles contain high amounts of Ag. Furthermore, a proposed schematic illustrates the authors’ hypothesis for the peeling mechanism.

14 SOLAR ENERGY↗
DOE OSTI2025

Low embodied energy and carbon, high lifetime silicon boules via a combined chemical vapor deposition/float zone process

This work evaluates a new process route to making float zone (Fz)-quality silicon wafers using a combination of computational fluid dynamics (CFD) modeling and technoeconomic analysis. Our analysis finds that the new process competes with Czochralski (Cz)-grown wafers on a levelized cost of energy system level. The new process also decreases embodied energy and carbon of silicon photovoltaics (PV) by ~6x circumventing the energy-costly Siemens process used in polycrystalline silicon (poly-Si) production plants to generate feedstock for Fz and Cz boules. Instead of using poly-Si from the Siemens process to feed crystallization, the new process uses the high-purity, trichlorosilane (TCS) precursor gas to grow a poly-Si feed rod in-situ during a modified Fz1,2 boule growth process. The gas-to-boule float zone process enables opportunity to produce high-purity (low metals and oxygen content), uniformly doped single crystal silicon boules and wafers with high bulk lifetimes (τ bulk > 15 ms) to enable higher efficiency cells (>27 %) with fewer known degradation mechanisms than Czochralski (Cz)-grown wafers. These benefits reduce the levelized cost of electricity (LCOE) of PV-produced electricity. Here we show the results of our CFD and chemical modeling of the process to prove feasibility and economic viability.

14 SOLAR ENERGY↗
DOE OSTI2024

Continuously tunable uniaxial strain control of van der Waals heterostructure devices

Uniaxial strain has been widely used as a powerful tool for investigating and controlling the properties of quantum materials. However, existing strain techniques have so far mostly been limited to use with bulk crystals. Although recent progress has been made in extending the application of strain to two-dimensional van der Waals (vdW) heterostructures, these techniques have been limited to optical characterization and extremely simple electrical device geometries. Here, we report a piezoelectric-based in situ uniaxial strain technique enabling simultaneous electrical transport and optical spectroscopy characterization of dual-gated vdW heterostructure devices. Critically, our technique remains compatible with vdW heterostructure devices of arbitrary complexity fabricated on conventional silicon/silicon dioxide wafer substrates. We demonstrate a large and continuously tunable strain of up to –0.15% at millikelvin temperatures, with larger strain values also likely achievable. We quantify the strain transmission from the silicon wafer to the vdW heterostructure, and further demonstrate the ability of strain to modify the electronic properties of twisted bilayer graphene. Our technique provides a highly versatile new method for exploring the effect of uniaxial strain on both the electrical and optical properties of vdW heterostructures and can be easily extended to include additional characterization techniques.

Electrical properties and parameters↗
DOE OSTI2021

Sonic Lift-off of GaAs-based Solar Cells with Reduced Surface Facets

Spalling has been proposed as a promising kerfless technique for slicing thin wafers and devices, enhancing the wafer yield from an ingot by reducing kerf-losses and enabling substrate reuse for the case of costly devices. The main challenge of spalling is to control the roughness and thickness variation of the spalled wafers that can be as high as 100% of the wafer thickness. Here, we have shown previously that the thickness variations are largely influenced by the interaction of the crack front with its own reflected waves. Herein we show that through Sonic Lift-off we can offer a modification to standard spalling technologies that minimizes the interaction of reflected waves with the crack front during lift-off of GaAs(100)-based solar cells. We show that the average surface facets amplitude can be reduced by 96% while obtaining a high quality bulk with no discernible residual strain as measured by PL. The resulting spalling depth can easily be tuned from 100 µm to less than 15µm. The electrical characterization of the Sonic lift-off cell shows no degradation of the VOC and a power conversion within 99% relative of a non-spalled baseline.

42 ENGINEERING↗
DOE OSTI2021

Facet Suppression in (100) GaAs Spalling via Use of a Nanoimprint Lithography Release Layer

Controlled spalling is an emerging technique developed for fast, scalable wafer reuse, but for the commonly used (100) GaAs substrate system, the process leaves large facets ranging from 5-10 µm on the wafer surface. Removing them for wafer reuse requires a costly re-polishing step that limits the cost savings that can be achieved with spalling as a wafer reuse technique. In this study, we investigate facet suppression in spalling of (100) GaAs by redirecting the fracture front along features created by buried nanoimprint lithography (NIL)-patterned SiO 2 . We show successful facet suppression using patterns that result in favorable fracture along the SiO 2 /GaAs interface. The results from this work show NIL patterned interlayers are a promising method for faceting suppression in (100) GaAs spalling.

controlled spalling↗
DOE OSTI2022

Fabrication and Irradiation Behavior of Thulium Sesquioxide

The results of reactor irradiation of thulium sesquioxide are discussed, along with chemical and physical properties and wafer fabrication. Sintered densities up to 90% of theoretical were obtained in target wafers using oxide reprocessed to obtain readily sinterable powder. Irradiation to about 1.8 w/g did not change the microstructure of the wafers although some wafers broke, probably because of mechanical stresses in target and disassembly.

36 MATERIALS SCIENCE↗
DOE OSTI2026

A Path to III-V Photovoltaic Cost Reduction Combining GaAs (211) Spalling with Halide Vapor Phase Epitaxy

This presentation is an overview of the following, Spalling on 211 oriented wafers produces flat surface without faceting: 1) Demonstrated spall on entire 2" wafer; 2) GaAs and GaInP grown on 211 wafers by HVPE; and 3) Promising cell with VOC=1.02 V and IQE-1. Next steps: 1) Grow cell on spalled wafer and 2) Growth studies to improve material and cell on 211 substrates.

14 SOLAR ENERGY↗
DOE OSTI2025

Quality assurance and quality control of the $26~\text {m}^2$ SiPM production for the DarkSide-20k dark matter experiment

DarkSide-20k is a novel liquid argon dark matter detector currently under construction at the Laboratori Nazionali del Gran Sasso (LNGS) of the Istituto Nazionale di Fisica Nucleare (INFN) that will push the sensitivity for Weakly Interacting Massive Particle (WIMP) detection into the neutrino fog. The core of the apparatus is a dual-phase Time Projection Chamber (TPC), filled with 50 tonnes of low radioactivity underground argon (UAr) acting as the WIMP target. NUV-HD-cryo Silicon Photomultipliers (SiPM)s designed by Fondazione Bruno Kessler (FBK) (Trento, Italy) were selected as the photon sensors covering two $10.5~\text {m}^2$ Optical Planes, one at each end of the TPC, and a total of $5~\text {m}^2$ photosensitive surface for the liquid argon veto detectors. This paper describes the Quality Assurance and Quality Control (QA/QC) plan and procedures accompanying the production of FBK NUV-HD-cryo SiPM wafers manufactured by LFoundry s.r.l. (Avezzano, AQ, Italy). SiPM characteristics are measured at 77 K at the wafer level with a custom-designed probe station. As of March 2025, 1314 of the 1400 production wafers (94% of the total) for DarkSide-20k were tested. The wafer yield is $93.2\pm 2.5$%, which exceeds the 80% specification defined in the original DarkSide-20k production plan.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1971

Shielding method for polycrystalline and epitaxy growths

Technique prevents silicon wafers from adhering to susceptor following silicon epitaxial deposition. Annular ring of refractory material goes around wafer during epitaxial deposit. Silicon is deposited on ring, susceptor, and portions of wafer. Ring breaks away from susceptor and wafer and no silicon undergrowth occurs.

Bue, J. L.↗
NASA NTRS1976

Economic analysis of low cost silicon sheet produced from Czochralski grown material

This study shows that the lower limits for manufacturing add-on costs to convert polysilicon to wafers is in the range of $22 to $26/sq m with the cost about equally divided between the crystal growth and wafering processes. However, the $22 to $26/sq m cost limit should be viewed as an asymptote since it is based on multicharge or continuous growth configurations, solidification rates in excess of 2 Kg/hr, multiblade wafering and a slice plus kerf of .045 cm. It should also be emphasized that the results of this study are based on as-sawn wafers, 100% yields (growth and slicing) and no profit. To the first approximation, the limiting cost factors are crucible material and furnace parts for growth and blade material and slurry for slicing.

Koliwad, K. M.↗
NASA NTRS1978

Effect of multiblade slurry saw induced damage on silicon solar cells

A correlation between the optimum etch loss and the depth of damage is established using wafers produced by the Multiblade Slurry (MBS) and the Internal Diameter (ID) saws. The observations are based on the measurement of the performance of solar cells fabricated on these wafers. Sample preparation and test results are described and the following conclusions are made: (1) the amount of silicon removal necessary for optimum solar cell performance coincides with the depth of saw-induced damage; (2) optimization of cell performance is not affected by the method of silicon removal; (3) sawing conditions should be optimized to minimize the extent of saw-induced damage; (4) the MBS saw is found to induce damage to a lesser extent; (5) since the extent of damage in MBS-sawn wafers is in the limit of etch loss required in texture etching, it is possible to achieve optimum improvement in cell performance by merely texture etching the surface of as-sawn wafers.

Daud, T.↗
NASA NTRS1980

Development and fabrication of a solar cell junction processing system

Experiments were completed which indicate that single-pulse, liquid-phase epitaxial regrowth is the optimum technique for pulsed electron beam annealing of ion implantation damage in silicon wafers. An electron beam which covers the entire area of the wafer was chosen for the solar cell processor. Beam control experiments to improve beam propagation and to test the concept of partial space charge and current neutralization were initiated. The electrical parameters of the pulsed electron beam subsystem were chosen on the basis of computer calculations and past experience in pulsed electron accelerator design and operation. The pulser, designated SPI-PULSE 7000, is designed to anneal 10 cm diameter silicon wafers at a rate of 30 per minute. The preliminary design of the major elements of the SPI-PULSE 7000 was completed, and the detailed design of many of the components begun. These elements include a capacitive energy store and charging system, an electron accelerator, a beam control system, a wafer handling system and pressure and vacuum assemblies.

Halvason, W.↗
NASA NTRS1981

X-ray topography study of complex silicon microcircuits

The correlation between the yield of silicon microcircuits wafers versus defects observed in X-ray topographs produced by a high speed curved wafer X-ray topographic camera was investigated. Most of the topographs were made after final wafer probe. Results indicated that most high volume silicon wafer processing does not need X-ray topography as a routine process control. It is further indicated that in changing any existing process or developing a new process the technique can be of significant benefit.

Parker, D. L.↗
NASA NTRS1981

Silicon solar cell process development, fabrication and analysis

Solar cells were fabricated from EFG ribbons dendritic webs, cast ingots by heat exchanger method, and cast ingots by ubiquitous crystallization process. Baseline and other process variations were applied to fabricate solar cells. EFG ribbons grown in a carbon-containing gas atmosphere showed significant improvement in silicon quality. Baseline solar cells from dendritic webs of various runs indicated that the quality of the webs under investigation was not as good as the conventional CZ silicon, showing an average minority carrier diffusion length of about 60 um versus 120 um of CZ wafers. Detail evaluation of large cast ingots by HEM showed ingot reproducibility problems from run to run and uniformity problems of sheet quality within an ingot. Initial evaluation of the wafers prepared from the cast polycrystalline ingots by UCP suggested that the quality of the wafers from this process is considerably lower than the conventional CZ wafers. Overall performance was relatively uniform, except for a few cells which showed shunting problems caused by inclusions.

Yoo, H. I.↗
NASA NTRS1982

Design and use of multiple blade slurry sawing in a production atmosphere

The technique and uses of the multiple blade slurry (MBS) saw are considered. Multiple bands of steel are arranged in a frame and the frame is reciprocated with the steel bands to a workpiece, while simultaneously applying abrasive at the point of contact. The blades wear slots in the workpiece and progress through the piece resulting in several parts of wafers. The transition to MBA from diamond slicing is justified by savings resulting from minimized kerf losses, minimized subsurface damage, and improved surface quality off the saw. This allows wafering much closer to finished thickness specifications. The current state of the art MBS technology must be significantly improved if the low cost solar array (LSA) goals are to be attained. It is concluded that although MBS will never be the answer to every wafering requirement, the economical production of wafers to LSA project specifications will be achieved.

Lynah, F. P., Jr.↗
NASA NTRS1982

Field experience with various slicing methods

Wafer slicing using internal diameter (ID) saw, multiblade slurry (MBS) saw and multiwire slurry (MWS) saw techniques were evaluated. Wafer parameters such as bow, taper, and roughness which may not be important factors for solar cell fabrication, were considerably better for ID saw than those of the MBS and MWS saw. Analysis of add-on slicing cost indicated that machine productivity seems to be a major limiting factor for ID saw, while expendible material costs are a major factor for both MBS and MWS saw. Slicing experience indicated that the most important factors controling final wafer cost are: (1) silicon cost (wafer thickness + kerf loss); (2) add-on slicing cost, and (3) mechanical yield. There is a very strong interaction between these parameters, suggesting a necessity of optimization of these parameters.

Yoo, H. I.↗
NASA NTRS1982

Silicon solar cell process development, fabrication and analysis

For UCP Si, randomly selected wafers and wafers cut from two specific ingots were studied. For the randomly selected wafers, a moderate gettering diffusion had little effect. Moreover, an efficiency up to 14% AMI was achieved with advanced processes. For the two specific UCP ingots, ingot #5848-13C displayed severe impurity effects as shown by lower 3sc in the middle of the ingot and low CFF in the top of the ingot. Also the middle portions of this ingot responded to a series of progressively more severe gettering diffusion. Unexplained was the fact that severely gettered samples of this ingot displayed a negative light biased effect on the minority carrier diffusion length while the nongettered or moderately gettered ones had the more conventional positive light biased effect on diffusion length. On the other hand, ingot C-4-21A did not have the problem of ingot 5848-13C and behaved like to the randomly selected wafers. The top half of the ingot was shown to be slightly superior to the bottom half, but moderate gettering helped to narrow the gap.

Iles, P. A.↗
NASA NTRS1985

Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

Buehler, M. G.↗