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At least 379 records · Page 21

Parallel Conjugate Gradient: Effects of Ordering Strategies, Programming Paradigms, and Architectural Platforms

The Conjugate Gradient (CG) algorithm is perhaps the best-known iterative technique to solve sparse linear systems that are symmetric and positive definite. A sparse matrix-vector multiply (SPMV) usually accounts for most of the floating-point operations within a CG iteration. In this paper, we investigate the effects of various ordering and partitioning strategies on the performance of parallel CG and SPMV using different programming paradigms and architectures. Results show that for this class of applications, ordering significantly improves overall performance, that cache reuse may be more important than reducing communication, and that it is possible to achieve message passing performance using shared memory constructs through careful data ordering and distribution. However, a multi-threaded implementation of CG on the Tera MTA does not require special ordering or partitioning to obtain high efficiency and scalability.

Oliker, Leonid↗

Data-dependence Profiling to Enable Safe Thread Level Speculation

Data-dependence profling is a technique that enables a com- piler to judiciously decide when the execution of a loop | which the compiler could not prove to be dependence free | should be speculated through the use of Thread Level Spec- ulation (TLS). The data collected by a data-dependence pro- fler can be used to predict if may dependencies reported by a compiler static analysis are likely to materialize at runtime. A cost analysis can then be used to decide that some loops with a lower probability of dependence should be specula- tively parallelized. This paper addresses the question as to whether a loops' dependence behaviour changes when the in- put to the program changes | a study of 57 different bench- marks indicates that it usually does not change. Then the paper describes SpecEval, an automatic speculative paral- lelization framework that uses single-input data-dependence profles to find speculation candidates in the SPEC2006 and PolyBench/C benchmarks. This paper also presents a per- formance evaluation of TLS implementation in IBM's Blue- Gene/Q supercomputer and shows that the performance of TLS is affected by several factors, including the number of speculated loops, the execution-time coverage of speculated loops, the miss-speculation overhead, the L1 cache miss rate and the effect on dynamic instruction path length.

Bhattacharyya, Arnamoy↗

Particle signatures of magnetic topology at the magnetopause: AMPTE/CCE observations

Electron distributions at energies above 50 eV have been found to be a sensitive indicator of magnetic topology for magnetopause crossings of the AMPTE/CCE spacecraft. Progressing from the magnetosheath to the magnetosphere two abrupt transitions occur. First, the magnetosheath electron population directed either parallel or antiparallel to the magnetic field is replaced by a streaming, heated magnetosheath electron population. The other half of the distribution is unchanged. The region with unidirectional, heated magnetosheath electrons is identified as the magnetosheath boundary layer (MSBL). Second, the unheated magnetosheath electron population is replaced by a heated population nearly identical to the population encountered in the MSBL, resulting in a symmetric counterstreaming distribution. The region populated by the bidirectional heated magnetosheath electrons is identified as the low-latitude boundary layer (LLBL). The MSBL and LLBL identified by the electron transitions are the same as the regions identified using ion composition measurements. The magnetosheath-MSBL transition reflects a change in magnetic topology from a solar wind field line to one that threads the magnetopause, and the existence of a magnetosheath-MSBL transition implies that the magnetopause is open. When the current layer is easily identified, the MSBL-LLBL transition coincides with the magnetopause current layer, indicating that the magnetosheath electrons are heated in the current layer. Both magnetosheath-MSBL and MSBL-LLBL transitions are observed for low as well as high magnetic shears. Moreover, the transitions are particularly clear for low shear implying that magnetic topology boundaries are sharp even when abrupt changes in the field and other plasma parameters are absent. Furthermore, for low magnetic shear, solar wind ions with low parallel drift speeds make up the majority of the LLBL population indicating that the magnetosheath plasma has convected directly across the magnetosheath plasma has converted directly across the magnetopause. These observations are consistent with quasi-steady, high-latitude reconnection and indicate that the signatures of this reconnection geometry are commonly present in the subpolar region.

Fuselier, S. A.↗

System, methods and apparatus for program optimization for multi-threaded processor architectures

Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least two multi-stage execution units that allow for parallel execution of tasks. The first custom computing apparatus optimizes the code for parallelism, locality of operations and contiguity of memory accesses on the second computing apparatus. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

42 ENGINEERING↗

Towards Superior Software Portability with SHAD and HPX C++ Libraries

As hardware architectures and software stacks complexity grows, development productivity, performance and software portability, quickly evolve from desirable features to actual needs. SHAD, the Scalable High-performance Algorithms and Data-structures C++ library is designed to mitigate these issues: it provides general purpose building blocks as well as high-level custom utilities, and offers a shared-memory programming abstraction which facilitates the programming of complex systems, scaling up to High Performance Computing clusters. SHAD’s portability is achieved through an abstract runtime interface, which decouples the upper layers of the library and hides the low level details of the underlying architecture. This layer enables SHAD to interface with different runtime/threading systems, e.g. Intel TBB and Global Memory and Threading (GMT). However, current backends targeting distributed systems, rely on a centralized controller which may possibly limit scalability up to hundreds of nodes and creates a network hot spot due to all to one communication for synchronization, and possibly resulting in degraded performance at high process counts. In this research, we explore HPX, the C++ standard library for parallelism and concurrency, as an additional backend in support of the SHAD library, and present the methodologies in support of local and remote task executions in SHAD with respect to HPX. Finally, we evaluate the proposed system by comparing against existing backends of SHAD and analyzing their performance on C++ Standard Template Library algorithms.

Wu, Nanmiao↗

Reader set encoding for directory of shared cache memory in multiprocessor system

In a parallel processing system with speculative execution, conflict checking occurs in a directory lookup of a cache memory that is shared by all processors. In each case, the same physical memory address will map to the same set of that cache, no matter which processor originated that access. The directory includes a dynamic reader set encoding, indicating what speculative threads have read a particular line. This reader set encoding is used in conflict checking. A bitset encoding is used to specify particular threads that have read the line.

97 MATHEMATICS AND COMPUTING↗

Repairable and Reconfigurable Structured Liquid Circuits

The advance of printed electronics is significantly bolstered by the development of liquid-state electronics that overcome the inherent limitations in flexibility and reconfigurability of solid-state electronics. By integrating the biocompatibility and conductivity of sulfonated polyaniline (S-PANI) and phytic acid (PA) with the reconfigurability of structured liquids, highly conductive all-liquid threads are developed. The dense packing and overlap of PA/S-PANI complexes at an oil/water interface promotes in-plane electron transport, and standard four-point probe measurements of PA/S-PANI interfacial assemblies demonstrate enhanced electrical properties. Notably, the rapid jetting of the ink phase into the matrix phase allows for liquid threads to be printed, enabling the fabrication of large-scale, conductive pathways between two electrodes and liquid circuits. Upon mechanical cleavage of the liquid wires, circuits can be broken, but will easily self-repair using an electric field, making this motif useful in the design of switches as well as restoring conductive pathways in series or in parallel. In conclusion, the demonstrated flexibility and reconfigurability these PA/S-PANI wires possess hold significant promise for their practical use in the design of flexible and adaptive bioelectronics that can be repaired on demand, signifying a transformative step in the evolution of liquid electronic materials.

36 MATERIALS SCIENCE↗

Some calculations bearing on the heating and cooling of quiescent prominences

The evolution of heat along and perpendicular to magnetic fields threading quiescent prominences is discussed. It was shown that while heating of prominence material can occur on a time scale of the order of 1000's, individual flux tubes are effectively thermally insulated from neighboring tubes, since the transverse heat conduction time scale is of the order of 10000 per year. The exact solution to the one-dimensional parallel heat conduction problem is shown to differ significantly from the approximate solution of Ioshpa (1965). It was suggested that uneven heating of a quiescent prominence by the surrounding solar corona may contribute to surges and/or the 'winking' phenomenon recorded in many quiescent prominences. The signature of such a temperature pulse would be a sharp brightening of continuum radiation with a correlated decrease in the free-bound emission, followed by a slow recovery of both to their pre-heat pulse levels.

Lerche, I.↗

Writing ROOT Data in Parallel with TBufferMerger

Experiments at the Large Hadron Collider (LHC) produce tens of petabytes of new data in ROOT format per year that need to be processed and analysed. In the next decade, following the planned upgrades of the LHC and its detectors, this data production rate is expected to increase at least ten-fold. Therefore, optimizing the ROOT I/O subsystem is of critical importance to the success of the LHC physics programme. This contribution presents ROOT’s approach for writing data from multiple threads to a single output file in an efficient way. Technical aspects of the implementation—the TBufferMerger class—and programming model examples are described. Measurements of runtime performance and the overall improvement relative to the case of serial data writing are also discussed.

47 OTHER INSTRUMENTATION↗

On the Scalability of Data Reduction Techniques in Current and Upcoming HPC Systems from an Application Perspective

We implement and benchmark parallel I/O methods for the fully-manycore driven particle-in-cell code PIConGPU. Identifying throughput and overall I/O size as a major challenge for applications on today’s and future HPC systems, we present a scaling law characterizing performance bottlenecks in state-of-the-art approaches for data reduction. Consequently, we propose, implement and verify multi-threaded data-transformations for the I/O library ADIOS as a feasible way to trade underutilized host-side compute potential on heterogeneous systems for reduced I/O latency.

Huebl, Axel↗

The Minos Computing Library: Efficient Parallel Programming for Extremely Heterogeneous Systems

Hardware specialization has become the silver bullet to achieve efficient high performance, from Systems-on-Chip systems, where hardware specialization can be ``extreme'', to large-scale HPC systems. As the complexity of the systems increases, so does the complexity of programming such architectures in a portable way. This work introduces the Minos Computing Library (MCL), as system software, programming model, and programming model runtime that facilitate programming extremely heterogeneous systems. MCL supports the execution of several multi-threaded applications within the same compute node, performs asynchronous execution of application tasks, efficiently balances computation across hardware resources, and provides performance portability. We show that code developed on a personal desktop automatically scales up to fully utilize powerful workstations with 8 GPUs and down to power-efficient embedded systems. MCL provides up to 17.5x speedup over OpenCL on NVIDIA DGX-1 systems and up to 1.88x speedup on single-GPU systems. In multi-application workloads, MCL dynamically resource allocation provides up to 2.43x performance improvement over manual, static allocation of computing resources.

Gioiosa, Roberto↗

Reverse-Mode Algorithmic Differentiation of an OpenMP-Parallel Compressible Flow Solver

y Reverse-mode algorithmic differentiation (AD) is an established method for obtaining adjoint derivatives of computer simulation applications. In computational fluid dynamics (CFD), adjoint derivatives of a cost function output such as drag or lift with respect to design parameters such as surface coordinates or geometry control points are a key ingredient for shape optimization, uncertainty quantification and flow control. The computational cost of CFD applications and their derivatives makes it essential to use high-performance computing hardware efficiently, including multi- and many-core architectures. Nevertheless, OpenMP is not supported in most AD tools, and previously shown methods achieve poor scalability of the derivative code. We present the AD of an OpenMP-parallelized finite volume compressible flow solver for unstructured meshes. Our approach enables us to reuse the parallelization of the original code in the computation of adjoint derivatives. The method works by identifying code segments that can be differentiated in reverse-mode without changing their memory access pattern. The OpenMP parallelization is integrated into the derivative code during the build process in a way that is robust to modifications of the original code and independent of the OpenMP support of the differentiation tool. We show the scalability of our adjoint CFD solver on test cases ranging from thousands to millions of finite volume mesh cells on CPUs with up to 16 threads as well as on an Intel XeonPhi card with 236 threads. We demonstrate that our approach is more practical to implement for production-sized CFD codes and produces more efficient adjoint derivative code than previously shown AD methods.

Huckelheim, Jan↗

Parallel sort with a ranged, partitioned key-value store in a high perfomance computing environment

Improved sorting techniques are provided that perform a parallel sort using a ranged, partitioned key-value store in a high performance computing (HPC) environment. A plurality of input data files comprising unsorted key-value data in a partitioned key-value store are sorted. The partitioned key-value store comprises a range server for each of a plurality of ranges. Each input data file has an associated reader thread. Each reader thread reads the unsorted key-value data in the corresponding input data file and performs a local sort of the unsorted key-value data to generate sorted key-value data. A plurality of sorted, ranged subsets of each of the sorted key-value data are generated based on the plurality of ranges. Each sorted, ranged subset corresponds to a given one of the ranges and is provided to one of the range servers corresponding to the range of the sorted, ranged subset. Each range server sorts the received sorted, ranged subsets and provides a sorted range. A plurality of the sorted ranges are concatenated to obtain a globally sorted result.

97 MATHEMATICS AND COMPUTING↗

Induced spin-accumulation and spin-polarization in a quantum-dot ring by using magnetic quantum dots and Rashba spin-orbit effect

The effect of magnetic contacts on spin-dependent electron transport and spin-accumulation in a quantum ring, which is threaded by a magnetic flux, is studied. The quantum ring is made up of four quantum dots, where two of them possess magnetic structure and other ones are subjected to the Rashba spin-orbit coupling. The magnetic quantum dots, referred to as magnetic quantum contacts, are connected to two external leads. Two different configurations of magnetic moments of the quantum contacts are considered; the parallel and the anti-parallel ones. When the magnetic moments are parallel, the degeneracy between the transmission coefficients of spin-up and spin-down electrons is lifted and the system can be adjusted to operate as a spin-filter. In addition, the accumulation of spin-up and spin-down electrons in non-magnetic quantum dots are different in the case of parallel magnetic moments. When the intra-dot Coulomb interaction is taken into account, we find that the electron interactions participate in separation between the accumulations of electrons with different spin directions in non-magnetic quantum dots. Furthermore, the spin-accumulation in non-magnetic quantum dots can be tuned in the both parallel and anti-parallel magnetic moments by adjusting the Rashba spin-orbit strength and the magnetic flux. Thus, the quantum ring with magnetic quantum contacts could be utilized to create tunable local magnetic moments which can be used in designing optimized nanodevices.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

An overview of the Opus language and runtime system

We have recently introduced a new language, called Opus, which provides a set of Fortran language extensions that allow for integrated support of task and data parallelism. lt also provides shared data abstractions (SDA's) as a method for communication and synchronization among these tasks. In this paper, we first provide a brief description of the language features and then focus on both the language-dependent and language-independent parts of the runtime system that support the language. The language-independent portion of the runtime system supports lightweight threads across multiple address spaces, and is built upon existing lightweight thread and communication systems. The language-dependent portion of the runtime system supports conditional invocation of SDA methods and distributed SDA argument handling.

Mehrotra, Piyush↗

Planning for Pre-Exascale Platform Environment (Fiscal Year 2015 Level 2 Milestone 5216)

This Plan for ASC Pre-Exascale Platform Environments document constitutes the deliverable for the fiscal year 2015 (FY15) Advanced Simulation and Computing (ASC) Program Level 2 milestone Planning for Pre-Exascale Platform Environment. It acknowledges and quantifies challenges and recognized gaps for moving the ASC Program towards effective use of exascale platforms and recommends strategies to address these gaps. This document also presents an update to the concerns, strategies, and plans presented in the FY08 predecessor document that dealt with the upcoming (at the time) petascale high performance computing (HPC) platforms. With the looming push towards exascale systems, a review of the earlier document was appropriate in light of the myriad architectural choices currently under consideration. The ASC Program believes the platforms to be fielded in the 2020s will be fundamentally different systems that stress ASC’s ability to modify codes to take full advantage of new or unique features. In addition, the scale of components will increase the difficulty of maintaining an errorfree system, thus driving new approaches to resilience and error detection/correction. The code revamps of the past, from serial- to vector-centric code to distributed memory to threaded implementations, will be revisited as codes adapt to a new message passing interface (MPI) plus “x” or more advanced and dynamic programming models based on architectural specifics. Development efforts are already underway in some cases, and more difficult or uncertain aspects of the new architectures will require research and analysis that may inform future directions for program choices. In addition, the potential diversity of system architectures may require parallel if not duplicative efforts to analyze and modify environments, codes, subsystems, libraries, debugging tools, and performance analysis techniques as well as exploring new monitoring methodologies. It is difficult if not impossible to selectively eliminate some of these activities until more information is available through simulations of potential architectures, analysis of systems designs, and informed study of commodity technologies that will be the constituent parts of future platforms.

97 MATHEMATICS AND COMPUTING↗

Bringing OpenCL to Commodity RISC-V CPUs

The importance of open-source hardware has been increasing in recent years with the introduction of the RISC-V Open ISA. This has also accelerated the push for support of the open-source software stack from compiler tools to full-blown operating systems. Parallel computing with today’s Application Programming Interfaces such as OpenCL has proven to be effective at leveraging the parallelism in commodity multi-core processors and programmable parallel accelerators. However, to the best of our knowledge, there is currently no publicly available implementation of OpenCL targeting commodity RISC-V processors that is accessible to the open-source community. Besides opening RISC-V to the existing rich variety of scientific parallel applications, OpenCL also provides access to a unique genre of benchmarks useful in computer architecture research. In this work, we extended an Open-source implementation of OpenCL to target RISC-V CPUs. Our work not only cover commodity multi-core RISC-V processors, but also plethora of low- profile embedded RISC-V CPUs that often do not support atomic instructions or multi-threading.

Tine, Blaise↗