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Large-scale integrated (LSI) devices fabricated with integrated injection logic (I2L) were studied by both heavy ion experiments and device analysis to determine the upset threshold, the charge collection volumes and ultimately the probability for upset in the galactic cosmic ray spectrum. The devices studied, the SEP9900A, the SBP9989 and the P-Code generator were fabricated by Texas Instruments, Inc.
Simple modification of oscilloscope probe allows easy detection of floating inputs or tristate outputs in digital-IC's. Oscilloscope probe easily modified with 1/4 W resistor and switch for detecting floating inputs in CMOS logic circuits.
Control signals for phase-delay rectifiers, which require a variable firing angle that ranges from 0 deg to 180 deg, are derived from line-to-line 3-phase signals and both positive and negative firing angle control signals which are generated by comparing current command and actual current. Line-to-line phases are transformed into line-to-neutral phases and integrated to produce 90 deg phase delayed signals that are inverted to produce three cosine signals, such that for each its maximum occurs at the intersection of positive half cycles of the other two phases which are inputs to other inverters. At the same time, both positive and negative (inverted) phase sync signals are generated for each phase by comparing each with the next and producing a square wave when it is greater. Ramp, sync and firing angle controls signals are than used in combinational logic to generate the gate firing control signals SCR gate drives which fire SCR devices in a bridge circuit.
This paper deals with the issue of designing microprocessor based systems with testability in mind. The ease of eventual testability should be a design consideration from the earliest design stage. Design guidelines with explicit examples for ease of testability are given. The issue of testing microprocessors as contrasted with testing random logic design is addressed, and procedures are delineated for the testability of microprocessors. Microprocessor testability design guidelines are discussed both at the design stage of the microprocessor itself as well as at the stage where the processor is imbedded as a component in a larger system. Specific instances and examples of a collection of design do's and don'ts are provided.
Unit-delay simulation, event driven simulation, zero-delay simulation, simulation techniques, 2-valued versus multivalued logic, network initialization, gate operations and alternate network representations, parallel versus serial mode simulation fault modelling, extension of multiprocessor systems, and simulation timing are discussed. Functional level networks, gate equivalent circuits, the prototype BDX-930 network model, fault models, identifying detected faults for BGLOSS are discussed. Preprocessor tasks, postprocessor tasks, executive tasks, and a library of bliss coded macros for GGLOSS are also discussed.
Circuit for checking two-line complementary-logic bits for single faults used as building block for self-checking memory interface for Hammingcoded data. Intended for such applications as fault-tolerant computing, data handling, and data transmission. Circuit performs exclusive-OR function. Many such circuits combined produce complete memory interface with both detection and correction abilities.
Subjects were required to discover the structure of a logical network whose links were invisible. Network structure had to be inferred from the behavior of the components after a failure. It was hypothesized that since such failure diagnosis tasks often draw on spatial processes, a good deal of spatial complexity in the network should affect network discovery. Results show that the ability to discover the linkages in the network is directly related to the spatial complexity of the pathway described by the linkages. This effect was generally independent of the amount of evidence available to subjects about the existence of the link. These results raise the question of whether inferences about spatially complex pathways were simply not made, or whether they were made but not retained because of a high load on memory resources.
Improvements were made to the Adaptive Maneuvering Logic (AML) computer program, a computer-generated, air-to-air combat opponent. The primary improvement was incorporating a measure of performance, the exchange ratio, defined as the statistical measure of number of enemy kills divided by number of friendly losses. This measure was used to test a new modification of the AML's combat tactics. When the new version of the AML competed against the old version, the new version won with an exchange ratio of 1.4.
A proof-of-concept computer program called IGGLOSS (Interim Generalized Gate Logic Software Simulator) was developed and is discussed. The simulator engine was designed to perform stochastic estimation of self test coverage (fault-detection latency times) of digital computers or systems. A major attribute of the IGGLOSS is its high-speed simulation: 9.5 x 1,000,000 gates/cpu sec for nonfaulted circuits and 4.4 x 1,000,000 gates/cpu sec for faulted circuits on a VAX 11/780 host computer.
The nonlinear phenomena of signal beam saturation, pump beam depletion, and optically controlled coupling coefficient of two-beam interaction in photorefractive materials are analyzed. Applications of these phenomena to digital logic operations is discussed and supported by experimental results obtained in photorefractive BaTiO3.
The Adaptive Maneuvering Logic (AML) computer program simulates close-in, one-on-one air-to-air combat between two fighter aircraft. Three important improvements are described. First, the previously available versions of AML were examined for their suitability as a baseline program. The selected program was then revised to eliminate some programming bugs which were uncovered over the years. A listing of this baseline program is included. Second, the equations governing the motion of the aircraft were completely revised. This resulted in a model with substantially higher fidelity than the original equations of motion provided. It also completely eliminated the over-the-top problem, which occurred in the older versions when the AML-driven aircraft attempted a vertical or near vertical loop. Third, the requirements for a versatile generic, yet realistic, aircraft model were studied and implemented in the program. The report contains detailed tables which make the generic aircraft to be either a modern, high performance aircraft, an older high performance aircraft, or a previous generation jet fighter.
A digital logic controller provides instruction execution times on the order of 50 nanoseconds and employing read-only memory outputting instructions to a pipeline register, a portion of each instruction providing a status-select control signal and address signals for controlling selection of the next instruction from the read-only memory.
The United States space transportation plans are discussed with emphasis on returning the Titan and the Shuttle to operational status. In particular, Shuttle enhancements via advanced solid rocket boosters and replacement of solid rocket boosters by liquid rocket boosters are examined. The Shuttle-C vehicle is then discussed as the next logical step that could provide a heavy launch capability in the early 1990s. The Shuttle-C will provide assured and flexible access to space for large Centaur-class payloads, for Space Station assembly, and for planetary missions.
Adaptive, self-organizing concurrent systems (ASOCS) that combine self-organization with massive parallelism for such applications as adaptive logic devices, robotics, process control, and system malfunction management, are presently discussed. In ASOCS, an adaptive network composed of many simple computing elements operating in combinational and asynchronous fashion is used and problems are specified by presenting if-then rules to the system in the form of Boolean conjunctions. During data processing, which is a different operational phase from adaptation, the network acts as a parallel hardware circuit.
The author presents a condensed exposition of some basic ideas underlying fuzzy logic and describes some representative applications. The discussion covers basic principles; meaning representation and inference; basic rules of inference; and the linguistic variable and its application to fuzzy control.
This paper describes an abstract reference model of cooperating rule-based systems (CRBSs). The model is intended to assist in the planning, specification, development, and verification of space information systems involving multiple, distributed, communicating rule-based systems. The functions performed in ground control systems are described, and five types of rule-based systems that could be used in such centers are identified. The interactions between rule-based systems are examined, and the unique requirements of such systems are addressed. A four-layer logical model is discussed which provides a framework for discussing solutions to unique CRBS requirements. The elements and operations at each layer are described.
Voltage regulator bypassed to supply starting current. Starting or "pullup" circuit supplies large inrush of current required by erasable programmable logic device (EPLD) while being turned on. Operates only during such intervals of high demand for current and has little effect any other time. Performs needed bypass, acting as current-dependent shunt connecting battery or other source of power more nearly directly to EPLD. Input capacitor of regulator removed when starting circuit installed, reducing probability of damage to transistor in event of short circuit in or across load.
A primary flight display format was integrated with the flight guidance and control system logic in support of various flight tests conducted with the NASA Transport Systems Research Vehicle B-737-100 airplane. The functional operation of the flight guidance mode control panel and the corresponding primary flight display formats are presented.