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At least 379 records · Page 21
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

Hardware Architecture Study for NASA's Space Software Defined Radios

This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

Reinhart, Richard C.↗
NASA NTRS1982

LANDSAT and radar mapping of intrusive rocks in SE-Brazil

The feasibility of intrusive rock mapping was investigated and criteria for regional geological mapping established at the scale of 1:500,00 in polycyclic and polymetamorphic areas using the logic method of photointerpretation of LANDSAT imagery and radar from the RADAMBRASIL project. The spectral behavior of intrusive rocks, was evaluated using the interactive multispectral image analysis system (Image-100). The region of Campos (city) in northern Rio de Janeiro State was selected as the study area and digital imagery processing and pattern recognition techniques were applied. Various maps at the 2:250,000 scale were obtained to evaluate the results of automatic data processing.

Parada, N. D. J.↗
NASA NTRS2004

Four-Channel PC/104 MIL-STD-1553 Circuit Board

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Cox, Gary L.↗
NASA NTRS1981

Flight test results for the F-8 digital fly-by-wire aircraft control sensor analytic redundancy management technique

This paper reviews the formulation and flight test results of an algorithm to detect and isolate the first failure of any one of twelve duplex control sensor signals being monitored. The technique uses like-signal differences for fault detection while relying upon analytic redundancy relationships among unlike quantities to isolate the faulty sensor. The fault isolation logic utilizes the modified sequential probability ratio test, which explicitly accommodates the inevitable irreducible low frequency errors present in the analytic redundancy residuals. In addition, the algorithm uses sensor output selftest, which takes advantage of the duplex sensor structure by immediately removing a highly erratic sensor from control calculations and analytic redundancy relationships while awaiting a definitive fault isolation decision via analytic redundancy. This study represents a proof of concept demonstration of a methodology that can be applied to duplex or higher flight control sensor configurations and, in addition, can monitor the health of one simplex signal per analytic redundancy relationship.

Deckert, J. C.↗
NASA NTRS1974

Digital adaptive flight control design using single stage model following indices

Simple mechanical linkages are often unable to cope with many control problems associated with high-performance aircraft. This has led to the development of digital fly-by-wire control systems and in particular digital adaptive controllers that can be efficiently adjusted during system operation. To this effect, a control law has been derived based upon the minimization of a single-stage weighted combination of control energy and the squared error between the states of a linear plant and model. This control logic is interfaced with an on-line weighted least-squares estimator and a Kalman state filter. The utility of the resultant control system is illustrated by its application to the linearized dynamics of a typical fighter aircraft.

Alag, G.↗
NASA NTRS1975

Users manual for flight control design programs

Computer programs for the design of analog and digital flight control systems are documented. The program DIGADAPT uses linear-quadratic-gaussian synthesis algorithms in the design of command response controllers and state estimators, and it applies covariance propagation analysis to the selection of sampling intervals for digital systems. Program SCHED executes correlation and regression analyses for the development of gain and trim schedules to be used in open-loop explicit-adaptive control laws. A linear-time-varying simulation of aircraft motions is provided by the program TVHIS, which includes guidance and control logic, as well as models for control actuator dynamics. The programs are coded in FORTRAN and are compiled and executed on both IBM and CDC computers.

Nalbandian, J. Y.↗
NASA NTRS1999

Test Results for the Automated Rendezvous and Capture System

The Automated Rendezvous and Capture (AR&C) system was designed and tested at NASA's Marshall Space Flight Center (MSFC) to demonstrate technologies and mission strategies for automated rendezvous and docking of spacecraft in Earth orbit, The system incorporates some of the latest innovations in Global Positioning, System space navigation, laser sensor technologies and automated mission sequencing algorithms. The system's initial design and integration was completed in 1998 and has undergone testing at MSFC. This paper describes the major components of the AR&C system and presents results from the official system tests performed in MSFC's Flight Robotics Laboratory with digital simulations and hardware in the loop tests. The results show that the AR&C system can safely and reliably perform automated rendezvous and docking missions in the absence of system failures with 100 percent success. When system failures are included, the system uses its automated collision avoidance maneuver logic to recover in a safe manner. The primary objective of the AR&C project is to prove that by designing a safe and robust automated system, mission operations cost can be reduced by decreasing the personnel required for mission design, preflight planning and training required for crewed rendezvous and docking missions.

Cruzen, Craig↗
NASA NTRS1986

Ulysses: A functional description and simulation software system

Current design tools for digital circuits and systems are not well-integrated among the behavioral, gate, and transistor levels of design. Ulysses is a prototype software system that consists of a description language, a description compiler, and a simulator that make no distinction among these levels. The language is uniform over the entire range of logical descriptions, the description is hierarchical with no fundamental restrictions on depth or mixing of levels, and the simulator is fully integrated with the description. The structure of the language, compiler, and simulator are described in terms of their relationships to the abstractions of physical systems that are made in order to create logical descriptions and models of behavior.

Griswold, T. W.↗
NASA NTRS1982

A high speed implementation of the random decrement algorithm

The algorithm is useful for measuring net system damping levels in stochastic processes and for the development of equivalent linearized system response models. The algorithm works by summing together all subrecords which occur after predefined threshold level is crossed. The random decrement signature is normally developed by scanning stored data and adding subrecords together. The high speed implementation of the random decrement algorithm exploits the digital character of sampled data and uses fixed record lengths of 2(n) samples to greatly speed up the process. The contributions to the random decrement signature of each data point was calculated only once and in the same sequence as the data were taken. A hardware implementation of the algorithm using random logic is diagrammed and the process is shown to be limited only by the record size and the threshold crossing frequency of the sampled data. With a hardware cycle time of 200 ns and 1024 point signature, a threshold crossing frequency of 5000 Hertz can be processed and a stably averaged signature presented in real time.

Kiraly, L. J.↗
NASA NTRS1983

A high-speed implementation of the random decrement algorithm

The algorithm is useful for measuring net system damping levels in stochastic processes and for the development of equivalent linearized system response models. The algorithm works by summing together all subrecords which occur after predefined threshold level is crossed. The random decrement signature is normally developed by scanning stored data and adding subrecords together. The high speed implementation of the random decrement algorithm exploits the digital character of sampled data and uses fixed record lengths of 2(n) samples to greatly speed up the process. The contributions to the random decrement signature of each data point was calculated only once and in the same sequence as the data were taken. A hardware implementation of the algorithm using random logic is diagrammed and the process is shown to be limited only by the record size and the threshold crossing frequency of the sampled data. With a hardware cycle time of 200 ns and 1024 point signature, a threshold crossing frequency of 5000 Hertz can be processed and a stably averaged signature presented in real time.

Kiraly, L. J.↗
NASA NTRS1983

Documentation for the machine-readable version of the Stellar Spectrophotometric Atlas, 3130 A lamda 10800 A of Gunn and Stryker (1983)

A detailed description of the machine-readable version of the atlas as it is currently beng distributed from the Astronomical Data Center is given. The data were obtained with the Oke multichannel scanner on the 5-meter Hale reflector for purposes of synthesizing galaxy spectra, and the digitized atlas contains normalized spectral energy distributions, computed colors, scan line and continuum indices for 175 selected stars covering the complete ranges of spectral type and luminosity class. The documentation includes a byte-by-byte format description, a table of the indigenous characteristics of the magnetic tape file, and a sample listing of logical records exactly as they are recorded on the tape.

Source record↗
NASA NTRS1984

Documentation for the machine-readable version of the Stellar Spectrophotometric Atlas, 3130 A lambda 10800 A of Gunn and Stryker (1983)

The machine-readable version of the Atlas as it is currently being distributed from the Astronomical Data Center is described. The data were obtained with the Oke multichannel scanner on the 5-meter Hale reflector for purposes of synthesizing galaxy spectra, and the digitized Atlas contains normalized spectral energy distributions, computed colors, scan line and continuum indices for 175 selected stars covering the complete ranges of spectral type and luminosity class. The documentation includes a byte-by-byte format description, a table of the indigenous characteristics of the magnetic tape file, and a sample listing of logical records exactly as they are recorded on the tape.

Warren, W. H., Jr.↗
NASA NTRS1992

Optical computing and neural networks; Proceedings of the Meeting, National Chiao Tung Univ., Hsinchu, Taiwan, Dec. 16, 17, 1992

The present conference discusses optical neural networks, photorefractive nonlinear optics, optical pattern recognition, digital and analog processors, and holography and its applications. Attention is given to bifurcating optical information processing, neural structures in digital halftoning, an exemplar-based optical neural net classifier for color pattern recognition, volume storage in photorefractive disks, and microlaser-based compact optical neuroprocessors. Also treated are the optical implementation of a feature-enhanced optical interpattern-associative neural network model and its optical implementation, an optical pattern binary dual-rail logic gate module, a theoretical analysis for holographic associative memories, joint transform correlators, image addition and subtraction via the Talbot effect, and optical wavelet-matched filters. (No individual items are abstracted in this volume)

Hsu, Ken-Yuh↗
NASA NTRS2004

Taking evolutionary circuit design from experimentation to implementation: some useful techniques and a silicon demonstration

Current techniques in evolutionary synthesis of analogue and digital circuits designed at transistor level have focused on achieving the desired functional response, without paying sufficient attention to issues needed for a practical implementation of the resulting solution. No silicon fabrication of circuits with topologies designed by evolution has been done before, leaving open questions on the feasibility of the evolutionary circuit design approach, as well as on how high-performance, robust, or portable such designs could be when implemented in hardware. It is argued that moving from evolutionary 'design-for experimentation' to 'design-for-implementation' requires, beyond inclusion in the fitness function of measures indicative of circuit evaluation factors such as power consumption and robustness to temperature variations, the addition of certain evaluation techniques that are not common in conventional design. Several such techniques that were found to be useful in evolving designs for implementation are presented; some are general, and some are particular to the problem domain of transistor-level logic design, used here as a target application. The example used here is a multifunction NAND/NOR logic gate circuit, for which evolution obtained a creative circuit topology more compact than what has been achieved by multiplexing a NAND and a NOR gate. The circuit was fabricated in a 0.5 mum CMOS technology and silicon tests showed good correspondence with the simulations.

digital circuits designs↗
NASA NTRS1974

A self-reorganizing digital flight control system for aircraft

This paper presents a design method for digital self-reorganizing control systems which is optimally tolerant of failures in aircraft sensors. The functions of this system are accomplished with software instead of the popular and costly technique of hardware duplication. The theoretical development, based on M-ary hypothesis testing, results in a bank of M Kalman filters operating in parallel in the failure detection logic. A moving window of the innovations of each Kalman filter drives the detection logic to decide the failure state of the system. The detection logic also selects the optimal state estimate (for control logic) from the bank of Kalman filters. The design process is applied to the design of a self-reorganizing control system for a current configuration of the space shuttle orbiter at Mach 5 and 120,000 feet. The failure detection capabilities of the system are demonstrated using a real-time simulation of the system with noisy sensors.

Montgomery, R. C.↗
NASA NTRS1978

The Space Shuttle Ground Terminal Delta Modulation System

Shuttle voice processing uses a Variable Slope Delta Modulation scheme which is a variant of the ABATE algorithm. This paper summarizes the ground terminal subsystem which processes the multiplexed voice and telemetry data digital sequence in the downlink processing and digitizes the voice signal in the uplink processing. The Delta Modulation System (DMS) performance characteristics are given in terms of an intelligibility test score and in terms of time and frequency responses measured on a production system developed for NASA Goddard Space Flight Center. Implementation details of the encoder and decoder algorithms are given in terms of the circuit logic used to implement them.

Auger, R. L.↗
NASA NTRS1984

Augmentor transient capability of an F100 engine equipped with a digital electronic engine control

An F100 augmented turbofan engine equipped with digital electronic engine control (DEEC) system was evaluated. The engine was equipped with a specially modified augmentor to provide improved steady state and transient augmentor capability. The combination of the DEEC and the modified augmentor was evaluated in sea level and altitude facility tests and then in four different flight phases in an F-15 aircraft. The augmentor configuration, logic, and test results are presented.

Burcham, F. W., Jr.↗