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At least 379 records · Page 21

All sources NASA NTRS DOE OSTI

NASA NTRS1991

Synchronized computational architecture for generalized bilateral control of robot arms

A master six degree of freedom Force Reflecting Hand Controller (FRHC) is available at a master site where a received image displays, in essentially real time, a remote robotic manipulator which is being controlled in the corresponding six degree freedom by command signals which are transmitted to the remote site in accordance with the movement of the FRHC at the master site. Software is user-initiated at the master site in order to establish the basic system conditions, and then a physical movement of the FRHC in Cartesean space is reflected at the master site by six absolute numbers that are sensed, translated and computed as a difference signal relative to the earlier position. The change in position is then transmitted in that differential signal form over a high speed synchronized bilateral communication channel which simultaneously returns robot-sensed response information to the master site as forces applied to the FRHC so that the FRHC reflects the feel of what is taking place at the remote site. A system wide clock rate is selected at a sufficiently high rate that the operator at the master site experiences the Force Reflecting operation in real time.

Szakaly, Zoltan F.↗

NASA NTRS2010

Flagging and Correction of Pattern Noise in the Kepler Focal Plane Array

In order for Kepler to achieve its required less than 20 PPM photometric precision for magnitude 12 and brighter stars, instrument-induced variations in the CCD readout bias pattern (our "2D black image"), which are either fixed or slowly varying in time, must be identified and the corresponding pixels either corrected or removed from further data processing. The two principle sources of these readout bias variations are crosstalk between the 84 science CCDs and the 4 fine guidance sensor (FGS) CCDs and a high frequency amplifier oscillation on less than 40% of the CCD readout channels. The crosstalk produces a synchronous pattern in the 2D black image with time-variation observed in less than 10% of individual pixel bias histories. We will describe a method of removing the crosstalk signal using continuously-collected data from masked and over-clocked image regions (our "collateral data"), and occasionally-collected full-frame images and reverse-clocked readout signals. We use this same set to detect regions affected by the oscillating amplifiers. The oscillations manifest as time-varying moir pattern and rolling bands in the affected channels. Because this effect reduces the performance in only a small fraction of the array at any given time, we have developed an approach for flagging suspect data. The flags will provide the necessary means to resolve any potential ambiguity between instrument-induced variations and real photometric variations in a target time series. We will also evaluate the effectiveness of these techniques using flight data from background and selected target pixels.

Kolodziejczak, Jeffery J.↗

NASA NTRS1972

Utilization of FSK communications for time

The method of time control at a radio station for time signal transmission using frequency shift keying, is discussed. Methods for extracting a recovered clock at the receiver are described. Results of a test involving the methods of processing time signals are presented. The requirements for adapting Precise Time and Time Interval control to a communications system are analyzed. A method for reducing the time required for synchronization or identification of messages and the fallout from the communication system to passive timekeeping users are reported.

Stone, R. R., Jr.↗

NASA NTRS2005

Clocks and timing in the NASA Deep Space Network

A new timing system has been developed for the NASA Deep Space Network (DSN) and is currently in the final stages of integration, testing and implementation in all three DSN sites. The DSN is a distributed antenna network for deep space communication, whose facilities are continuously engaged in spacecraft tracking, Very Long Baseline Interferometry (VLBI) or Radio Astronomy activities. Its primary components consist of three Deep Space Communication Centers (DSCC) separated nearly equidistant around the Earth in California, USA; Spain; and Australia. Within each DSCC, synchronized, low jitter timing signals must be distributed to many users over distances of up to 30 kilometers. The design criteria for the timing system required state of the art stability and jitter performance, but also extremely high operability and reliability. This paper describes some of the key features and recent system performance data as measured both in the laboratory and the operational DSN.

clocks↗

NASA NTRS1980

An ultrasonic plethysmograph for space flight applications

The development of an ultrasonic plethysmograph based on the transit time measurement principle is reported, which meets the space-imposed requirements for evaluating cardiovascular deconditioning. It consists of a pulse generator, pulse receiver amplifier, voltage comparator, synchronous pulse generator, elapsed time counter, and transmit and receive piezoelectric crystals resonant at 2 MHz and of 3 mm diameter. The transit time for an ultrasonic pulse to propagate across a limb cross section is computed in a digital fashion using a 32 MHz clock, and resolution is 0.049 mm with the range being approximately 200 mm. Experimental results regarding dynamic system response were found comparable in both accuracy and sensitivity to those of a Whitney strain gage using a 50 torr venous occlusion.

Bhagat, P. K.↗

NASA NTRS1972

Handbook of operation and maintenance instructions for Model 5208A bit synchronizer unit

Electrical/mechanical characteristics, operation, theory of operation, parts list, and electrical diagrams for the model 5208A bit synchronizer unit are provided. The unit is capable of performing the functions of bit synchronization and signal conditioning on demodulated wave trains containing amplitude, frequency, and phase distortions, as well as additive noise. Operating frequencies in the 1 to 27 MHz bit rate range are accommodated through the use of discrete frequency plug-in subunits. The unit provides 0 and 180 degree clocks and either a single signal hard decision, or a three bit quantized soft decision data output.

Source record↗

NASA NTRS2012

Measurement Techniques for Clock Jitter

NASA is in the process of modernizing its communications infrastructure to accompany the development of a Crew Exploration Vehicle (CEV) to replace the shuttle. With this effort comes the opportunity to infuse more advanced coded modulation techniques, including low-density parity-check (LDPC) codes that offer greater coding gains than the current capability. However, in order to take full advantage of these codes, the ground segment receiver synchronization loops must be able to operate at a lower signal-to-noise ratio (SNR) than supported by equipment currently in use.

Lansdowne, Chatwin↗

NASA NTRS1976

Development of a drive system for a sequential space camera

Breadboard models of single and dual motor drives for the shutter, claw and magazine of a space camera system were designed and tested. The single motor technique utilizes a single electronically commutated motor to drive the claw and shutter without resorting to a solenoid actuated clutch for pulse operation. Shutter speed is established by a combination of the cinemode speed and the opening of the conventional DAC two piece shutter. Pulse mode operation is obtained by applying power at a fixed clock rate and removing power at an appropriate point in the mechanical cycle such that the motor comes to rest by system friction. The dual motor approach utilizes a stepper motor to drive the shutter and an electronically commutated dc motor to drive the claw and magazine functions. The motors are synchronized electronically.

Sharpsteen, J. T.↗

NASA NTRS2011

Frame Synchronization Without Attached Sync Markers

We describe a method to synchronize codeword frames without making use of attached synchronization markers (ASMs). Instead, the synchronizer identifies the code structure present in the received symbols, by operating the decoder for a handful of iterations at each possible symbol offset and forming an appropriate metric. This method is computationally more complex and doesn't perform as well as frame synchronizers that utilize an ASM; nevertheless, the new synchronizer acquires frame synchronization in about two seconds when using a 600 kbps software decoder, and would take about 15 milliseconds on prototype hardware. It also eliminates the need for the ASMs, which is an attractive feature for short uplink codes whose coding gain would be diminished by the overheard of ASM bits. The lack of ASMs also would simplify clock distribution for the AR4JA low-density parity-check (LDPC) codes and adds a small amount to the coding gain as well (up to 0.2 dB).

Hamkins, Jon↗

NASA NTRS1990

50 Mbps free space direct detection laser diode optical communication system with Q = 4 PPM signaling

A 50 Mbps direct detection optical communication system for use in an intersatellite link was constructed with an AlGaAs laser diode transmitter and a silicon avalanche photodiode photodetector. The system used a Q = 4 PPM format. The receiver consisted of a maximum likelihood PPM detector and a timing recovery subsystem. The PPM slot clock was recovered at the receiver by using a transition detector followed by a PLL. The PPM word clock was recovered by using a second PLL whose input was derived from the presence of back-to-back PPM pulses contained in the received random PPM pulse sequences. The system achieved a bit error rate of 0.000001 at less than 50 detected signal photons/information bit. The receiver was capable of acquiring and maintaining slot and word synchronization for received signal levels greater than 20 photons/information bit, at which the receiver bit error rate was about 0.01.

Sun, Xiaoli↗

NASA NTRS1982

Using the NAVSTAR Global Positioning System as a global timing system

The application of NAVSTAR GPS to the problems of PTTI dissemination is discussed. A short review of the GPS concept lead to a detailed description of the implementation of time transfer through NAVSTAR GPS. Time was followed from the U.S. Naval Observatory (USNO) through the ground control, satellite, and receiving segments of GPS to the user's clock system. The three options by which a user's system can receive from the GPS receivers, currently under development by the DOD, are defined in detail. The electrical/digital/mechanical interface parameters along with suggested methods for their use are outlined for each option. A detailed error model is also presented for the traceability of UTC (GPS) to UTC (USNO). Real time synchronization between stationary users on the time continent can be controlled to within a few nanoseconds, and absolute post processed time offset with UTC (USNO) measured within 25 nanoseconds or better. A discussion of some of the potential work around techniques and their applications are included.

Kovach, K. L.↗

NASA NTRS2013

DESDynI Quad First Stage Processor - A Four Channel Digitizer and Digital Beam Forming Processor

The proposed Deformation, Eco-Systems, and Dynamics of Ice Radar (DESDynI-R) L-band SAR instrument employs multiple digital channels to optimize resolution while keeping a large swath on a single pass. High-speed digitization with very fine synchronization and digital beam forming are necessary in order to facilitate this new technique. The Quad First Stage Processor (qFSP) was developed to achieve both the processing performance as well as the digitizing fidelity in order to accomplish this sweeping SAR technique. The qFSP utilizes high precision and high-speed analog to digital converters (ADCs), each with a finely adjustable clock distribution network to digitize the channels at the fidelity necessary to allow for digital beam forming. The Xilinx produced FX130T Virtex 5 part handles the processing to digitally calibrate each channel as well as filter and beam form the receive signals. Demonstrating the digital processing required for digital beam forming and digital calibration is instrumental to the viability of the proposed DESDynI instrument. The qFSP development brings this implementation to Technology Readiness Level (TRL) 6. This paper will detail the design and development of the prototype qFSP as well as the preliminary results from hardware tests.

Chuang, Chung-Lun↗

NASA NTRS1995

A novel photonic oscillator

We report a novel oscillator for photonic RF systems. This oscillator is capable of generating high-frequency signals up to 70 GHz in both electrical and optical domains and is a special voltage-controlled oscillator with an optical output port. It can be used to make a phase-locked loop (PLL) and perform all functions that a PLL is capable of for photonic systems. It can be synchronized to a reference source by means of optical injection locking, electrical injection locking, and PLL. It can also be self-phase locked and self-injection locked to generate a high-stability photonic RF reference. Its applications include high-frequency reference regeneration and distribution, high-gain frequency multiplication, comb-frequecy and square-wave generation, carrier recovery, and clock recovery. We anticipate that such photonic voltage-controlled oscillators (VCOs) will be as important to photonic RF systems as electrical VCOs are to electrical RF systems.

Yao, X. S.↗

NASA NTRS1992

Formal Techniques for Synchronized Fault-Tolerant Systems

We present the formal verification of synchronizing aspects of the Reliable Computing Platform (RCP), a fault-tolerant computing system for digital flight control applications. The RCP uses NMR-style redundancy to mask faults and internal majority voting to purge the effects of transient faults. The system design has been formally specified and verified using the EHDM verification system. Our formalization is based on an extended state machine model incorporating snapshots of local processors clocks.

DiVito, Ben L.↗

NASA NTRS1983

Redundant asynchronous microprocessor system for fault tolerant flight control and navigation

Unlike their synchronized counterparts, redundant channels in an asynchronous flight system can, under no-fault conditions, exhibit cross-channel data disparities. Sources of these errors are examined in terms of the general, individual functions of the flight control and navigation application in the asynchronous digital environment. The effects of asynchronism on trajectory programmers, dynamic control algorithms and data reconstruction processes are examined in terms of data skews, data latencies, and clock rate uncertainties. An example is presented in which time corrections are applied to reduce the data disparities. Practical limitations of the approach of the example are discussed.

Dunn, W. R.↗

NASA NTRS1992

CCD data acquisition systems at Lick and Keck Observatories

This paper will describe and compare two distinct but related CCD data acquisition systems (DAS) currently under development at Lick and Keck Observatories. Although these two systems have a number of major architectural differences, they share a considerable amount of common hardware and software. Both of these new systems build on a large body of proven software that is the foundation of the existing CCD DAS currently in use at Lick Observatory. Both will provide support for reading up to four on-chip amplifiers per CCD and/or reading out mosaics of CCD chips. In addition, they will provide the capability for interactive, real-time adjustment of CCD waveforms for engineering purposes. Each of these two systems is composed of three major subsystems: (1) an instrument computer and its software; (2) a data capture computer and its software; and (3) a CCD/dewar controller and its software. The instrument computer is a Unix workstation, and the functions it provides include user interfaces, the interactive real-time display of CCD images, and the recording of image and FITS header data to disk and/or tape. The data capture computer is responsible for the packaging and high-speed transfer of the CCD pixel data stream into a bulk RAM, and the subsequent transfer of this data to the instrument computer. The CCD/dewar controller generates the waveforms for clocking the CCD, digitizes the pixel data, and transmits it via high-speed link to the data capture computer. It is also responsible for monitoring and controlling the dewar temperature and cryogen levels. Given the number of different types of processors and high-speed data links employed in both systems, a major emphasis of this paper will be on the various forms of interprocessor communications utilized for data transfer and distributed process synchronization.

Kibrick, R. I.↗

NASA NTRS1994

Time synchronized video systems

The idea of synchronizing multiple video recordings to some type of 'range' time has been tried to varying degrees of success in the past. Combining this requirement with existing time code standards (SMPTE) and the new innovations in desktop multimedia however, have afforded an opportunity to increase the flexibility and usefulness of such efforts without adding costs over the traditional data recording and reduction systems. The concept described can use IRIG, GPS or a battery backed internal clock as the master time source. By converting that time source to Vertical Interval Time Code or Longitudinal Time Code, both in accordance with the SMPTE standards, the user will obtain a tape that contains machine/computer readable time code suitable for use with editing equipment that is available off-the-shelf. Accuracy on playback is then determined by the playback system chosen by the user. Accuracies of +/- 2 frames are common among inexpensive systems and complete frame accuracy is more a matter of the users' budget than the capability of the recording system.

Burnett, Ron↗

NASA NTRS1988

Programmable Pulser

User controls number of clock pulses to prevent burnout. New digital programmable pulser circuit in three formats; freely running, counted, and single pulse. Operates at frequencies up to 5 MHz, with no special consideration given to layout of components or to terminations. Pulser based on sequential circuit with four states and binary counter with appropriate decoding logic. Number of programmable pulses increased beyond 127 by addition of another counter and decoding logic. For very large pulse counts and/or very high frequencies, use synchronous counters to avoid errors caused by propagation delays. Invaluable tool for initial verification or diagnosis of digital or digitally controlled circuity.

Baumann, Eric↗