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At least 379 records · Page 21
All sourcesNASA NTRSDOE OSTI
NASA NTRS1995

Prototype development and test results of a continuous ambient air monitoring system for hydrazine at the 10 ppb level

A Hydrazine Vapor Area Monitor (HVAM) system is currently being field tested as a detector for the presence of hydrazine in ambient air. The MDA/Polymetron Hydrazine Analyzer has been incorporated within the HVAM system as the core detector. This analyzer is a three-electrode liquid analyzer typically used in boiler feed water applications. The HVAM system incorporates a dual-phase sample collection/transport method which simultaneously pulls ambient air samples containing hydrazine and a very dilute sulfuric acid solution (0.0001 M) down a length of 1/4 inch outside diameter (OD) tubing from a remote site to the analyzer. The hydrazine-laden dilute acid stream is separated from the air and the pH is adjusted by addition of a dilute caustic solution to a pH greater than 10.2 prior to analysis. Both the dilute acid and caustic used by the HVAM are continuously generated during system operation on an "as needed" basis by mixing a metered amount of concentrated acid/base with dilution water. All of the waste water generated by the analyzer is purified for reuse by Barnstead ion-exchange cartridges so that the entire system minimizes the generation of waste materials. The pumping of all liquid streams and mixing of the caustic solution and dilution water with the incoming sample are done by a single pump motor fitted with the appropriate mix of peristaltic pump heads. The signal to noise (S/N) ratio of the analyzer has been enhanced by adding a stirrer in the MDA liquid cell to provide mixing normally generated by the high liquid flow rate designed by the manufacturer. An onboard microprocessor continuously monitors liquid levels, sample vacuum, and liquid leak sensors, as well as handles communications and other system functions (such as shut down should system malfunctions or errors occur). The overall system response of the HVAM can be automatically checked at regular intervals by measuring the analyzer response to a metered amount of calibration standard injected into the dilute acid stream. The HVAM system provides two measurement ranges (threshold limit value (TLV): 10 to 1000 parts per billion (ppb)/LEAK: 100 ppb to 10 parts per million (ppm)). The LEAK range is created by dilution of the sulfuric acid/hydrazine liquid sample with pure water. This dual range capability permits the analyzer to quantify ambient air samples whose hydrazine concentrations range from 10 ppb to as high as 10 ppm. The laboratory and field prototypes have demonstrated total system response times on the order of 10 to 12 minutes for samples ranging from 10 to 900 ppb in the lLV mode and is greater than 2 minutes for samples ranging from 100 to 1300 ppb in the LEAK mode. Service intervals of over 3 months have been demonstrated for continuous 24 hour/day, 7 day/week usage. The HVAM is made up of a purged cabinet that contains power supplies, RS422 signal transmission capabilities, a UPS, an on-site warning system, and a Line Replaceable Unit (LRU). The LRU includes all of the liquid flow system, the analyzer, the control/data system microprocessor and assorted flow and liquid-level sensors. The LRU is mounted on a track slide system so it can be serviced inplace or totally removed and quickly exchanged with another calibrated unit, thus minimizing analyzer downtime. Once an LRU is removed from an analyzer enclosure, it can be brought to a laboratory facility for complete calibration and periodic maintenance.

Meneghelli, Barry↗
NASA NTRS1996

Design and implementation of scalable tape archiver

In order to reduce costs, computer manufacturers try to use commodity parts as much as possible. Mainframes using proprietary processors are being replaced by high performance RISC microprocessor-based workstations, which are further being replaced by the commodity microprocessor used in personal computers. Highly reliable disks for mainframes are also being replaced by disk arrays, which are complexes of disk drives. In this paper we try to clarify the feasibility of a large scale tertiary storage system composed of 8-mm tape archivers utilizing robotics. In the near future, the 8-mm tape archiver will be widely used and become a commodity part, since recent rapid growth of multimedia applications requires much larger storage than disk drives can provide. We designed a scalable tape archiver which connects as many 8-mm tape archivers (element archivers) as possible. In the scalable archiver, robotics can exchange a cassette tape between two adjacent element archivers mechanically. Thus, we can build a large scalable archiver inexpensively. In addition, a sophisticated migration mechanism distributes frequently accessed tapes (hot tapes) evenly among all of the element archivers, which improves the throughput considerably. Even with the failures of some tape drives, the system dynamically redistributes hot tapes to the other element archivers which have live tape drives. Several kinds of specially tailored huge archivers are on the market, however, the 8-mm tape scalable archiver could replace them. To maintain high performance in spite of high access locality when a large number of archivers are attached to the scalable archiver, it is necessary to scatter frequently accessed cassettes among the element archivers and to use the tape drives efficiently. For this purpose, we introduce two cassette migration algorithms, foreground migration and background migration. Background migration transfers cassettes between element archivers to redistribute frequently accessed cassettes, thus balancing the load of each archiver. Background migration occurs the robotics are idle. Both migration algorithms are based on access frequency and space utility of each element archiver. To normalize these parameters according to the number of drives in each element archiver, it is possible to maintain high performance even if some tape drives fail. We found that the foreground migration is efficient at reducing access response time. Beside the foreground migration, the background migration makes it possible to track the transition of spatial access locality quickly.

Nemoto, Toshihiro↗
NASA NTRS1997

Automated Liquid-Level Control of a Nutrient Reservoir for a Hydroponic System

A microprocessor-based system for control of the liquid level of a nutrient reservoir for a plant hydroponic growing system has been developed. The system uses an ultrasonic transducer to sense the liquid level or height. A National Instruments' Multifunction Analog and Digital Input/Output PC Kit includes NI-DAQ DOS/Windows driver software for an IBM 486 personal computer. A Labview Full Development system for Windows is the graphical programming system being used. The system allows liquid level control to within 0.1 cm for all levels tried between 8 and 36 cm in the hydroponic system application. The detailed algorithms have been developed and a fully automated microprocessor based nutrient replenishment system has been described for this hydroponic system.

Smith, Boris↗
NASA NTRS1999

Formal Verification of the AAMP-FV Microcode

This report describes the experiences of Collins Avionics & Communications and SRI International in formally specifying and verifying the microcode in a Rockwell proprietary microprocessor, the AAMP-FV, using the PVS verification system. This project built extensively on earlier experiences using PVS to verify the microcode in the AAMP5, a complex, pipelined microprocessor designed for use in avionics displays and global positioning systems. While the AAMP5 experiment demonstrated the technical feasibility of formal verification of microcode, the steep learning curve encountered left unanswered the question of whether it could be performed at reasonable cost. The AAMP-FV project was conducted to determine whether the experience gained on the AAMP5 project could be used to make formal verification of microcode cost effective for safety-critical and high volume devices.

Miller, Steven P.↗
NASA NTRS1998

An Adaptable Power System with Software Control Algorithm

A low cost, flexible and modular spacecraft power system design was developed in response to a call for an architecture that could accommodate multiple missions in the small to medium load range. Three upcoming satellites will use this design, with one launch date in 1999 and two in the year 2000. The design consists of modular hardware that can be scaled up or down, without additional cost, to suit missions in the 200 to 600 Watt orbital average load range. The design will be applied to satellite orbits that are circular, polar elliptical and a libration point orbit. Mission unique adaptations are accomplished in software and firmware. In designing this advanced, adaptable power system, the major goals were reduction in weight volume and cost. This power system design represents reductions in weight of 78 percent, volume of 86 percent and cost of 65 percent from previous comparable systems. The efforts to miniaturize the electronics without sacrificing performance has created streamlined power electronics with control functions residing in the system microprocessor. The power system design can handle any battery size up to 50 Amp-hour and any battery technology. The three current implementations will use both nickel cadmium and nickel hydrogen batteries ranging in size from 21 to 50 Amp-hours. Multiple batteries can be used by adding another battery module. Any solar cell technology can be used and various array layouts can be incorporated with no change in Power System Electronics (PSE) hardware. Other features of the design are the standardized interfaces between cards and subsystems and immunity to radiation effects up to 30 krad Total Ionizing Dose (TID) and 35 Mev/cm(exp 2)-kg for Single Event Effects (SEE). The control algorithm for the power system resides in a radiation-hardened microprocessor. A table driven software design allows for flexibility in mission specific requirements. By storing critical power system constants in memory, modifying the system code for other programs is simple. These constants can be altered also by ground command, or in response to an anomolous event. All critical power system functions have backup hardware functions to prevent a software or computer glitch from propagating. A number of battery charge control schemes can be implemented by selecting the proper control terms in the code. The architecture allows the design engineer to tune the system response to various system components and anticipated load profiles without costly alterations. A design trade was made with the size, weight and power dissipation of the electronics versus the performance of the power bus to load variations. Linear, fine control is maintained with a streamlined electronics design. This paper describes the hardware design as well as the software control algorithm. The challenges of closing the system control loop digitally is discussed. Control loop margin and power system performance is presented. Lab measurements are shown and compared to the system response of a hardware model running actual flight software.

Castell, Karen↗
NASA NTRS1997

A Report of Bethune-Cookman College NASA JOVE Projects

This document is the final report for the Joint Venture (JOVE) in Space Sciences, and describes the tasks, performed with the support of the contract. These tasks include work in: (1) interfacing microprocessor systems to high performance parallel interface chips, SCSI drive and memory, needed for the implementation of a Space Optical Data Recorder; (2) designing a digital interface architecture for a microprocessor controlled sensors monitoring unit for a NASA Jitter Attenuation and Dynamics Experiment (JADE) project; (3) developing an enhanced back-propagation training algorithm; (4) studying the effect of simulated spaceflight on Aortic Contractility; (5) developing a course in astronomy; and (6) improving internet access by running cables, and installing hubs in various places on the campus; and (7) researching the characteristics of Nd:YALO laser resonator.

Agba, Lawrence C.↗
NASA NTRS2001

Spaceborne Global Positioning System for Spacecraft

The spaceborne Global Positioning System receiver provides navigational solutions and is designed for use in low Earth orbit. The spaceborne GPS receiver can determine the orbital position of a spacecraft using any of the satellites wi thin the GPS constellation. It is a multiple processor system incorporating redundancy by using a microcontroller to handle the closure of tracking loops for acquired GPS satellites, while a separate microprocessor computes the spacecraft navigational solution and handles other tasks within the receiver. 'Me spaceborne GPS receiver can use either microcontroller or the microprocessor to close the satellite tracking loops. The use of microcontroller provides better tracking performance of acquired GPS satellites. The spaceborne GPS receiver utilizes up to seven separate GPS boards, with each board including its own set of correlators, down-converters and front-end components. The spaceborne GPS receiver also includes telemetry and time-marking circuitry. The spaceborne GPS receiver communicates with other spacecraft systems through a variety of interfaces and can be software-configured to support several different mission profiles.

Lamar F Dougherty↗
NASA NTRS1995

RISC Processors and High Performance Computing

In this tutorial, we will discuss top five current RISC microprocessors: The IBM Power2, which is used in the IBM RS6000/590 workstation and in the IBM SP2 parallel supercomputer, the DEC Alpha, which is in the DEC Alpha workstation and in the Cray T3D; the MIPS R8000, which is used in the SGI Power Challenge; the HP PA-RISC 7100, which is used in the HP 700 series workstations and in the Convex Exemplar; and the Cray proprietary processor, which is used in the new Cray J916. The architecture of these microprocessors will first be presented. The effective performance of these processors will then be compared, both by citing standard benchmarks and also in the context of implementing a real applications. In the process, different programming models such as data parallel (CM Fortran and HPF) and message passing (PVM and MPI) will be introduced and compared. The latest NAS Parallel Benchmark (NPB) absolute performance and performance per dollar figures will be presented. The next generation of the NP13 will also be described. The tutorial will conclude with a discussion of general trends in the field of high performance computing, including likely future developments in hardware and software technology, and the relative roles of vector supercomputers tightly coupled parallel computers, and clusters of workstations. This tutorial will provide a unique cross-machine comparison not available elsewhere.

Saini, Subhash↗
NASA NTRS1995

High Performance Parallel Computational Nanotechnology

At a recent press conference, NASA Administrator Dan Goldin encouraged NASA Ames Research Center to take a lead role in promoting research and development of advanced, high-performance computer technology, including nanotechnology. Manufacturers of leading-edge microprocessors currently perform large-scale simulations in the design and verification of semiconductor devices and microprocessors. Recently, the need for this intensive simulation and modeling analysis has greatly increased, due in part to the ever-increasing complexity of these devices, as well as the lessons of experiences such as the Pentium fiasco. Simulation, modeling, testing, and validation will be even more important for designing molecular computers because of the complex specification of millions of atoms, thousands of assembly steps, as well as the simulation and modeling needed to ensure reliable, robust and efficient fabrication of the molecular devices. The software for this capacity does not exist today, but it can be extrapolated from the software currently used in molecular modeling for other applications: semi-empirical methods, ab initio methods, self-consistent field methods, Hartree-Fock methods, molecular mechanics; and simulation methods for diamondoid structures. In as much as it seems clear that the application of such methods in nanotechnology will require powerful, highly powerful systems, this talk will discuss techniques and issues for performing these types of computations on parallel systems. We will describe system design issues (memory, I/O, mass storage, operating system requirements, special user interface issues, interconnects, bandwidths, and programming languages) involved in parallel methods for scalable classical, semiclassical, quantum, molecular mechanics, and continuum models; molecular nanotechnology computer-aided designs (NanoCAD) techniques; visualization using virtual reality techniques of structural models and assembly sequences; software required to control mini robotic manipulators for positional control; scalable numerical algorithms for reliability, verifications and testability. There appears no fundamental obstacle to simulating molecular compilers and molecular computers on high performance parallel computers, just as the Boeing 777 was simulated on a computer before manufacturing it.

Saini, Subhash↗
NASA NTRS2003

Experimental Verification of Electric Drive Technologies Based on Artificial Intelligence Tools

A laboratory implementation of a fuzzy logic-tracking controller using a low cost Motorola MC68HC11E9 microprocessor is described in this report. The objective is to design the most optimal yet practical controller that can be implemented and marketed, and which gives respectable performance, even when the system loads, inertia and parameters are varying. A distinguishing feature of this work is the by-product goal of developing a marketable, simple, functional and low cost controller. Additionally, real-time nonlinearities are not ignored, and a mathematical model is not required. A number of components have been designed, built and tested individually, and in various combinations of hardware and software segments. These components have been integrated with a brushless motor to constitute the drive system. A microprocessor-based FLC is incorporated to provide robust speed and position control. Design objectives that are difficult to express mathematically can be easily incorporated in a fuzzy logic-based controller by linguistic information (in the form of fuzzy IF-THEN rules). The theory and design are tested in the laboratory using a hardware setup. Several test cases have been conducted to confirm the effectiveness of the proposed controller. The results indicate excellent tracking performance for both speed and position trajectories. For the purpose of comparison, a bang-bang controller has been tested. The fuzzy logic controller performs significantly better than the traditional bang-bang controller. The bang-bang controller has been shown to be relatively inaccurate and lacking in robustness. Description of the implementation hardware system is also given.

Rubaai, Ahmed↗
NASA NTRS2003

Field Programmable Gate Array for Implementation of Redundant Advanced Digital Feedback Control

The goal of this effort was to develop a digital motor controller using field programmable gate arrays (FPGAs). This is a more rugged approach than a conventional microprocessor digital controller. FPGAs typically have higher radiation (rad) tolerance than both the microprocessor and memory required for a conventional digital controller. Furthermore, FPGAs can typically operate at higher speeds. (While speed is usually not an issue for motor controllers, it can be for other system controllers.) Other than motor power, only a 3.3-V digital power supply was used in the controller; no analog bias supplies were used. Since most of the circuit was implemented in the FPGA, no additional parts were needed other than the power transistors to drive the motor. The benefits that FPGAs provide over conventional designs-lower power and fewer parts-allow for smaller packaging and reduced weight and cost.

King, K. D.↗
NASA NTRS2004

Single Event Effects in Highly Scaled Devices for Space Applications

This paper discusses single-event upset (SEU) in memories and microprocessors that are the "drivers" of highly scaled commercial integrated circuits. Despite the decrease in critical charge that occurs for highly scaled CMOS devices, recent test data has shown that SEU rates are actually somewhat lower for scaled devices compared to older devices with larger feature size. Hard errors, which are increasingly important for memories, are discussed along with conventional soft errors. Functional errors in memories and microprocessors are particularly significant, and tend to dominate the response of highly scaled devices from an application standpoint. Predictions for future devices are made using the Semiconductor Industry Roadmap along with recent modeling and radiation test results.

microelectronics↗
NASA NTRS1988

Programmable control means for providing safe and controlled medication infusion

An implantable programmable infusion pump (IPIP) is disclosed and generally includes: a fluid reservoir filled with selected medication; a pump for causing a precise volumetric dosage of medication to be withdrawn from the reservoir and delivered to the appropriate site within the body; and, a control means for actuating the pump in a safe and programmable manner. The control means includes a microprocessor, a permanent memory containing a series of fixed software instructions, and a memory for storing prescription schedules, dosage limits and other data. The microprocessor actuates the pump in accordance with programmable prescription parameters and dosage limits stored in the memory. A communication link allows the control means to be remotely programmed. The control means incorporates a running integral dosage limit and other safety features which prevent an inadvertent or intentional medication overdose. The control means also monitors the pump and fluid handling system and provides an alert if any improper or potentially unsafe operation is detected.

Fischell, Robert E.↗
NASA NTRS1985

Portable instant display and analysis reflectance spectrometer

A portable analysis spectrometer (10) for field mineral identification is coupled to a microprocessor (11) and memory (12) through a bus (13) and A/D converter (14) to display (16) a spectrum of reflected radiation in a band selected by an adjustable band spectrometer (20) and filter (23). A detector array (21) provides output signals at spaced frequencies within the selected spectrometer band which are simultaneously converted to digital form for display. The spectrum displayed is compared with a collection of spectra for known minerals. That collection is stored in memory and selectively displayed with the measured spectrum, or stored in a separate portfolio. In either case, visual comparison is made. Alternatively, the microprocessor may use an algorithm to make the comparisons in search for the best match of the measured spectrum with one of the stored spectra to identify the mineral in the target area.

Goetz, Alexander F. H.↗
NASA NTRS1997

Portable light source unit for simulating fires having an adjustable aperture

A portable, hand held light source unit is employed to check operation of fire detectors, such as hydrogen fire detectors. The unit emits radiation in a narrow band of wavelengths which are generated by the type of fire to be tested, but not by other light sources such as the sun or incandescent lamps. The unit can test fire detectors at different distances, and of different sensitivities. The intensity of the radiation emitted by the unit is adjustable for this purpose by means of a rotatable disk having a plurality of different sized apertures for selective placement between the light source and an output lens. The disk can also be rotated to a calibration position which causes a microprocessor circuit in the unit to initiate a calibration procedure. During this procedure, the lamp intensity is measured by a photodetector contained within the unit, and the microprocessor adjusts the lamp current to insure that its intensity remains within a preset range of values. A green and a red LED are mounted on the unit which indicate to an operator whether the calibration is successful, as well as the condition of the unit's battery power supply.

Youngquist, Robert C.↗
NASA NTRS2009

Lithium Ion Battery (LIB) Charger: Spacesuit Battery Charger Design with 2-Fault Tolerance to Catastrophic Hazards

Charger design that is 2-fault tolerant to catastrophic has been achieved for the Spacesuit Li-ion Battery with key features. Power supply control circuit and 2 microprocessors independently control against overcharge. 3 microprocessor control against undercharge (false positive: Go for EVA) conditions. 2 independent channels provide functional redundancy. Capable of charge balancing cell banks in series. Cell manufacturing and performance uniformity is excellent with both designs. Once a few outliers are removed, LV cells are slightly more uniform than MoliJ cells. If cell balance feature of charger is ever invoked, it will be an indication of a significant degradation issue, not a nominal condition.

Darcy, Eric↗
NASA NTRS2009

Airborne Antenna System for Minimum-Cycle-Slip GPS Reception

A system that includes a Global Positioning System (GPS) antenna and associated apparatus for keeping the antenna aimed upward has been developed for use aboard a remote-sensing-survey airplane. The purpose served by the system is to enable minimum- cycle-slip reception of GPS signals used in precise computation of the trajectory of the airplane, without having to restrict the airplane to maneuvers that increase the flight time needed to perform a survey. Cycle slip signifies loss of continuous track of the phase of a signal. Minimum-cycle-slip reception is desirable because maintaining constant track of the phase of the carrier signal from each available GPS satellite is necessary for surveying to centimeter or subcentimeter precision. Even a loss of signal for as short a time as a nanosecond can cause cycle slip. Cycle slips degrade the quality and precision of survey data acquired during a flight. The two principal causes of cycle slip are weakness of signals and multipath propagation. Heretofore, it has been standard practice to mount a GPS antenna rigidly on top of an airplane, and the radiation pattern of the antenna is typically hemispherical, so that all GPS satellites above the horizon are viewed by the antenna during level flight. When the airplane must be banked for a turn or other maneuver, the reception hemisphere becomes correspondingly tilted; hence, the antenna no longer views satellites that may still be above the Earth horizon but are now below the equatorial plane of the tilted reception hemisphere. Moreover, part of the reception hemisphere (typically, on the inside of a turn) becomes pointed toward ground, with a consequent increase in received noise and, therefore, degradation of GPS measurements. To minimize the likelihood of loss of signal and cycle slip, bank angles of remote-sensing survey airplanes have generally been limited to 10 or less, resulting in skidding or slipping uncoordinated turns. An airplane must be banked in order to make a coordinated turn. For small-radius, short-time coordinated turns, it is necessary to employ banks as steep as 45 , and turns involving such banks are times and for confining airplanes as closely as possible to areas to be surveyed. The idea underlying the design is that if the antenna can be kept properly aimed, then the incidence of cycle slips caused by loss or weakness of signals can be minimized. The system includes an articulating GPS antenna and associated electronic circuitry mounted under a radome atop an airplane. The electronic circuitry includes a microprocessor-based interface-circuit-and-data-translation module. The system receives data on the current attitude of the airplane from the inertial navigation system of the airplane. The microprocessor decodes the attitude data and uses them to compute commands for the GPS-antenna-articulating mechanism to tilt the antenna, relative to the airplane, in opposition to the roll or bank of the airplane to keep the antenna pointed toward the zenith. The system was tested aboard the hurricane- hunting airplane of the National Oceanic and Atmospheric Administration (NOAA) [see figure] during an 11-hour flight to observe the landfall of Hurricane Bret in late summer of 1999. No bank-angle restrictions were imposed during the flight. Post-flight analysis of the GPS trajectory data revealed that no cycle slip had occurred.considered normal maneuvers. These steep banks are highly desirable for minimizing flight

Wright, C. Wayne↗
NASA NTRS2009

Radiation-hardened fast acquisition/weak signal tracking system and method

A global positioning system (GPS) receiver and method of acquiring and tracking GPS signals comprises an antenna adapted to receive GPS signals; an analog radio frequency device operatively connected to the antenna and adapted to convert the GPS signals from an analog format to a digital format; a plurality of GPS signal tracking correlators operatively connected to the analog RF device; a GPS signal acquisition component operatively connected to the analog RF device and the plurality of GPS signal tracking correlators, wherein the GPS signal acquisition component is adapted to calculate a maximum vector on a databit correlation grid; and a microprocessor operatively connected to the plurality of GPS signal tracking correlators and the GPS signal acquisition component, wherein the microprocessor is adapted to compare the maximum vector with a predetermined correlation threshold to allow the GPS signal to be fully acquired and tracked.

Winternitz, Luke↗