Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “Circuits”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 379 records · Page 21
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Developing an Empirical Model for Estimating the Probability of Electrical Short Circuits from Tin Whiskers

To comply with lead-free legislation, many manufacturers have converted from tin-lead to pure tin finishes of electronic components. However, pure tin finishes have a greater propensity to grow tin whiskers than tin-lead finishes. Since tin whiskers present an electrical short circuit hazard in electronic components, simulations have been developed to quantify the risk of said short circuits occurring. Existing risk simulations make the assumption that when a free tin whisker has bridged two adjacent exposed electrical conductors, the result is an electrical short circuit. This conservative assumption is made because shorting is a random event that had an unknown probability associated with it. Note however that due to contact resistance electrical shorts may not occur at lower voltage levels. In our first article we developed an empirical probability model for tin whisker shorting. In this paper, we develop a more comprehensive empirical model using a refined experiment with a larger sample size, in which we studied the effect of varying voltage on the breakdown of the contact resistance which leads to a short circuit. From the resulting data we estimated the probability distribution of an electrical short, as a function of voltage. In addition, the unexpected polycrystalline structure seen in the focused ion beam (FIB) cross section in the first experiment was confirmed in this experiment using transmission electron microscopy (TEM). The FIB was also used to cross section two card guides to facilitate the measurement of the grain size of each card guide's tin plating to determine its finish.

Courey, Karim J.↗
NASA NTRS2013

Fast, High-Precision Readout Circuit for Detector Arrays

The GEO-CAPE mission described in NASA's Earth Science and Applications Decadal Survey requires high spatial, temporal, and spectral resolution measurements to monitor and characterize the rapidly changing chemistry of the troposphere over North and South Americas. High-frame-rate focal plane arrays (FPAs) with many pixels are needed to enable such measurements. A high-throughput digital detector readout integrated circuit (ROIC) that meets the GEO-CAPE FPA needs has been developed, fabricated, and tested. The ROIC is based on an innovative charge integrating, fast, high-precision analog-to-digital circuit that is built into each pixel. The 128×128-pixel ROIC digitizes all 16,384 pixels simultaneously at frame rates up to 16 kHz to provide a completely digital output on a single integrated circuit at an unprecedented rate of 262 million pixels per second. The approach eliminates the need for off focal plane electronics, greatly reducing volume, mass, and power compared to conventional FPA implementations. A focal plane based on this ROIC will require less than 2 W of power on a 1×1-cm integrated circuit. The ROIC is fabricated of silicon using CMOS technology. It is designed to be indium bump bonded to a variety of detector materials including silicon PIN diodes, indium antimonide (InSb), indium gallium arsenide (In- GaAs), and mercury cadmium telluride (HgCdTe) detector arrays to provide coverage over a broad spectral range in the infrared, visible, and ultraviolet spectral ranges.

Rider, David M.↗
NASA NTRS2014

5.8kV SiC PiN Diode for Switching of High-Efficiency Inductive Pulsed Plasma Thruster Circuits

Inductive Pulsed Plasma Thruster (IPPT) pulse circuits, such as those needed to operate the Pulsed Inductive Thruster (PIT), are required to quickly switch capacitor banks operating at a period of μs while conducting current at levels on the order of at least 10 kA. [1,2] For all iterations of the PIT to date, spark gaps have been used to discharge the capacitor bank through an inductive coil. Recent availability of fast, high‐power solid state switching devices makes it possible to consider the use of semiconductor switches in modern IPPTs. In addition, novel pre‐ionization schemes have led to a reduction in discharge energy per pulse for electric thrusters of this type, relaxing the switching requirements for these thrusters. [3,4] Solid state switches offer the advantage of greater controllability and reliability, as well as decreased drive circuit dimensions and mass relative to spark gap switches. The use of solid state devices such as Integrated Gate Bipolar Transistors (IGBTs), Gate Turn‐off Thyristors (GTOs) and Silicon‐Controlled Rectifiers (SCRs) often involves the use of power diodes. These semiconductor devices may be connected antiparallel to the switch for protection from reverse current, or used to reduce power loss in a circuit by clamping off current ringing. In each case, higher circuit efficiency may be achieved by using a diode that is able to transition, or 'switch,' from the forward conducting state ('on' state) to the reverse blocking state ('off' state) in the shortest amount of time, thereby minimizing current ringing and switching losses. Silicon Carbide (SiC) PiN diodes offer significant advantages to conventional fast‐switching Silicon (Si) diodes for high power and fast switching applications. A wider band gap results in a breakdown voltage 10 times that of Si, so that a SiC device may have a thinner drift region for a given blocking voltage. [5] This leads to smaller, lighter devices for high voltage applications, as well as reduced forward conduction losses, faster reverse recovery time (faster turn‐off), and lower‐magnitude reverse recovery current. In addition, SiC devices have lower leakage current as compared to their Si counterparts, and a high thermal conductivity, potentially allowing the former to operate at higher temperatures with a smaller, lighter heatsink (or no heatsink at all).

Toftul, Alexandra↗
NASA NTRS2016

Sampling and Control Circuit Board for an Inertial Measurement Unit

A circuit board that serves as a control and sampling interface to an inertial measurement unit ("IMU") is provided. The circuit board is also configured to interface with a local oscillator and an external trigger pulse. The circuit board is further configured to receive the external trigger pulse from an external source that time aligns the local oscillator and initiates sampling of the inertial measurement device for data at precise time intervals based on pulses from the local oscillator. The sampled data may be synchronized by the circuit board with other sensors of a navigation system via the trigger pulse.

Chelmins, David T↗
NASA NTRS2016

Vibration Damping Circuit Card Assembly

A vibration damping circuit card assembly includes a populated circuit card having a mass M. A closed metal container is coupled to a surface of the populated circuit card at approximately a geometric center of the populated circuit card. Tungsten balls fill approximately 90% of the metal container with a collective mass of the tungsten balls being approximately (0.07) M.

Hunt, Ronald Allen↗
NASA NTRS2017

Temporal Planning for Compilation of Quantum Approximate Optimization Algorithm Circuits

We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus our initial experiments on Quantum Approximate Optimization Algorithm (QAOA) circuits that have few ordering constraints and allow highly parallel plans. We report on experiments using several temporal planners to compile circuits of various sizes to a realistic hardware. This early empirical evaluation suggests that temporal planning is a viable approach to quantum circuit compilation.

planning↗
NASA NTRS2018

Building Reliable Printed Circuit Boards - the Lessons Learned

"Printed circuit boards (PCBs) are the baseline for electronics manufacturing upon which electronic components are mounted and formed into electronic systems. PCBs are used in a variety of electronic circuits from simple one-transistor amplifiers to large super computers. A PCB serves three main functions: 1) it provides the necessary mechanical support for the components in the circuit 2) it provides the necessary electrical interconnections, and 3) it bears some form of legend which identifies the components it carries. The failure modes on the PCBs can be categorized in a hierarchical structure, in which the mechanisms and causes are site or location dependant. This one day workshop will discuss a variety of failure mechanisms that effect the functionality of PCBs. These mechanisms can be related to how PCB materials are selected, PCBs are designed, manufactured, tested and used in the field conditions. The workshop will begin with an overview of PCB manufacturing, materials and processes. With the help of examples and case studies, a wide range of failure mechanisms will be discussed, case studies are focused on digital circuits, however some failures in analog, double sided boards are also presented. The workshop then provides the guideline for selection of methodologies for identifying potential failure mechanisms based on the failure history and how a systematic root cause failure analysis of the PCB can result in prevention of future issues."

Sood, Bhanu↗
NASA NTRS2009

Understanding how molecular hydrogen impacts the total dose and dose rate response of linear bipolar circuits

Recent Enhanced Low Dose Rate Sensitivity (ELDRS) investigations carried out by RLP Research, Arizona State University (ASU) and Jet Propulsion Laboratory (JPL) have shown significant differences in the degradation of bipolar micro-circuits with total dose in the presence of molecular hydrogen (H2) in packages. This has a significant impact on radiation hardness assurance and opens up opportunities to improve device performance. The general objectives of this program are to: 1. Determine the extent to which hydrogen contamination affects the total dose and dose rate response of linear bipolar circuits; 2. Develop a model that will enable the prediction of high dose rate (HDR) and low dose rate (LDR) response asymptotes and transition dose rates as a function of total dose, temperature, pressurized hydrogen, defect precursors, and other process dependent variables; 3. Explore the possibility of an accelerated hardness assurance method and possible hardening approaches; and 4. Extend the work to other technologies that have total dose response affected by hydrogen contamination.In this document, we xperimentally demonstrate with test transistors and circuits that hydrogen is correlated with ELDRS in bipolar linear circuits. We show that the amount of hydrogen determines: 1) the total dose response versus dose rate and 2) the transition dose rates between the high and low dose rate responses. The experimental results are supported with a steady state drift/diffusion analytical model as well as modeling calculations using COMSOL Multiphysics.

Pease, Ron↗
NASA NTRSDate not supplied

Process Recipes for Additively Printed Copper Ink Flexible Circuits using Direct Write Methods

In this paper, the process-recipes and process-performance relationships for additive-printing of copper circuits using direct-write methods have been studied. The process has been implemented on the direct write platform. Interest in the use of additive printing methods for the manufacture of micro-circuits has grown immensely in recent times. Direct write methods have been shown to have the ability to create circuits in a limited manner. However, the process recipes and the effect of process parameters on the manufactured properties are not well understood. Copper ink is a good and cost-effective alternative to silver ink but its use has lagged owing to an increased propensity for oxidation. In this paper, photonic curing has been used to sinter copper ink to make the traces conductive. The method flashes high energy light that sinter metal particles instantaneously and the temperature of the substrate remains low. The effect of the different photonic sintering profiles on the mechanical and electrical properties of the printed traces has been studied in this paper.The print process parameters also play an important role in the line width and height that has been studied to print with the desired line profile for the end application. An LC filter circuit is been printed with SMD components been attached using an electrically conductive adhesive (ECA). The manufactured flexible LC filter is been tested for its frequency sweep to compare with the commercially available LC filer with the help of the Bode plot.

Process control↗
NASA NTRSDate not supplied

Surrogate Optimization for Quantum Circuits

Variational quantum Eigensolvers are touted as a near-term algorithm capable of impacting many applications. However, the potential has yet to be realized with few claims of quantum advantage and high resource estimates mainly due to the need for optimization in the presence of noise. Finding algorithms and methods to improve the convergence is essential to accelerate the capabilities of near-term hardware for VQE or more broad applications of hybrid methods in which optimization is required. To this goal we look to use modern approaches recently developed in circuit simulations and stochastic classical optimization that can be combined in a surrogate optimization approach to classical circuits. Using an approximate state vector simulator, we efficiently calculate an approximate Hessian, fed as an input for a detailed quantum circuit simulator. We demonstrate the capabilities of such an approach with and without sampling noise. We also show that this method outperforms Powell in the presence of quantum circuit shot noise by a factor of 2-4

quantum computing↗
DOE OSTI2019

Input-output processing on a remote integrated circuit chip

An electronic device includes a first integrated circuit chip including a processing functional block, and a second integrated circuit chip including an input-output (IO) functional block. The IO functional block performs one or more IO processing operations on behalf of the processing functional block in the first integrated circuit chip. The first integrated circuit chip lacks at least some elements of the IO functional block, so that the processing functional block is unable to perform corresponding IO operations without the IO functional block.

42 ENGINEERING↗
DOE OSTI2020

Discrete time analog front end circuit implemented in a receiver device

A device can comprise a peaked integrator circuit that generates an output signal from a continuous time signal based on a sub rate clock timing cycle. The device can further comprise a track and hold circuit coupled to the output of the peaked integrator that generates a held discrete time signal from the output of the peaked integrator based on a second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval. The device can further comprise an integrator circuit coupled to an output of the track and hold circuit that integrates the held discrete time signal, based on the second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval.

42 ENGINEERING↗
DOE OSTI2022

Smart dim fuse: electrical load flexibility controller using sub-circuit voltage modulation and load sensing

Improved control of electrical power consumption is provided with “Smart Dim Fuses” (SDF) which can alter their output voltage as provided to the load circuits they are connected to. SDF units can replace conventional circuit breakers in electrical panels. The voltage control capability provided by SDF units can lead to improved control of electrical power consumption, since many loads can smoothly operate at lower power consumption when the voltage they are driven with decreases. SDF units can comply with relevant safety requirements, such as uninterrupted neutral connections between electrical mains and load circuits. SDF units can also provide a current limiting function that can substitute for the protective action of conventional circuit breakers.

Goldin, Aaron↗
DOE OSTI2022

Offset-aligned three-dimensional integrated circuit

A method for manufacturing a three-dimensional integrated circuit includes attaching a first side of a first die to a first carrier wafer. The method includes preparing a second side of the first die to generate a prepared second side of the first die. The method includes attaching the prepared second side of the first die to a second carrier wafer. The method includes removing the first carrier wafer from the first side of the first die to form a transitional three-dimensional integrated circuit. The method includes attaching a third carrier wafer to a first side of the transitional three-dimensional integrated circuit. The method includes attaching a first side of the second die to a second side of the transitional three-dimensional integrated circuit.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Power Converter Circuit Design Automation using Parallel Monte Carlo Tree Search

The tidal waves of modern electronic/electrical devices have led to increasing demands for ubiquitous application-specific power converters. A conventional manual design procedure of such power converters is computation- and labor-intensive, which involves selecting and connecting component devices, tuning component-wise parameters and control schemes, and iteratively evaluating and optimizing the design. To automate and speed up this design process, we propose an automatic framework that designs custom power converters from design specifications using Monte Carlo Tree Search. Specifically, the framework embraces the upper-confidence-bound-tree (UCT), a variant of Monte Carlo Tree Search, to automate topology space exploration with circuit design specification-encoded reward signals. Moreover, our UCT-based approach can exploit small offline data via the specially designed default policy and can run in parallel to accelerate topology space exploration. Further, it utilizes a hybrid circuit evaluation strategy to substantially reduce design evaluation costs. Empirically, we demonstrated that our framework could generate energy-efficient circuit topologies for various target voltage conversion ratios. Compared to existing automatic topology optimization strategies, the proposed method is much more computationally efficient --- the sequential version can generate topologies with the same quality while being up to 67% faster. Here, the parallelization schemes can further achieve high speedups compared to the sequential version.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2022

Mode connectivity in the loss landscape of parameterized quantum circuits

Variational training of parameterized quantum circuits (PQCs) underpins many workflows employed on near-term noisy intermediate scale quantum (NISQ) devices. It is a hybrid quantum-classical approach that minimizes an associated cost function in order to train a parameterized ansatz. In this work we adapt the qualitative loss landscape characterization for neural networks introduced in Goodfellow et al. (2014); Li et al. (2017) and tests for connectivity used in Draxler et al. (2018) to study the loss landscape features in PQC training. We present results for PQCs trained on a simple regression task, using the bilayer circuit ansatz, which consists of alternating layers of parameterized rotation gates and entangling gates. Multiple circuits are trained with 3 different batch gradient optimizers: stochastic gradient descent, the quantum natural gradient, and Adam. We identify large features in the landscape that can lead to faster convergence in training workflows.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Comparison of quantum advantage experiments using random circuit sampling

Random circuit sampling, the task of sampling bit strings from a random unitary operator, has been implemented to demonstrate quantum advantage on the Sycamore quantum processor with 53 qubits and on the Zuchongzhi quantum processor with 56 and 61 qubits. Recently, it was claimed that classical computers using tensor network simulation could catch on to current noisy quantum processors for random circuit sampling. While the linear cross-entropy benchmark fidelity was used to certify all these claims, it may not capture statistical properties of outputs in detail. Here, we compare the bit strings sampled from classical computers using tensor network simulation by Pan et al. [F. Pan, K. Chen, and P. Zhang, Phys. Rev. Lett. 129, 090502 (2022)] and by Kalachev et al. [G. Kalachev, P. Panteleev, P. Zhou, and M.-H. Yung, arXiv:2112.15083] with the bit strings from the Sycamore quantum processor. It is shown that all of Kalachev et al.'s samples passed the NIST random number tests. The heat maps of bit strings show that Pan et al.'s and Kalachev et al.'s samples are quite different from the Sycamore or Zuchongzhi samples. The analysis with the Marchenko-Pastur distribution and the Wasssertein distances demonstrates that Kalachev et al.'s samples are statistically closer to the Sycamore samples than Pan et al.'s while the three datasets have similar values for the linear cross-entropy fidelity. In conclusion, our finding implies that further study is needed to certify or beat the claims of quantum advantage using random circuit sampling.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2025

Cost of emulating a small quantum annealing problem in the circuit model

Demonstrations of quantum advantage for certain sampling problems have generated considerable excitement for quantum computing and have further spurred the development of circuit-model quantum computers, which represent quantum programs as a sequence of quantum gates acting on a finite number of qubits. Amongst this excitement, analog quantum computation has become less prominent, with the expectation that circuit-model quantum computers will eventually be sufficient for emulating analog quantum computation and thus rendering analog quantum computation obsolete. In this work we explore the basic requirements for emulating a specific analog quantum computation in the circuit model: the preparation of a biased superposition of degenerate ground states of an Ising Hamiltonian using an adiabatic evolution. We show that the overhead of emulation is substantial even for this simple problem. This supports using analog quantum computation for solving time-dependent Hamiltonian dynamics in the short term and midterm, assuming analog errors can be made low enough and coherence times long enough to solve problems of practical interest.

Quantum algorithms & computation↗