DOE OSTI2011
Many next-generation physics experiments will be characterized by the collection of large quantities of data, taken in rapid succession, from which scientists will have to unravel the underlying physical processes. In most cases, large backgrounds will overwhelm the physics signal. Since the quantity of data that can be stored for later analysis is limited, real-time event selection is imperative to retain the interesting events while rejecting the background. Scaling of current technologies is unlikely to satisfy the scientific needs of future projects, so investments in transformational new technologies need to be made. For example, future particle physics experiments looking for rare processes will have to address the demanding challenges of fast pattern recognition in triggering as detector hit density becomes significantly higher due to the high luminosity required to produce the rare processes. In this proposal, we intend to develop hardware-based technology that significantly advances the state-of-the-art for fast pattern recognition within and outside HEP using the 3D vertical integration technology that has emerged recently in industry. The ultimate physics reach of the LHC experiments will crucially depend on the tracking trigger's ability to help discriminate between interesting rare events and the background. Hardware-based pattern recognition for fast triggering on particle tracks has been successfully used in high-energy physics experiments for some time. The CDF Silicon Vertex Trigger (SVT) at the Fermilab Tevatron is an excellent example. The method used there, developed in the 1990's, is based on algorithms that use a massively parallel associative memory architecture to identify patterns efficiently at high speed. However, due to much higher occupancy and event rates at the LHC, and the fact that the LHC detectors have a much larger number of channels in their tracking detectors, there is an enormous challenge in implementing pattern recognition for a track trigger, requiring about three orders of magnitude more associative memory patterns than what was used in the original CDF SVT. Significant improvement in the architecture of associative memory structures is needed to run fast pattern recognition algorithms of this scale. We are proposing the development of 3D integrated circuit technology as a way to implement new associative memory structures for fast pattern recognition applications. Adding a 'third' dimension to the signal processing chain, as compared to the two-dimensional nature of printed circuit boards, Field Programmable Gate Arrays (FPGAs), etc., opens up the possibility for new architectures that could dramatically enhance pattern recognition capability. We are currently performing preliminary design work to demonstrate the feasibility of this approach. In this proposal, we seek to develop the design and perform the ASIC engineering necessary to realize a prototype device. While our focus here is on the Energy Frontier (e.g. the LHC), the approach may have applications in experiments in the Intensity Frontier and the Cosmic Frontier as well as other scientific and medical projects. In fact, the technique that we are proposing is very generic and could have wide applications far beyond track trigger, both within and outside HEP.
43 PARTICLE ACCELERATORS↗