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A new class of CMOS VLSI asynchronous sequential circuits utilizing pass transistors is introduced. This class of self synchronizing circuits eliminates the need for critical race free state assignments. These circuits synchronize the transition path action by forcing the circuit to sequence through proper unstable states.
A large class of scientific and engineering applications may be classified as irregular and loosely synchronous from the perspective of parallel processing. We present a partial classification of such problems. This classification has motivated us to enhance FORTRAN D to provide language support for irregular, loosely synchronous problems. We present techniques for parallelization of such problems in the context of FORTRAN D.
Proposed optoelectronic system for guiding vehicle in approaching and docking with another vehicle includes active optical targets (flashing lights) on approached vehicle synchronized with sensor and image-processing circuitry on approaching vehicle. Conceived for use in automated approach and docking of two spacecraft. Also applicable on Earth to manually controlled and automated approach and docking of land vehicles, aircraft, boats, and submersible vehicles, using GPS or terrestrial broadcast time signals for synchronization. Principal advantage: optical power reduced, with consequent enhancement of safety.
A new method that uses round-trip paths to accurately measure transmission delay for time synchronization is proposed. The performance of the method in Synchronous Digital Hierarchy networks is discussed. The feature of this method is that it separately measures the initial round trip path delay and the variations in round-trip path delay. The delay generated in SDH equipment is determined by measuring the initial round-trip path delay. In an experiment with actual SDH equipment, the error of initial delay measurement was suppressed to 30ns.
Almost everyone that has heard of SONET knows that the acronym stands for Synchronous Optical NETwork. There has been a host of magazine articles on SONET rings, SONET features, even SONET compatibility with digital radio. What has not been highly publicized is the critical relationship between SONET, network synchronization, and payload jitter. This topic is addressed.
An iterative logic array (ILA) architecture for synchronous sequential circuits is presented. This technique utilizes linear algebra to produce the design equations. The ILA realization of synchronous sequential logic can be fully automated with a computer program. A programmable design procedure is proposed to fullfill the design task and layout generation. A software algorithm in the C language has been developed and tested to generate 1 micron CMOS layouts using the Hewlett-Packard FUNGEN module generator shell.
The Code Converter/Clock Regenerator (CCCR) provides a low-cost alternative to high-performance Pulse Code Modulation (PCM) bit synchronizers in environments with a large Signal-to-Noise Ratio (SNR). In many applications, the CCCR can be used in place of PCM bit synchronizers at about one fifth the cost. The CCCR operates at rates from 10 bps to 2.5 Mbps and performs PCM code conversion and clock regeneration. The CCCR has been integrated into a stand-alone system configurable from one to six channels and has also been designed for use in VMEbus compatible systems.
This paper proposes faster, more robust, frame synchronization schemes for various Inmarsat-B and Inmarsat-M communication and signalling channels. Equations are developed which permit frame synchronization strategies of the type specified by Inmarsat to be evaluated in terms of average true lock time, average false maintenance time, and average search time. Evaluation of the currently specified framing schemes shows that a significant performance improvement is obtained by optimizing the threshold parameters of the scheme. The optimization seeks a compromise between the conflicting requirements of maximizing true lock time and minimizing search time.
A fault-tolerant clock synchronization circuit was designed and tested. A comparison to a previous design and the procedure followed to achieve the current optimization are included. The report also includes a description of the system and the results of tests performed to study the synchronization and fault-tolerant characteristics of the implementation.
In July 1994, the U.S. Naval Observatory (USNO) Time Service System Engineering Division conducted a field test to establish a baseline accuracy for two-way satellite time transfer synchronization. Three Hewlett-Packard model 5071 high performance cesium frequency standards were transported from the USNO in Washington, DC to Los Angeles, California in the USNO's mobile earth station. Two-Way Satellite Time Transfer links between the mobile earth station and the USNO were conducted each day of the trip, using the Naval Research Laboratory(NRL) designed spread spectrum modem, built by Allen Osborne Associates(AOA). A Motorola six channel GPS receiver was used to track the location and altitude of the mobile earth station and to provide coordinates for calculating Sagnac corrections for the two-way measurements, and relativistic corrections for the cesium clocks. This paper will discuss the trip, the measurement systems used and the results from the data collected. We will show the accuracy of using two-way satellite time transfer for synchronization and the performance of the three HP 5071 cesium clocks in an operational environment.
Responding to an increased demand for reliable, accurate time on the Internet and Milnet, the U.S. Naval Observatory Time Service has established the network time servers, tick.usno.navy.mil and tock.usno.navy.mil. The system clocks of these HP9000/747i industrial work stations are synchronized to within a few tens of microseconds of USNO Master Clock 2 using VMEbus IRIG-B interfaces. Redundant time code is available from a VMEbus GPS receiver. UTC(USNO) is provided over the network via a number of protocols, including the Network Time Protocol (NTP) (DARPA Network Working Group Report RFC-1305), the Daytime Protocol (RFC-867), and the Time protocol (RFC-868). Access to USNO network time services is presently open and unrestricted. An overview of USNO time services and results of LAN and WAN time synchronization tests will be presented.
The objective of this work is to validate mathematically derived clock synchronization theories and their associated algorithms through experiment. Two theories are considered, the Interactive Convergence Clock Synchronization Algorithm and the Mid-Point Algorithm. Special clock circuitry was designed and built so that several operating conditions and failure modes (including malicious failures) could be tested. Both theories are shown to predict conservative upper bounds (i.e., measured values of clock skew were always less than the theory prediction). Insight gained during experimentation led to alternative derivations of the theories. These new theories accurately predict the clock system's behavior. It is found that a 100% penalty is paid to tolerate worst case failures. It is also shown that under optimal conditions (with minimum error and no failures) the clock skew can be as much as 3 clock ticks. Clock skew grows to 6 clock ticks when failures are present. Finally, it is concluded that one cannot rely solely on test procedures or theoretical analysis to predict worst case conditions. conditions.
Synchronization times reduced to reduce loss of data. Scheme for decoding received doubly encoded binary-data signal provides for joint synchronization of two decoders. Applies to concatenated error-correcting channel coding communication system in which, at transmitter, data first encoded by interleaved Reed-Solomon code (block code), then by convolutional code.
This talk presents the latest stage in formal development of a fault-tolerant clock synchronization circuit. The development spans from a high level specification of the required properties to a circuit realizing the core function of the system. An abstract description of an algorithm has been verified to satisfy the high-level properties using the mechanical verification system EHDM. This abstract description is recast as a behavioral specification input to the Digital Design Derivation system (DDD) developed at Indiana University. DDD provides a formal design algebra for developing correct digital hardware. Using DDD as the principle design environment, a core circuit implementing the clock synchronization algorithm was developed. The design process consisted of standard DDD transformations augmented with an ad hoc refinement justified using the Prototype Verification System (PVS) from SRI International. Subsequent to the above development, Wilfredo Torres-Pomales discovered an area-efficient realization of the same function. Establishing correctness of this optimization requires reasoning in arithmetic, so a general verification is outside the domain of both DDD transformations and model-checking techniques. DDD represents digital hardware by systems of mutually recursive stream equations. A collection of PVS theories was developed to aid in reasoning about DDD-style streams. These theories include a combinator for defining streams that satisfy stream equations, and a means for proving stream equivalence by exhibiting a stream bisimulation. DDD was used to isolate the sub-system involved in Torres-Pomales' optimization. The equivalence between the original design and the optimized verified was verified in PVS by exhibiting a suitable bisimulation. The verification depended upon type constraints on the input streams and made extensive use of the PVS type system. The dependent types in PVS provided a useful mechanism for defining an appropriate bisimulation.
Solving the hard Satisfiability Problem is time consuming even for modest-sized problem instances. Solving the Random L-SAT Problem is especially difficult due to the ratio of clauses to variables. This report presents a parallel synchronous simulated annealing method for solving the Random L-SAT Problem on a large-scale distributed-memory multiprocessor. In particular, we use a parallel synchronous simulated annealing procedure, called Generalized Speculative Computation, which guarantees the same decision sequence as sequential simulated annealing. To demonstrate the performance of the parallel method, we have selected problem instances varying in size from 100-variables/425-clauses to 5000-variables/21,250-clauses. Experimental results on the AP1000 multiprocessor indicate that our approach can satisfy 99.9 percent of the clauses while giving almost a 70-fold speedup on 500 processors.
A constant outward radial thrust acceleration can be used to reduce the radius of a circular orbit of specified period. Heliocentric circular orbits are designed to match the orbital period of Earth or Mars for various radial thrust accelerations and are defined as synchronous orbits. Minimum-time solar sail orbit transfers to these synchronous heliocentric orbits are presented.
Gear cracks are typically difficult to diagnose with sufficient time before catastrophic damage occurs. Significant damage must be present before algorithms appear to be able to detect the damage. Frequently there are multiple gear meshes on a single shaft. Since they are all synchronous with the shaft frequency, the commonly used synchronous averaging technique is ineffective in removing other gear mesh effects. Carefully applying a filter to these extraneous gear mesh frequencies can reduce the overall vibration signal and increase the accuracy of commonly used vibration metrics. The vibration signals from three seeded fault tests were analyzed using this filtering procedure. Both the filtered and unfiltered vibration signals were then analyzed using commonly used fault detection metrics and compared. The tests were conducted on aerospace quality spur gears in a test rig. The tests were conducted at speeds ranging from 2500 to 5000 revolutions per minute and torques from 184 to 228 percent of design load. The inability to detect these cracks with high confidence results from the high loading which is causing fast fracture as opposed to stable crack growth. The results indicate that these techniques do not currently produce an indication of damage that significantly exceeds experimental scatter.
The research reports on the development of a whole-field, system-level interferometry technique having phase-synchronized data acquisition and adjustable phase triggering. The technique utilizes a Fizeau interferometer, arbitrary function generator, oscilloscope, trigger filter, and CCD camera to determine the out-of-plane modal frequencies of a thin, highly reflective membrane. The technique generates phase-adjustable CCD camera trigger signals that are synchronized to the audio frequency excitation signal. The surface figures from the resulting interferograms were evaluated with fringe-following software and compared against that of an ideal membrane vibrating at resonance.