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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 361 records · Page 20
All sourcesNASA NTRSDOE OSTI
NASA NTRS1980

High-energy subnanosecond pulse amplification in XeCl

Pulse slicing and two-pass amplification are investigated as a means of producing high-energy subnanosecond pulses in the near ultraviolet. A simple laboratory-scale XeCl oscillator-Pockels cell pulse slicer-amplifier system is used to produce 50-mJ pulses of subnanosecond duration at 308 nm. Comparison of multinanosecond and subnanosecond pulse amplification allows estimation of the amplifier energy storage time to be 5 ns and demonstrates nearly complete extraction of available stored energy by the subnanosecond pulse.

Pacala, T. J.↗
NASA NTRS1982

High-Speed Wafer Slicer

Multiblade cutter slices silicon ingots into solar-cell wafers quickly and with little waste. Speed and blade pressure ensure high wafer-production rate. Lightweight, balanced construction minimizes blade vibration and reduces sideways motion that would otherwise widen kerf and waste silicon.

Schmid, F.↗
NASA NTRS1980

G-cueing microcontroller (a microprocessor application in simulators)

A g cueing microcontroller is described which consists of a tandem pair of microprocessors, dedicated to the task of simulating pilot sensed cues caused by gravity effects. This task includes execution of a g cueing model which drives actuators that alter the configuration of the pilot's seat. The g cueing microcontroller receives acceleration commands from the aerodynamics model in the main computer and creates the stimuli that produce physical acceleration effects of the aircraft seat on the pilots anatomy. One of the two microprocessors is a fixed instruction processor that performs all control and interface functions. The other, a specially designed bipolar bit slice microprocessor, is a microprogrammable processor dedicated to all arithmetic operations. The two processors communicate with each other by a shared memory. The g cueing microcontroller contains its own dedicated I/O conversion modules for interface with the seat actuators and controls, and a DMA controller for interfacing with the simulation computer. Any application which can be microcoded within the available memory, the available real time and the available I/O channels, could be implemented in the same controller.

Horattas, C. G.↗
NASA NTRS1980

Distributed microprocessors in a tactical universal modem

The distributed microprocessor system associated with a wideband signal conversion unit (WBSCU) is described. Multiple embedded 8086 and 2901 microprocessors, supported by dedicated hardware modules, perform the required real time operations for both transmit and receive functions. Commands from a host computer determine the configuration of the WBSCU via the IEEE 488 bus. Each of the four WBSCU channels is assigned to process a specified IF waveform; each channel configures its own resources and, in some cases, borrows resources from other channels. The processed waveform data is communicated from individual channels to redundant global memories. Data flow between the user community and global memories occurs via redundant 1553 buses through intelligent Bus Interface Units. Each WBSCU channel contains one 2901 bit slice machine and one 8086 microprocessor. The 2901 provides high speed processing capability for the most time critical operations. The 8086 is used for lower speed processing tasks where its high level language capability can be better exploited. Each 8086 has a global bus for wideband interprocessor communication, and a local bus for 8086/2901, master/slave communication. Software architecture consists of a control and communications structure governing mode dependent signal processing tasks.

Gray, D. M.↗
NASA NTRS1980

Application of software technology to a future spacecraft computer design

A study was conducted to determine how major improvements in spacecraft computer systems can be obtained from recent advances in hardware and software technology. Investigations into integrated circuit technology indicated that the CMOS/SOS chip set being developed for the Air Force Avionics Laboratory at Wright Patterson had the best potential for improving the performance of spaceborne computer systems. An integral part of the chip set is the bit slice arithmetic and logic unit. The flexibility allowed by microprogramming, combined with the software investigations, led to the specification of a baseline architecture and instruction set.

Labaugh, R. J.↗
NASA NTRS1980

Trophic classification of Tennessee Valley area reservoirs derived from LANDSAT multispectral scanner data

LANDSAT MSS data from four different dates were extracted from computer tapes using a semiautomated digital data handling and analysis system. Reservoirs were extracted from the surrounding land matrix by using a Band 7 density level slice of 3; and descriptive statistics to include mean, variance, and ratio between bands for each of the four bands were calculated. Significant correlations ( 0.80) were identified between the MSS statistics and many trophic indicators from ground truth water quality data collected at 35 reservoirs in the greater Tennessee Valley region. Regression models were developed which gave significant estimates of each reservoir's trophic state as defined by its trophic state index and explained in all four LANDSAT frames at least 85 percent of the variability in the data. To illustrate the spatial variations within reservoirs as well as the relative variations between reservoirs, a table look up elliptical classification was used in conjunction with each reservoir's trophic state index to classify each reservoir on a pixel by pixel basis and produce color coded thematic representations.

Meinert, D. L.↗
NASA NTRS1980

The establishment of a production-ready manufacturing process utilizing thin silicon substrates for solar cells

Three inch diameter Czochralski silicon substrates sliced directly to 5 mil, 8 mil, and 27 mil thicknesses with wire saw techniques were procured. Processing sequences incorporating either diffusion or ion implantation technologies were employed to produce n+p or n+pp+ solar cell structures. These cells were evaluated for performance, ease of fabrication, and cost effectiveness. It was determined that the use of 7 mil or even 4 mil wafers would provide near term cost reductions for solar cell manufacturers.

Pryor, R. A.↗
NASA NTRS1980

Seasat SAR identification of dry climate urban land cover

Digitally processed Seasat synthetic aperture radar (SAR) imagery of the Denver, Colorado area was examined to assess its potential for mapping urban land cover and the compatibility of SAR derived classes with those described in the U.S. Geological Survey classification system. The entire scene was interpreted to generate a small-scale land cover map. In addition, six subscene enlargements representative of urban land cover categories extant in the area were used as test sites for detailed analysis of land cover types. Two distinct approaches were employed and compared in examining the imagery - a visual interpretation of black-and-white positive transparencies and an automated-machine/visual interpretation. The latter used the Image 100 interactive image analysis system to generate land cover classes by density level slicing of the image frequency histogram.

Henderson, F. M.↗
NASA NTRS1980

A silicon sheet casting experiment

The casting of silicon blanks for solar cells directly without slicing is an exciting concept. An experiment was performed to investigate the feasibility of developing a machine that casts wafers directly. A Czochralski furnace was modified to accept a graphite ingot-simulating fixture. Silicon was melted in the middle of the ingot simulator in a boron nitride mold. Sample castings showed reasonable crystal size. Solar cells were made from the cast blanks. The performance is reported.

Bickler, D. B.↗
NASA NTRS1981

Video image processor on the Spacelab 2 Solar Optical Universal Polarimeter /SL2 SOUP/

The SOUP instrument is designed to obtain diffraction-limited digital images of the sun with high photometric accuracy. The Video Processor originated from the requirement to provide onboard real-time image processing, both to reduce the telemetry rate and to provide meaningful video displays of scientific data to the payload crew. This original concept has evolved into a versatile digital processing system with a multitude of other uses in the SOUP program. The central element in the Video Processor design is a 16-bit central processing unit based on 2900 family bipolar bit-slice devices. All arithmetic, logical and I/O operations are under control of microprograms, stored in programmable read-only memory and initiated by commands from the LSI-11. Several functions of the Video Processor are described, including interface to the High Rate Multiplexer downlink, cosmetic and scientific data processing, scan conversion for crew displays, focus and exposure testing, and use as ground support equipment.

Lindgren, R. W.↗
NASA NTRS1983

VLSI Reed-Solomon Encoder

Modular Reed-solomon encoder uses identical custom VLSI chips called "symbol slices." By cascading and properly interconnecting group of these chips, encoder is made for any desired error-correcting capability and interleaving level. VLSI encoder requires only one-tenth the number of chips required by conventional Reed-Solomon Circuit implemented with discrete IC's.

Liu, K. Y.↗
NASA NTRS1983

High-Production Silicon-Ingot Slicer

New concept for slicing silicon ingots into wafers promises to increase production rates and improve yields of good wafers, thereby reducing cost of manufacturing silicon solar cells. In proposed wafer slicer, stack of ganged blades cuts group of silicon ingots simultaneously. Blades cut horizontally while ingots rotate about their vertical axes.

Kuo, Y. S.↗
NASA NTRS1981

Chesapeake Bay plume dynamics from LANDSAT

LANDSAT images with enhancement and density slicing show that the Chesapeake Bay plume usually frequents the Virginia coast south of the Bay mouth. Southwestern (compared to northern) winds spread the plume easterly over a large area. Ebb tide images (compared to flood tide images) show a more dispersed plume. Flooding waters produce high turbidity levels over the shallow northern portion of the Bay mouth.

Munday, J. C., Jr.↗
NASA NTRS1981

Development of an 1100 deg F capacitor

The feasibility of developing a high temperature capacitor for 1100 F operation which is as small and light as conventional capacitors for normal operating temperatures is discussed. Pyrolyic boron nitride (PBN) was selected for the dielectric. The PBN capacitors were made by slicing and lapping material from thick blocks and then sputtering thin film electrodes. These capacitors had breakdown strengths of 7,000 volts per mil and a dissipation factor of less than 0.001 at 1100 F. Additional processing improvements were made after testing a multi-layer or stacked PBN capacitor for 1,000 hours at 1100 F. Sputter etching the wafers before depositing electrodes resulted in a reduction in dissipation factor. A sputtered boron nitride film applied to the outer electrode surfaces produced a more stable capacitor. A design for a 0.1 mu F capacitor and a summary of PBN wafer fabrication costs are given.

Stapleton, R. E.↗
NASA NTRS1982

Design and use of multiple blade slurry sawing in a production atmosphere

The technique and uses of the multiple blade slurry (MBS) saw are considered. Multiple bands of steel are arranged in a frame and the frame is reciprocated with the steel bands to a workpiece, while simultaneously applying abrasive at the point of contact. The blades wear slots in the workpiece and progress through the piece resulting in several parts of wafers. The transition to MBA from diamond slicing is justified by savings resulting from minimized kerf losses, minimized subsurface damage, and improved surface quality off the saw. This allows wafering much closer to finished thickness specifications. The current state of the art MBS technology must be significantly improved if the low cost solar array (LSA) goals are to be attained. It is concluded that although MBS will never be the answer to every wafering requirement, the economical production of wafers to LSA project specifications will be achieved.

Lynah, F. P., Jr.↗
NASA NTRS1981

Architecture for VLSI design of Reed-Solomon encoders

The logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is discussed. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255,223) RD encoder requiring around 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.

Liu, K. Y.↗
NASA NTRS1980

Preliminary results of mapping urban land cover with Seasat SAR imagery

The detectability of urban land cover types is explored using digitally processed Seasat SAR imagery of the Denver, Colorado area. Test sites within the metropolitan area were selected to include a cross section of Anderson, et. al. Level II land cover classes and cover types representative of the urban area growth stages. Using the Image 100 interactive processing system each test site was level sliced in an attempt to define specific reflectance boundaries for each cover type and to determine the spectral and spatial characteristics of homogeneous response regions. The rural-urban fringe boundary was readily definable, but a precise Level I and Level II land cover classification was not possible. High density housing could be separated from low density housing and from parks, but reflectance values were often look angle dependent. Confusion between some water and vegetation responses also posed problems.

Henderson, F. M.↗
NASA NTRS1982

Architecture for VLSI design of Reed-Solomon encoders

A description is given of the logic structure of the universal VLSI symbol-slice Reed-Solomon (RS) encoder chip, from a group of which an RS encoder may be constructed through cascading and proper interconnection. As a design example, it is shown that an RS encoder presently requiring approximately 40 discrete CMOS ICs may be replaced by an RS encoder consisting of four identical, interconnected VLSI RS encoder chips, offering in addition to greater compactness both a lower power requirement and greater reliability.

Liu, K. Y.↗