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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 361 records · Page 20
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Dataset for manuscript "Rotational Memory Function of SPC/E water"

Memory effect are essential for dynamics of condensed materials and are responsible for non-exponential relaxation of correlation functions of dynamic variables through the memory function entering the memory equation. Memory functions of dipole rotations for polar liquids have never been calculated. We present here calculations of memory functions and single-dipole rotations and of the overall system dipole moment for SPC/E water measured by dielectric spectroscopy. The memory functions for single-particle and collective dynamics turn out to be nearly identical. This result validates theories of dielectric spectroscopy in terms of single-particle time correlation function and the connection between the collective and single-particle relaxation times in terms of the Kirkwood factor. The dataset includes single particle and system dipole moments, including their time-dependence.

74 ATOMIC AND MOLECULAR PHYSICS↗
DOE OSTI2023

Quantum optical memory for entanglement distribution

Optical photons are powerful carriers of quantum information, which can be delivered in free space by satellites or in fibers on the ground over long distances. Entanglement of quantum states over long distances can empower quantum computing, quantum communications, and quantum sensing. Quantum optical memories are devices designed to store quantum information in the form of stationary excitations, such as atomic coherence, and are capable of coherently mapping these excitations to flying qubits. Quantum memories can effectively store and manipulate quantum states, making them indispensable elements in future long-distance quantum networks. Over the past two decades, quantum optical memories with high fidelities, high efficiencies, long storage times, and promising multiplexing capabilities have been developed, especially at the single-photon level. In this review, we introduce the working principles of commonly used quantum memory protocols and summarize the recent advances in quantum memory demonstrations. We also offer a vision for future quantum optical memory devices that may enable entanglement distribution over long distances.

Lei, Yisheng↗
DOE OSTI2020

Traversing large graphs on GPUs with unified memory

Due to the limited capacity of GPU memory, the majority of prior work on graph applications on GPUs has been restricted to graphs of modest sizes that fit in memory. Recent hardware and software advances make it possible to address much larger host memory transparently as a part of a feature known as unified virtual memory. While accessing host memory over an interconnect is understandably slower, the problem space has not been sufficiently explored in the context of a challenging workload with low computational intensity and an irregular data access pattern such as graph traversal. We analyse the performance of breadth first search (BFS) for several large graphs in the context of unified memory and identify the key factors that contribute to slowdowns. Next, we propose a lightweight offline graph reordering algorithm, HALO (Harmonic Locality Ordering), that can be used as a pre-processing step for static graphs. HALO yields speedups of 1.5x-1.9x over baseline in subsequent traversals. Our method specifically aims to cover large directed real world graphs in addition to undirected graphs whereas prior methods only account for the latter. Additionally, we demonstrate ties between the locality ordering problem and graph compression and show that prior methods from graph compression such as recursive graph bisection can be suitably adapted to this problem.

Gera, Prasun↗
DOE OSTI2014

A Compute Capable SSD Architecture for Next-Generation Non-volatile Memories

Existing storage technologies (e.g., disks and ash) are failing to cope with the processor and main memory speed and are limiting the overall perfor- mance of many large scale I/O or data-intensive applications. Emerging fast byte-addressable non-volatile memory (NVM) technologies, such as phase-change memory (PCM), spin-transfer torque memory (STTM) and memristor are very promising and are approaching DRAM-like performance with lower power con- sumption and higher density as process technology scales. These new memories are narrowing down the performance gap between the storage and the main mem- ory and are putting forward challenging problems on existing SSD architecture, I/O interface (e.g, SATA, PCIe) and software. This dissertation addresses those challenges and presents a novel SSD architecture called XSSD. XSSD o oads com- putation in storage to exploit fast NVMs and reduce the redundant data tra c across the I/O bus. XSSD o ers a exible RPC-based programming framework that developers can use for application development on SSD without dealing with the complication of the underlying architecture and communication management. We have built a prototype of XSSD on the BEE3 FPGA prototyping system. We implement various data-intensive applications and achieve speedup and energy ef- ciency of 1.5-8.9 and 1.7-10.27 respectively. This dissertation also compares XSSD with previous work on intelligent storage and intelligent memory. The existing ecosystem and these new enabling technologies make this system more viable than earlier ones.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

Models for Total-Dose Radiation Effects in Non-Volatile Memory

The objective of this work is to develop models to predict radiation effects in non- volatile memory: flash memory and ferroelectric RAM. In flash memory experiments have found that the internal high-voltage generators (charge pumps) are the most sensitive to radiation damage. Models are presented for radiation effects in charge pumps that demonstrate the experimental results. Floating gate models are developed for the memory cell in two types of flash memory devices by Intel and Samsung. These models utilize Fowler-Nordheim tunneling and hot electron injection to charge and erase the floating gate. Erase times are calculated from the models and compared with experimental results for different radiation doses. FRAM is less sensitive to radiation than flash memory, but measurements show that above 100 Krad FRAM suffers from a large increase in leakage current. A model for this effect is developed which compares closely with the measurements.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2017

A Case Study on Neural Inspired Dynamic Memory Management Strategies for High Performance Computing.

As high performance computing architectures pursue more computational power there is a need for increased memory capacity and bandwidth as well. A multi-level memory (MLM) architecture addresses this need by combining multiple memory types with different characteristics as varying levels of the same architecture. How to efficiently utilize this memory infrastructure is an unknown challenge, and in this research we sought to investigate whether neural inspired approaches can meaningfully help with memory management. In particular we explored neurogenesis inspired re- source allocation, and were able to show a neural inspired mixed controller policy can beneficially impact how MLM architectures utilize memory.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2016

Samba: A Detailed Memory Management Unit (MMU) for the SST Simulation Framework

The Memory Management Unit (MMU) is one of the most important parts of any modern computing system. It can be thought of as the hardware support for virtual memory, which enforces access permissions, and manages the translation of processes' virtual addresses into real memory physical addresses. The operating system (OS) allocates the physical memory in a small granularity frames that can be accessed by processes with appropriate permissions. Each process has the illusion of having an entire memory space, however, the actual addresses issued by the process, (`virtual addresses'), are translated into the physical frame address allocated by the OS through virtual memory.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

A Cascaded Random Access Quantum Memory

Dynamic random access memory is critical to classical computing but notably absent in experimental quantum computers. Here we realize an 8-bit cascaded random access quantum memory using superconducting circuits and cavities and showcase the ability to perform arbitrary gate operations on it. In addition to individual error channels such as photon loss, quantum memories can also experience decoherence from many-body self-interaction. We characterize the origin and contributions of many-body infidelity throughout the memory cycle. We find that individual modes can be accessed with $\lesssim 1.5\%$ infidelity per mode and that the entire memory can be accessed in arbitrary order with an error rate below the depolarization threshold of the surface code, paving the way for fault-tolerant quantum memories.

Li, Ziqian [Stanford U., Appl. Phys. Dept.; Stanfo↗
NASA NTRS1976

Optical mass memories

Optical and magnetic variants in the design of trillion-bit read/write memories are compared and tabulated. Components and materials suitable for a random access read/write nonmoving memory system are examined, with preference given to holography and photoplastic materials. Advantages and deficiencies of photoplastics are reviewed. Holographic page composer design, essential features of an optical memory with no moving parts, fiche-oriented random access memory design, and materials suitable for an efficient photoplastic fiche are considered. The optical variants offer advantages in lower volume and weight at data transfer rates near 1 Mbit/sec, but power drain is of the same order as for the magnetic variants (tape memory, disk memory). The mechanical properties of photoplastic film materials still leave much to be desired.

Bailey, G. A.↗
NASA NTRS1978

A wide bandwidth CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. CCD shift register memories (8K bit) were used to construct a feasibility model 128 K-bit buffer memory system. Serial data that can have rates between 150 kHz and 4.0 MHz can be stored in 4K-bit, randomly-accessible memory blocks. Peak power dissipation during a data transfer is less than 7 W, while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. System expansion to accommodate parallel inputs or a greater number of memory blocks can be performed in a modular fashion. Since the control logic does not increase proportionally to increase in memory capacity, the power requirements per bit of storage can be reduced significantly in a larger system.

Siemens, K.↗
NASA NTRS1978

Test and evaluation of bubble memories

A description is presented of a test program which has shown that well-constructed bubble memories can operate reliably over long periods of time and at low error rates. Even the relatively high error rate of one memory during burn-in can be considered acceptable if compared with tape recorder standards. No wear-out mechanism or aging could be detected. Bubble memories are now considered suitable for long-duration space missions and certainly are suitable for many military and commercial applications. It must be recognized, however, that bubble memories are complex devices and not yet fully understood. While the particular memory tested may never find practical applications, it nevertheless has provided insight into performance characteristics considered typical of bubble memories.

Bahm, E.↗
NASA NTRS1979

Implementing a bubble memory hierarchy system

This paper reports on implementation of a magnetic bubble memory in a two-level hierarchial system. The hierarchy used a major-minor loop device and RAM under microprocessor control. Dynamic memory addressing, dual bus primary memory, and hardware data modification detection are incorporated in the system to minimize access time. It is the objective of the system to incorporate the advantages of bipolar memory with that of bubble domain memory to provide a smart, optimal memory system which is easy to interface and independent of user's system.

Segura, R.↗
NASA NTRS1980

A bubble memory module

A bubble memory module design providing flexibility for many user applications in spacecraft data recording is described. The memory module can be used with user-designed controllers with the memory organization determined by the application. Asynchronous data rates from zero to 1.33 Mbits/sec at minimum power are accomplished by using 8-chip memory cells with 100 K bit serial chips. The memory module is expandable from a 4 x 2 cell matrix to a 4 x 16 cell matrix corresponding to an expandable capacity of 6.55 M to 52.4 M bits. The module's design, utility in various memory systems, and user clocking scheme are described.

Hayes, P. J.↗
NASA NTRS1982

Short-term memory and dual task performance

Two hypotheses concerning the way in which short-term memory interacts with another task in a dual task situation are considered. It is noted that when two tasks are combined, the activity of controlling and organizing performance on both tasks simultaneously may compete with either task for a resource; this resource may be space in a central mechanism or general processing capacity or it may be some task-specific resource. If a special relationship exists between short-term memory and control, especially if there is an identity relationship between short-term and a central controlling mechanism, then short-term memory performance should show a decrement in a dual task situation. Even if short-term memory does not have any particular identity with a controlling mechanism, but both tasks draw on some common resource or resources, then a tradeoff between the two tasks in allocating resources is possible and could be reflected in performance. The persistent concurrence cost in memory performance in these experiments suggests that short-term memory may have a unique status in the information processing system.

Regan, J. E.↗
NASA NTRS1986

Memory and subjective workload assessment

Recent research suggested subjective introspection of workload is not based upon specific retrieval of information from long term memory, and only reflects the average workload that is imposed upon the human operator by a particular task. These findings are based upon global ratings of workload for the overall task, suggesting that subjective ratings are limited in ability to retrieve specific details of a task from long term memory. To clarify the limits memory imposes on subjective workload assessment, the difficulty of task segments was varied and the workload of specified segments was retrospectively rated. The ratings were retrospectively collected on the manipulations of three levels of segment difficulty. Subjects were assigned to one of two memory groups. In the Before group, subjects knew before performing a block of trials which segment to rate. In the After group, subjects did not know which segment to rate until after performing the block of trials. The subjective ratings, RTs (reaction times) and MTs (movement times) were compared within group, and between group differences. Performance measures and subjective evaluations of workload reflected the experimental manipulations. Subjects were sensitive to different difficulty levels, and recalled the average workload of task components. Cueing did not appear to help recall, and memory group differences possibly reflected variations in the groups of subjects, or an additional memory task.

Staveland, L.↗
NASA NTRS1985

Bubble memory module for spacecraft application

Bubble domain technology offers an all-solid-state alternative for data storage in onboard data systems. A versatile modular bubble memory concept was developed. The key module is the bubble memory module which contains all of the storage devices and circuitry for accessing these devices. This report documents the bubble memory module design and preliminary hardware designs aimed at memory module functional demonstration with available commercial bubble devices. The system architecture provides simultaneous operation of bubble devices to attain high data rates. Banks of bubble devices are accessed by a given bubble controller to minimize controller parts. A power strobing technique is discussed which could minimize the average system power dissipation. A fast initialization method using EEPROM (electrically erasable, programmable read-only memory) devices promotes fast access. Noise and crosstalk problems and implementations to minimize these are discussed. Flight memory systems which incorporate the concepts and techniques of this work could now be developed for applications.

Hayes, P. J.↗
NASA NTRS1987

Electronic implementation of associative memory based on neural network models

An electronic embodiment of a neural network based associative memory in the form of a binary connection matrix is described. The nature of false memory errors, their effect on the information storage capacity of binary connection matrix memories, and a novel technique to eliminate such errors with the help of asymmetrical extra connections are discussed. The stability of the matrix memory system incorporating a unique local inhibition scheme is analyzed in terms of local minimization of an energy function. The memory's stability, dynamic behavior, and recall capability are investigated using a 32-'neuron' electronic neural network memory with a 1024-programmable binary connection matrix.

Moopenn, A.↗
NASA NTRS1987

Neural network based feed-forward high density associative memory

A novel thin film approach to neural-network-based high-density associative memory is described. The information is stored locally in a memory matrix of passive, nonvolatile, binary connection elements with a potential to achieve a storage density of 10 to the 9th bits/sq cm. Microswitches based on memory switching in thin film hydrogenated amorphous silicon, and alternatively in manganese oxide, have been used as programmable read-only memory elements. Low-energy switching has been ascertained in both these materials. Fabrication and testing of memory matrix is described. High-speed associative recall approaching 10 to the 7th bits/sec and high storage capacity in such a connection matrix memory system is also described.

Daud, T.↗