Study of failure modes of multilevel large scale integrated circuits
Evaluation tests for electrical properties of oxide silicon interfaces in multilevel microcircuits
Schlegel, E. S.↗
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A brief review of the state of the art and some recent results on electromigration in integrated circuit aluminum metallization.
Dielectric overcoatings effect on Al interconnections electromigration in IC metallization, noting longer intervals between failures
Schwartz, S.↗
Large scale integrated circuits for space electronics
LSI circuits in space electronics, discussing packaging, reliability, applications, etc
Hamiter, L.↗
Silicon contact for area reduction of integrated circuits
Epitaxially grown Si contact for area reduction of MOS transistor circuits
Alexander, D. S.↗
Metallization systems for integrated circuits
Metallization systems materials for IC, discussing environmental stability, metals electromigration, electrochemical corrosion tests, etc
Terry, L. E.↗
Improved methods of forming monolithic integrated circuits having complementary bipolar transistors
Two new processes form complementary transistors in monolithic semiconductor circuits, require fewer steps /infusions/ than previous methods, and eliminate such problems as nonuniform h sub FE distribution, low yield, and large device formation.
Bohannon, R. O., Jr.↗
Computer-aided design of large-scale integrated circuits - A concept
Circuit design and mask development sequence are improved by using general purpose computer with interactive graphics capability establishing efficient two way communications link between design engineer and system. Interactive graphics capability places design engineer in direct control of circuit development.
Schansman, T. T.↗
Advantages of vapor-plated phosphosilicate films in large-scale integrated circuit arrays
MOS large scale IC phosphosilicate glass substrate vapor deposits effects, including hardness, pinhole density and electromigration
Keen, R. S., Jr.↗
Ferrimagnetic parts for microwave integrated circuits
Ferrimagnetic components in microwave IC, considering junction circulators, planar phase shifters, etc
Harrison, G. R.↗
Beam-lead processing of complementary MOS integrated circuits
Beam-lead technology application to complementary MOS IC processing
Murray, L. A.↗
Evaluation of errors in prior mean and variance in the estimation of integrated circuit failure rates using Bayesian methods
The critical point of any Bayesian analysis concerns the choice and quantification of the prior information. The effects of prior data on a Bayesian analysis are studied. Comparisons of the maximum likelihood estimator, the Bayesian estimator, and the known failure rate are presented. The results of the many simulated trails are then analyzed to show the region of criticality for prior information being supplied to the Bayesian estimator. In particular, effects of prior mean and variance are determined as a function of the amount of test data available.
Fletcher, B. C.↗
Derivation of a tangent function using an integrated circuit four-quadrant multiplier
A tangent function generator is provided which utilizes input signals proportionate to the sine and cosine of a given angle. The equipment accomplishes a trigonometric manipulation which forms an output signal substantially independent of the input reference voltage but proportional to the tangent of the angle. The device uses a multiplier and operational amplifier.
Bregman, B. J.↗
A quick accurate method to measure the dielectric constant of microwave integrated-circuit substrates.
Explore the source record for details and available documents.
Howell, J. Q.↗
Integrated-circuit balanced parametric amplifier
Amplifier, fabricated on single dielectric substrate, has pair of Schottky barrier varactor diodes mounted on single semiconductor chip. Circuit includes microstrip transmission line and slot line section to conduct signals. Main features of amplifier are reduced noise output and low production cost.
Dickens, L. E.↗
An optimized output stage for MOS integrated circuits
An output device for optimizing propagation delay and minimizing chip area is described. An optimum means of tapering the output stages to minimize propagation delay is determined. The minimum delay is a function of the capacitive load to node ratio, the number of output stages, and the interstage propagation delay. The effects on area are also presented. A figure of merit which is a function of area and propagation time is defined which is of use in designing output stages. An optimum exists which can be considered the best compromise between further decreasing propagation delay and increasing chip area. Data are also presented which allow a designer to determine the minimum chip area once the capacitive load and the maximum allowable delay are known.
Lin, H. C.↗
The 1.06 micrometer avalanche photodiode detectors with integrated circuit preamplifiers
The development of a complete solid state 1.06 micron optical receiver which can be used in optical communications at data rates approaching 1.5 Gb/s, or in other applications requiring sensitive, short-pulse detection, is reported. This work entailed both the development of a new type of heterojunction 3-5 semiconductor alloy avalanche photodiode and an extremely charge-sensitive wideband low-noise preamp design making use of GaAs Schottky barrier-gate field effect transistors.
Eden, R. C.↗
Complementary DMOS/VMOS integrated-circuit-structure
Complementary metal-oxide-semiconductor (CMOS) structure has relatively high speed, high breakdown voltage, high transconductance and high packing densities.
Jhabvala, M. D.↗
On the applicability of integrated circuit technology to general aviation orientation estimation
The criteria of the significant value of the panel instruments used in general aviation were examined and kinematic equations were added for comparison. An instrument survey was performed to establish the present state of the art in linear and angular accelerometers, pressure transducers, and magnetometers. A very preliminary evaluation was done of the computers available for data evaluation and estimator mechanization. The mathematical model of a light twin aircraft employed in the evaluation was documented, the results of the sensor survey and the results of the design studies were presented.
Debra, D. B.↗