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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 361 records · Page 20

Demonstration of a Pyrotechnic Bolt-Retractor System

A paper describes a demonstration of the X-38 bolt-retractor system (BRS) on a spacecraft-simulating apparatus, called the Large Mobility Base, in NASA's Flight Robotics Laboratory (FRL). The BRS design was proven safe by testing in NASA's Pyrotechnic Shock Facility (PSF) before being demonstrated in the FRL. The paper describes the BRS, FRL, PSF, and interface hardware. Information on the bolt-retraction time and spacecraft-simulator acceleration, and an analysis of forces, are presented. The purpose of the demonstration was to show the capability of the FRL for testing of the use of pyrotechnics to separate stages of a spacecraft. Although a formal test was not performed because of schedule and budget constraints, the data in the report show that the BRS is a successful design concept and the FRL is suitable for future separation tests.

Johnston, Nick↗

Observations on Dynamic Qualification Testing of a Component with Nonlinear Deadband Interfaces

Typical flight hardware dynamic qualification tests exhibit nearly linear structural response when exposed to acceleration inputs from low to full qualification levels. Even in these “linear” cases, there is typically a trend of increasing damping with test levels. The nonlinear mechanism behind this increase in energy dissipation well understood – typically stick/slip hysteresis at joint connections. This paper is concerned with a different type of nonlinearity: deadbands at structural interfaces. Deadband nonlinearities can have a significant influence on structural response and modal/spectral characteristics which can present difficulties in test, analysis, and structural certification. This subject nonlinear behaviour is observed during flight qualification testing of the AQUARIUS instrument and discussed here. Simple physical reasoning and analytical model is utilized to explain the behaviour which is consistent with the test findings.

Majed, Arya↗

Accelerating Lossy and Lossless Compression on Emerging BlueField DPU Architectures

Data compression has become a crucial technique in addressing performance bottlenecks caused by increasing data volumes in High-Performance Computing (HPC), Big Data, and Deep Learning (DL). Despite its potential to boost system performance, recent studies have identified significant challenges with existing compression methods, mainly due to their high computational demands amidst continuously growing data sizes. Concurrently, the advent of Data Processing Units (DPUs), equipped with programmable System-on-Chip (SoC) and specialized compression accelerators, offers a promising opportunity to alter the landscape of data compression. This paper explores the complexities and potential of leveraging NVIDIA BlueField DPUs to accelerate lossy and lossless compression. Towards this, we introduce PEDAL, an innovative library that leverages the hardware capabilities of DPUs to unify and optimize data compression designs. Moreover, we seamlessly co-design PEDAL with the popular MPICH MPI library, demonstrating up to 101x speedup in compression time and 88x decrease in communication latency. Drawing on these achievements, we share our experience with various research communities about accelerating data compression on DPUs in communication-oriented HPC scenarios.

Li, Yuke↗

wa-hls4ml and lui-gnn: A benchmark and GNN-based surrogate model for hls4ml resource and latency estimation

As machine learning (ML) increasingly serves as a tool for addressing real-time challenges in scientific applications, the development of advanced tooling has significantly reduced the time required to iterate on various designs. These advancements have solved major obstacles, but also exposed new challenges. For example, processes that were not previously considered bottlenecks, such as model synthesis, are now becoming limiting factors in the rapid iteration of designs. To reduce these emerging constraints, multiple efforts are being launched toward designing an ML-based surrogate model that estimates resource usage of synthesized accelerator architectures. This model would reduce the design iteration time, especially when designing within a set of given hardware constraints. This approach shows considerable potential, but as it stands, the effort is early and would benefit from coordination and standardization to assist future work as it emerges. We introduce wa-hls4ml, a benchmark for ML accelerator resource and latency estimation, and its corresponding initial dataset of more than 100,000 fully connected neural networks, all synthesized using hls4ml and targeting Xilinx FPGAs. In addition to the resource utilization and latency data provided, the dataset includes generated artifacts and log files for many of the synthesized neural networks, in order to support future research in ML-based code generation. The benchmark evaluates the performance of resource and latency predictors against several common ML model architectures, primarily originating from scientific domains, as exemplar models, as well as the average performance across a subset of the dataset. We measure the performance of a given predictor model through multiple metrics, including $R^2$ score and SMAPE on regression tasks, as well as inference time to further characterize the estimator under test. Additionally, we introduce the latency/utilization inference graph neural network (lui-gnn), a surrogate model that uses a graph neural network to represent input architectures in the form of a directed graph. This graph representation allows for a diverse set of model architectures to all be effectively handled by a surrogate model. We present the architecture and performance of the model, as evaluated by the new proposed benchmark, including SMAPE, $R^2$ score, and inference times, and find that lui-gnn generally predicts latency and utilization for the 75\% quantile within several percent of the synthesized resources on the synthetic test dataset, indicating that this approach of estimating resource and latency via a surrogate models has promise and warrants further research.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

3D-ReG: A 3D ReRAM-based Heterogeneous Architecture for Training Deep Neural Networks

Deep neural network (DNN) models are being expanded to a broader range of applications. The computational capability of traditional hardware platforms cannot accommodate the growth of model complexity. Among recent technologies to accelerate DNN, resistive memory (ReRAM)-based processing-in-memory (PIM) emerged as a promising solution for DNN inference due to its high efficiency for matrix-based computation. We face two major technical challenges in extending the use of ReRAM-based accelerators for training: (1) full-precision data is essential in back-propagation; (2) the need to support both feed-forward and back-propagation aggravates the data-movement burden. We propose a heterogeneous architecture named as 3D-ReG, which leverages full-precision GPU to ensure training accuracy and low-overhead 3D integration to provide low-cost data movements. Moreover, we introduce conservative and aggressive task-mapping schemes, which partition the computation phases in different ways to balance execution efficiency and training accuracy. We evaluate 3D-ReG implemented with two 3D integration technologies, through-silicon vias (TSVs) and monolithic inter-tier vias (MIVs), and compare them with GPU-only and PIM-only counterparts. Various GPU-only platforms using two main-memory technologies (DRAM, ReRAM) and three interconnect technologies (2D, TSV, MIV) are evaluated as well. Experimental results show that 3D-ReG can achieve on average 5.64× training speedup and 3.56× higher energy efficiency compared with the GPU with DRAM as main memory, at the cost of 0.05%–3.39% accuracy drop. We define a new metric, gain-loss ratio (GLR), which quantitatively evaluates the capability of a DNN training hardware in terms of the model accuracy and hardware efficiency. The results of our comparison show that the aggressive task-mapping scheme on MIV-based 3D-ReG outperforms the other methods.

Computer Science↗

GronOR: Massively Parallel and GPU-Accelerated Non-Orthogonal Configuration Interaction for Large Molecular Systems

GronOR is a program package for non-orthogonal configuration interaction calculations for an electronic wave function built in terms of anti-symmetrized products of multi-configuration molecular fragment wave functions. The two-electron integrals that have to be processed may be expressed in terms of atomic orbitals or in terms of an orbital basis determined from the molecular orbitals of the fragments. The code has been specifically designed for execution on distributed memory massively parallel and Graphics Processing Unit (GPU)-accelerated computer architectures, using an MPI+OpenACC/OpenMP programming approach. The task-based execution model used in the implementation allows for linear scaling with the number of nodes on the largest pre-exascale architectures available, provides hardware fault resiliency, and enables effective execution on systems with distinct central processing unit-only and GPU-accelerated partitions. The code interfaces with existing multi-configuration electronic structure codes that provide optimized molecular fragment orbitals, configuration interaction coefficients, and the required integrals. Algorithm and implementation details, parallel and accelerated performance benchmarks, and an analysis of the sensitivity of the accuracy of results and computational performance to thresholds used in the calculations are presented.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

Navier: Dataflow Architecture for Computation Chemistry

Navier’s objectives were two evaluate the use of emerging technologies, especially dataflow accelerators, for high-performance computing (HPC) applications, specifically in the domain of chemistry, and to develop a prototype software stack to support such applications. Navier builds on capabilities previously developed by synergistic projects, such as PNNL Data Model Convergence (DMC) LDRD Hardware Advanced Workflows (HAW) and DuOMO, as well as DOE ARIAA. Throughout its 18 months, the Navier team developed new capabilities and artifacts at all levels of the HW/SW stack, provided a seamless way to integrate novel computing architectures (Sambanova SN10 and Xilinx Versal AI) into an existing software stack, developed chemistry workflows, data analytics tools, and HPC molecular dynamics workflows that leverage the developed stack and PNNL institutional investments in emerging architectures. Navier also explored the use of active learning to accelerate a computational chemistry workflow for organic molecules on PNNL Junction cluster (in collaboration with AMD/Xilinx). Navier developed tools, methodologies, and studies for hardware software co-design and (sparse) dataflow accelerators that are composable and can be used together or separately. These methodologies are now used in other projects, such as DOE AMAIS and HPDA. This report describes Navier’s achievement, the developed tools and methodologies, and the research findings and conclusions.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗

High-power test of a C-band linear accelerating structure with an RFSoC-based LLRF system

Normal conducting linear particle accelerators consist of multiple rf stations with accelerating structure cavities. Low-level rf (LLRF) systems are employed to set the phase and amplitude of the field in the accelerating structure and to compensate for the pulse-to-pulse fluctuation of the rf field in the accelerating structures with a feedback loop. The LLRF systems are typically implemented with analog rf mixers, heterodyne-based architectures, and discrete data converters. There are multiple rf signals from each of the rf stations, so the number of rf channels required increases rapidly with multiple rf stations. With a large number of rf channels, the footprint, component cost, and system complexity of the LLRF hardware will increase significantly. To meet the design goals of being compact and affordable for future accelerators, we have designed the next-generation LLRF (NG-LLRF) with a higher integration level based on RFSoC technology. The NG-LLRF system samples rf signals directly and performs rf mixing digitally. Further, the NG-LLRF has been characterized in loopback mode to evaluate the performance of the system and has also been tested with a standing-wave accelerating structure, a prototype for the Cool Copper Collider (C 3 ) with a peak rf power level up to 16.45 MW. The loopback test demonstrated amplitude fluctuation below 0.15% and phase fluctuation below 0.15°, which are considerably better than the requirements of C 3 . The rf signals from the different stages of the accelerating structure at different power levels are measured by the NG-LLRF, which will be critical references for the control algorithm designs. The NG-LLRF also offers flexibility in waveform modulation, so we have used rf pulses with various modulation schemes, which could be useful for controlling some of the rf stations in accelerators. In this paper, the high-power test results at different stages of the test setup will be summarized, analyzed, and discussed.

47 OTHER INSTRUMENTATION↗

A Hierarchical Task Scheduler for Heterogeneous Computing

Heterogeneous computing is one of the future directions of HPC. Task scheduling in heterogeneous computing must balance the challenge of optimizing the application performance and the need for an intuitive interface with the programming run-time to maintain programming portability. The challenge is further compounded by the varying data communication time between tasks. This paper proposes RANGER, a hardware-assisted task-scheduling framework. By integrating RISC-V cores with accelerators, the RANGER scheduling framework divides scheduling into global and local levels. At the local level, RANGER further partitions each task into fine-grained subtasks to reduce the overall makespan. At the global level, RANGER maintains the coarse granularity of the task specification, thereby maintaining programming portability. The extensive experimental results demonstrate that RANGER achieves a 12.7× performance improvement on average, while only requires 2.7% of area overhead.

Miniskar, Narasinga Rao↗

A Relief Zone Architecture for Enhanced Durability of Ultrathin Membranes in Electrochemical Conversion Devices

Premature cell failures in electrochemical conversion systems often result when membrane electrode assemblies (MEAs) are prepared with ultra-thin (= 15 micrometer-thick) polymer electrolyte membranes (PEMs). These high-performance PEMs are susceptible to mechanical degradation from stress concentrations arising from component and device-level integration. Herein, a relief zone was developed to mitigate mechanical degradation by alleviating excess and non-uniform compression across the active area. Relief zones, created through the ablation of carbonaceous diffusion material achieves a seamless adaptation across a range of MEA dimensions and electrochemical applications without need for costly hardware modifications. This concept was demonstrated using fuel cells as a case study. Accelerated stress test (AST) validations yielded a 6-fold improvement for MEAs prepared with relief zones (i.e., lifetime approximately 1500 h) compared to those fabricated using conventional edge-protection techniques, showcasing the utility of this technique in decoupling integration and device-level engineering effects from intrinsic material limitations for durable electrochemical devices.

14 SOLAR ENERGY↗

The hypervelocity impact facilities at the University of Kent at Canterbury, UK

The University of Kent at Canterbury facilities for production of hypervelocity impacts are discussed. Meteoroids are simulated by electrostatic acceleration of small (10(exp -12) - 10(exp -17) kg) particles using a 2-MV Van de Graaff accelerator. This machine has been operational for many years; both the machine and experimental area are currently being upgraded. Larger particles (10(exp -10) - 10(exp -14) kg) are accelerated using a more recently installed light gas gun. The status of all hardware (including experimental areas) is given, along with brief details of recent, current, and future projects making use of them.

Burchell, Mark J.↗

Reliability of Electronics for Cryogenic Space Applications Being Assessed

Many future NASA missions will require electronic parts and circuits that can operate reliably and efficiently in extreme temperature environments below typical device specification temperatures. These missions include the Mars Exploration Laboratory, the James Webb Space Telescope, the Europa Orbiter, surface rovers, and deep-space probes. In addition to NASA, the aerospace and commercial sectors require cryogenic electronics in applications that include advanced satellites, military hardware, medical instrumentation, magnetic levitation, superconducting energy management and distribution, particle confinement and acceleration, and arctic missions. Besides surviving hostile space environments, electronics capable of low-temperature operation would enhance circuit performance, improve system reliability, extend lifetime, and reduce development and launch costs. In addition, cryogenic electronics are expected to result in more efficient systems than those at room temperature.

Patterson, Richard L.↗

Impact Report: Quantum Systems Accelerator

The Quantum Systems Accelerator (QSA) is a U.S. National Quantum Information Science Research Center established in August 2020 and funded by the Department of Energy (DOE) Office of Science. QSA is composed of 15 partner institutions— universities and national laboratories—bringing together pioneers of many of today’s unique quantum information science (QIS) and engineering capabilities. Led by Lawrence Berkeley National Laboratory (Berkeley Lab), with Sandia National Laboratories (Sandia Labs) as the lead partner, 250+ QSA researchers are catalyzing U.S. leadership in a fast-growing field that seeks solutions to the Nation’s and the world’s most pressing problems by harnessing the laws of quantum mechanics.

97 MATHEMATICS AND COMPUTING↗

High-Performance Computing Optimization for Aladyn – Adaptive Neural Network Molecular Dynamics Mini-Application

This report provides a description and performance evaluation of the optimization techniques for high performance computing (HPC) implementation of the open source Computational Materials mini-application Aladyn (https://github.com/nasa/aladyn). Aladyn is a basic molecular dynamics code written in FORTRAN 2003, which is designed to demonstrate the use of adaptive neural networks (ANNs) in atomistic simulations. The role of ANNs is to efficiently reproduce the very complex energy landscape resulting from the atomic interactions in materials with the accuracy of the more expensive quantum mechanics-based calculations. The ANN is trained on a large set of atomic structures calculated using the density functional theory (DFT) method. While achieving orders of magnitude faster computational performance than DFT, the ANN-based approach was still very computationally demanding compared to the conventional approach of using empirically fitted energy functions. After its initial development, Aladyn was evaluated and optimized by experts at the NASA Advanced Supercomputing (NAS) division to exploit modern supercomputer architectures. The code has been optimized for execution on multicore central processing units (CPUs), including Intel® Skylake microarchitecture, and on graphic accelerators, such as Nvidia® V100 graphic processing units (GPUs), using Open Multi-Processing (OpenMP) and Open Accelerators (OpenACC) programming interfaces. The optimization achieved a speedup of 4.7 times the baseline version on CPU performance and an additional 2.4 times on CPU+GPU performance. Atomistic computer simulations are a fundamental tool in materials research to model material properties form physics-based first principles. Atomic interaction, governed by Quantum Mechanics (QM) require sophisticated and highly computationally demanding mathematical models to calculate [1]. Classical methods use approximate functional forms, empirically fitted through a set of variable parameters to emulate atomic energies as direct functions of atomic coordinates [2]. While empirical potentials are computationally much simpler, allowing simulations of large-scale systems of up to a trillion (1012) atoms [3], they are substantially less accurate compared to quantum calculations and applicable only to very specific atomic configurations or predefined crystallographic phases. A recently suggested approach is to use heuristic machine learning methods [4], such as those based on Adaptive Neural Networks (ANNs) to predict atomic energies, after being trained on a sufficiently large database of QM-calculated structures [5,6]. This approach reduces significantly the computational complexity, allowing for simulations of orders of magnitude larger systems compared to QM-based methods without compromising accuracy. Still, compared to classical methods using empirical energy functions, ANN methods remain two- to three orders of magnitude more computationally demanding. Hence, the computational cost of simulations, together with the need for extensive training of ANNs, still makes the practical implementation of ANN-based methods quite challenging. The purpose of the Aladyn mini-application software [7], available as open source at https://github.com/nasa/aladyn, is to be a testbed for exploring possible optimization strategies to develop highly scalable parallel algorithms for ANN-based atomistic simulations. Aladyn is aimed at utilizing the architecture of the high-end modern highperformance computing (HPC) hardware based on multicore central processing units (CPUs) equipped with graphic processing unit (GPU) accelerators. Specifically, the goal is to optimize the performance on a single HPC compute node, before implementing scaling to multi-node parallelization using message passing interface (MPI). At the same time, the open source code of Aladyn can serve as a training model for students and professors in academia.

Yamakov, Vesselin I.↗

EJFAT Scientific Perspective

Presented new computing model to the test by deploying the EJFAT system alongside a data-stream processing framework running the production-level CLAS12 event reconstruction application. In this experiment, a continuous stream of CLAS12 Level-1 identified events was processed in real-time using the EJFAT load balancer, distributing the workload across 90 computing nodes located across the U.S. This marks the first-ever large-scale, real-time distributed data stream processing experiment, demonstrating that scientific data-streaming pipelines can efficiently scale across four dimensions, thanks to EJFAT’s advanced hardware and software capabilities.

Gyurjyan, Vardan [Thomas Jefferson National Accele↗

Measuring Q₀ in LCLS-II Cryomodules Using Helium Liquid Level

The nitrogen-doped cavities used in the Linac Coherent Light Source II (LCLS-II) cryomodules have shown an unprecedented high Q₀ in vertical and cryomodule testing compared with cavities prepared with standard methods. While demonstration of high Q₀ in the test stand has been achieved, maintaining that performance in the linac is critical to the success of LCLS-II and future accelerator projects. The LCLS-II cryomodules required a novel method of measuring Q₀, due to hardware incompatibilities with existing procedures. Initially developed at Jefferson Lab during cryomodule acceptance testing before being used in the tunnel at SLAC, we use helium liquid level data to estimate the heat generated by cavities. We first establish the relationship between the rate of helium evaporation from known heat loads using electric heaters, and then use that relationship to determine heat from an RF load. Here we present the full procedure along with the development process, lessons learned, and reproducibility while demonstrating for the first time that world record Q₀ can be maintained within the real accelerator environment.

43 PARTICLE ACCELERATORS↗

Disentangling Beam Losses in The Fermilab Main Injector Enclosure Using Real-Time Edge AI

The Fermilab Main Injector enclosure houses two accelerators, the Main Injector and Recycler Ring. During normal operation, high intensity proton beams exist simultaneously in both. The two accelerators share the same beam loss monitors (BLM) and monitoring system. Deciphering the origin of any of the 260 BLM readings is often difficult. The (Accelerator) Real-time Edge AI for Distributed Systems project, or READS, has developed an AI/ML model, and implemented it on fast FPGA hardware, that disentangles mixed beam losses and attributes probabilities to each BLM as to which machine(s) the loss originated from in real-time. The model inferences are then streamed to the Fermilab accelerator controls network (ACNET) where they are available for operators and experts alike to aid in tuning the machines.

43 PARTICLE ACCELERATORS↗

Captan+X Data Converter Integration

Fermi National Accelerator Laboratory's CAPTAN (Compact And Programmable daTa Acquisition Node) series provides a flexible hardware platform for data acquisition across a range of experiments and facilities. The latest iteration, CAPTAN+X, is built around a Kintex-7 FPGA supporting four FPGA Mezzanine Card (FMC) connections. As part of a broader laboratory effort to bring facility systems under a Model-Based Systems Engineering (MBSE) framework, CAPTAN+X is one of several systems slated to be incorporated into this modeling environment in the near term. A necessary step toward that goal is incorporating the platform's core functionality, which centers on integration with the LXD31K4 FMC, a data converter module combining dual AD9652 analog-to-digital converters and dual AD9142A digital-to-analog converters. Achieving compatibility required resolving pin-mapping conflicts between the LXD31K4's High Pin Count connector and the CAPTAN+X's available pin types, adapting a Board Support Project originally written for an UltraScale-class evaluation board to the Kintex-7 architecture, replacing incompatible primitives, restructuring clock distribution, and manually configuring chip initialization in place of an unsupported soft-processor-based approach. Functional verification of the ADC and DAC channels, followed by closed-loop testing combining both converters with real-time filtering, confirmed correct operation of the integrated system. These results establish a working hardware and firmware baseline for the CAPTAN+X platform, positioning it for future inclusion in the laboratory's growing MBSE modeling effort.

Espinoza, David [Illinois U., Urbana (main)]↗