SEARCH · Engineering Papers

Results for “circuit faults”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 361 records · Page 20

All sources NASA NTRS DOE OSTI

DOE OSTI2024

Realistic Cost to Execute Practical Quantum Circuits using Direct Clifford+T Lattice Surgery Compilation

We report a resource estimation pipeline that explicitly compiles quantum circuits expressed using the Clifford+T gate set into a surface code lattice surgery instruction set. The cadence of magic state requests from the compiled circuit enables the optimization of magic state distillation and storage requirements in a post-hoc analysis. To compile logical circuits into lattice surgery operations, we build upon the open-source Lattice Surgery Compiler. The revised compiler operates in two stages: the first translates logical gates into an abstract, layout-independent instruction set; the second compiles these into local lattice surgery instructions that are allocated to hardware tiles according to a specified resource layout. The second stage retains logical parallelism while avoiding resource contention in the fault-tolerant layer, aiding realism. Additionally, users can specify dedicated tiles at which magic states are replenished, enabling resource costs from the logical computation to be considered independently from magic state distillation and storage. We demonstrate the applicability of our pipeline to large practical quantum circuits by providing resource estimates for the ground state estimation of molecules. Finally, we find that variable magic state consumption rates in real circuits can cause the resource costs of magic state storage to dominate unless production is varied to suit.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS2013

An Efficient Model-based Diagnosis Engine for Hybrid Systems Using Structural Model Decomposition

Complex hybrid systems are present in a large range of engineering applications, like mechanical systems, electrical circuits, or embedded computation systems. The behavior of these systems is made up of continuous and discrete event dynamics that increase the difficulties for accurate and timely online fault diagnosis. The Hybrid Diagnosis Engine (HyDE) offers flexibility to the diagnosis application designer to choose the modeling paradigm and the reasoning algorithms. The HyDE architecture supports the use of multiple modeling paradigms at the component and system level. However, HyDE faces some problems regarding performance in terms of complexity and time. Our focus in this paper is on developing efficient model-based methodologies for online fault diagnosis in complex hybrid systems. To do this, we propose a diagnosis framework where structural model decomposition is integrated within the HyDE diagnosis framework to reduce the computational complexity associated with the fault diagnosis of hybrid systems. As a case study, we apply our approach to a diagnostic testbed, the Advanced Diagnostics and Prognostics Testbed (ADAPT), using real data.

Structural Decomposition↗

DOE OSTI2021

Variational quantum algorithms

Applications such as simulating complicated quantum systems or solving large-scale linear algebra problems are very challenging for classical computers, owing to the extremely high computational cost. Quantum computers promise a solution, although fault-tolerant quantum computers will probably not be available in the near future. Current quantum devices have serious constraints, including limited numbers of qubits and noise processes that limit circuit depth. Variational quantum algorithms (VQAs), which use a classical optimizer to train a parameterized quantum circuit, have emerged as a leading strategy to address these constraints. VQAs have now been proposed for essentially all applications that researchers have envisaged for quantum computers, and they appear to be the best hope for obtaining quantum advantage. Nevertheless, challenges remain, including the trainability, accuracy and efficiency of VQAs. Here we overview the field of VQAs, discuss strategies to overcome their challenges and finally, we highlight the exciting prospects for using them to obtain quantum advantage.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2020

Fixed-point quantum circuits for quantum field theories

Renormalization group ideas and effective operators are introduced to efficiently prepare ground states of massive lattice field theories on digital quantum devices. This is accomplished with a systematic approximation through localized unitaries that removes an exponentially costly barrier in the spatial volume of the quantum simulation. With these methods, classically computed ground states in a spatial volume L, containing a few Compton wavelengths, can be used to determine operators for preparing the ground state toward the thermodynamic limit with a precision improving as e –mL on beyond-classical quantum registers. Here, due to the exponential spatial decay of correlations in massive theories and the double exponential suppression of digitization artifacts in the number of qubits representing the scalar field, the derived fixed-point quantum circuits are expected to be relevant for simulations of quantum field theories throughout the evolution from small-scale near-term quantum devices to large-scale fault-tolerant quantum computers.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

DOE OSTI2025

QECC-Synth: A Layout Synthesizer for Quantum Error Correction Codes on Sparse Architectures

Quantum Error Correction (QEC) codes are essential for achieving fault-tolerant quantum computing (FTQC). However, their implementation faces significant challenges due to disparity between required dense qubit connectivity and sparse hardware architectures. Current approaches often either underutilize QEC circuit features or focus on manual designs tailored to specific codes and architectures, limiting their capability and generality. In response, we introduce QECC-Synth, an automated compiler for QEC code implementation that addresses these challenges. We leverage the ancilla bridge technique tailored to the requirements of QEC circuits and introduces a systematic classification of its design space flexibilities. We then formalize this problem using the MaxSAT framework to optimize these flexibilities. Evaluation shows that our method significantly outperforms existing methods while demonstrating broader applicability across diverse QEC codes and hardware architectures.

Yin, Keyi [University of California, San Diego]↗

NASA NTRS1993

Advanced electric motor technology flux mapping

Design of electric motors which fulfill the needs of Thrust Vector Control (TVC) actuators used in large rocket propelled launch vehicles is covered. To accomplish this end the methodology of design is laid out in some detail. In addition a point design of a motor to fulfill the requirements of a certain actuator specified by MSFC is accomplished and reported upon. In the course of this design great stress has been placed on ridding the actuator of internally generated heat. To conduct the heat out of the motor use is made of the unique properties of the in house MSFC designed driving electronics. This property is that as along as they are operated in a quasi-linear mode the electronics nullify the effects of armature inductance as far as the phase of the armature current versus the rotor position is concerned. Actually the additional inductance due to the extended end turns in this design is of benefit because in the shorted armature failure mode the armature current in the fault (caused by the rotor flux sweeping past the armature) is diminished at a given rotor speed when compared to a more conventional motor with lower inductance. The magnetic circuit is analyzed using electromagnetic finite element methods.

Doane, George B., III↗

NASA NTRS1983

A basic design fault in ceramic flat packs

Recent moisture resistance tests of various multilayer top brazed ceramic flat packs and leaded and unleaded chip carriers has revealed a serious design defect. These packages, which utilize a tungsten interconnect system, in the presence of high humidity, suffer a galvanic corrosion which anodically consumes the tungsten. This process can continue until the package suffers an open circuit. The test results indicate that the lead plating system does not adequately seal off the interface area where the tungsten stripe egresses from the inside of the package. Leaded and leadless chip carrier packages were also subjected to the moisture resistance test. The familiar red and green corrosion products were visible after the test was completed. Careful sectioning of the chip carriers has revealed that the tungsten interconnect stripe instead of exiting under the castellations, exits at the top of the castellation and is thus vulnerable to the attack of moisture. These basic design faults severely impact the reliability of these packages.

Drotman, B.↗

NASA NTRS1991

Test and evaluation of the generalized gate logic system simulator

The results of the initial testing of the Generalized Gate Level Logic Simulator (GGLOSS) are discussed. The simulator is a special purpose fault simulator designed to assist in the analysis of the effects of random hardware failures on fault tolerant digital computer systems. The testing of the simulator covers two main areas. First, the simulation results are compared with data obtained by monitoring the behavior of hardware. The circuit used for these comparisons is an incomplete microprocessor design based upon the MIL-STD-1750A Instruction Set Architecture. In the second area of testing, current simulation results are compared with experimental data obtained using precursors of the current tool. In each case, a portion of the earlier experiment is confirmed. The new results are then viewed from a different perspective in order to evaluate the usefulness of this simulation strategy.

Miner, Paul S.↗

NASA NTRS1978

Shock Prevention

The electrician pictured is installing a General Electric Ground Fault Interrupter (GFI), a device which provides protection against electrical shock in the home or in industrial facilities. Shocks due to defective wiring in home appliances or other electrical equipment can cause severe burns, even death. As a result, the National Electrical Code now requires GFIs in all new homes constructed. This particular type of GFI employs a sensing element which derives from technology acquired in space projects by SCI Systems, Inc., Huntsville, Alabama, producer of sensors for GE and other manufacturers of GFI equipment. The sensor is based on the company's experience in developing miniaturized circuitry for space telemetry and other spacecraft electrical systems; this experience enabled SCI to package interruptor circuitry in the extremely limited space available and to produce sensory devices at practicable cost. The tiny sensor measures the strength of the electrical current and detects current differentials that indicate a fault in the functioning of an electrical system. The sensing element then triggers a signal to a disconnect mechanism in the GFI, which cuts off the current in the faulty circuit.

Source record↗

DOE OSTI2022

A Universal Refrigerant Charge Fault Detection and Diagnostics Method Based on Pump Down Operation

The performance of the heat pump system varies greatly depending on the refrigerant charge amount. Improving the refrigerant charge fault detection and diagnostics (FDD) method of vapor compression systems have the potential for increasing energy efficiency and reducing service cost. Previous studies to predict refrigerant charge amount are mostly empirical methods which require significant amount of experimental data for high accuracy. The primary goal of this research is to develop a universal charge fault detection method which requires only a few experimental data with high prediction accuracy.Currently, pump down operations are typical practices by HVAC technicians when they need to open the refrigerant circuit to make a repairment. In addition, compressors have a built-in low-pressure cut-off protection function, and the compressor performance maps are commonly available from manufacturers. The proposed method innovatively utilizes the typical pump down operation, the compressor low-pressure cut-off protection, and the compressor performance map. It does not require any geometry information of heat exchangers, refrigerant lines, or charge buffers.The new charge prediction method is firstly formulated through theoretical analysis, then verified and calibrated by a quasi-steady-state simulation of the pump down process for a residential heat pump system. The quasi steady-state simulation uses an HVAC system simulation framework driven by DOE/ORNL Heat Pump Design Model (HPDM). Preliminary experiment validations with heat pump refrigerant leakage tests demonstrate the deviation of the proposed charge prediction method compared with measurement is within 8%. This technology makes refrigerant charge amount available at the technician’s fingertips and leads to shorter maintenance time and fewer site visits.

Li, Zhenning↗

DOE OSTI2026

Preparing Fermions via Classical Sampling and Linear Combinations of Unitaries

We present an extension of the Evolving density matrices on Qubits (E$ρ$OQ) framework that enables efficient fault-tolerant preparation of fermionic quantum states. The original method circumvents state preparation by stochastic sampling, but faces a sign problem in fermionic systems leading to a large number of circuits necessary. We resolve this by combining classical stochastic sampling with a linear combination of unitaries method that avoids the exponential circuit scaling that plagued naïve implementations. The resulting algorithm requires $\mathcal{O}(M^2)$$R_Z$ rotations for circuit preparation, where $M$ is the number of retained basis states. We validate the method for ground and excited states in the Thirring model, including by computing two-point correlation functions relevant to scattering. In this model for fixed accuracy $\varepsilon$, $M$ is found to scale empirically as $M \propto \frac{1}{mg}\log(1/g)\log(1/m)$.

Gustafson, Erik J. [RIACS, Mtn. View] (ORCID:00000↗

DOE OSTI2023

Determining circuit model parameters from operation data for PV system degradation analysis: $\mathrm{PVPRO}$

Physics-based circuit parameters like series and shunt resistance are essential to provide insights into the degradation status of photovoltaic (PV) arrays. However, calculating these parameters typically requires a full current-voltage characteristic (I-V curve), the acquisition of which involves specific measurement devices and costly methods. Thus, I-V curves of the PV system level are often not available. Here this paper proposes a methodology (PVPRO) to estimate these I-V curve parameters using only operation (string-level DC voltage and current) and weather data (irradiance and temperature). PVPRO first performs multi-stage data pre-processing to remove noisy data. Next, the time-series DC data are used to fit an equivalent circuit single-diode model (SDM) to estimate the circuit parameters by minimizing the differences between the measured and estimated values. In this way, the time evolutions of the SDM parameters are obtained. We evaluate PVPRO on synthetic datasets and find an excellent estimation of both SDM and the key I-V parameters (e.g., open-circuit voltage, short-circuit current, maximum power, etc.) with an average relative error of 0.55%. The performance, especially the extracted degradation rate of parameters, is robust to various measurement noises and the presence of faults. In addition, PVPRO is applied to a 271 kW PV field system. The relative error between the real and estimated operation voltage and current is less than 1%, suggesting that degradation trends are well captured. PVPRO represents a promising open-source tool to extract the time-series degradation trends of key PV parameters from routine operation data.

14 SOLAR ENERGY↗

NASA NTRS2009

Lightning Pin Injection Testing on MOSFETS

Lightning transients were pin-injected into metal-oxide-semiconductor field-effect transistors (MOSFETs) to induce fault modes. This report documents the test process and results, and provides a basis for subsequent lightning tests. MOSFETs may be present in DC-DC power supplies and electromechanical actuator circuits that may be used on board aircraft. Results show that unprotected MOSFET Gates are susceptible to failure, even when installed in systems in well-shielded and partial-shielded locations. MOSFET Drains and Sources are significantly less susceptible. Device impedance decreased (current increased) after every failure. Such a failure mode may lead to cascading failures, as the damaged MOSFET may allow excessive current to flow through other circuitry. Preliminary assessments on a MOSFET subjected to 20-stroke pin-injection testing demonstrate that Breakdown Voltage, Leakage Current and Threshold Voltage characteristics show damage, while the device continues to meet manufacturer performance specifications. The purpose of this research is to develop validated tools, technologies, and techniques for automated detection, diagnosis and prognosis that enable mitigation of adverse events during flight, such as from lightning transients; and to understand the interplay between lightning-induced surges and aging (i.e. humidity, vibration thermal stress, etc.) on component degradation.

Ely, Jay J.↗

NASA NTRS2011

Integrated Software Health Management for Aircraft GN and C

Modern aircraft rely heavily on dependable operation of many safety-critical software components. Despite careful design, verification and validation (V&V), on-board software can fail with disastrous consequences if it encounters problematic software/hardware interaction or must operate in an unexpected environment. We are using a Bayesian approach to monitor the software and its behavior during operation and provide up-to-date information about the health of the software and its components. The powerful reasoning mechanism provided by our model-based Bayesian approach makes reliable diagnosis of the root causes possible and minimizes the number of false alarms. Compilation of the Bayesian model into compact arithmetic circuits makes SWHM feasible even on platforms with limited CPU power. We show initial results of SWHM on a small simulator of an embedded aircraft software system, where software and sensor faults can be injected.

Schumann, Johann↗

DOE OSTI2023

Distributed Ledger Technology for Fault Tolerant Distribution Grid Operations

This paper explores the potential of distributed ledger technology (DLT) to improve fault-tolerant grid operations by leveraging its core features as an immutable, decentralized ledger, a distributed, consensus-based agreement process, and a distributed state-replication engine. Distribution power systems deliver electricity to millions of customers; however, they are susceptible to various threats that can result in customer interruptions. These include faults caused by adverse weather conditions, natural disasters, vegetation growth, equipment failure, and malicious attacks. To minimize the effects of these faults, fault-handling approaches rely on network knowledge to isolate affected areas and reconnect unaffected areas, reducing the number of affected customers while maintaining safety. Here, we present a trusted data-sharing architecture that enables independent, distributed actors to reconstruct the pre-fault system state by enabling distributed resources to make appropriate decisions with limited network/system information. Although the process requires some data sharing between switch-delimited areas, the approach limits the amount of private information shared, preserving customers' privacy and business-sensitive information. We include three use cases that form a foundation for third parties to develop functional solutions that can eventually be deployed in the field. The gross error detection method used within switch-delimited areas can identify sensor errors and accurately detect circuit breaker states. The evaluation of possible reconnection while preserving data ownership resulted in a voltage magnitude difference smaller than 0.001% from the OpenDSS power flow solution that has full system knowledge, which is below the expected power flow tolerance. The approach offers a promising opportunity for improving fault-tolerant distribution grid operations.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2020

Optimized Highly Efficient SSCB Using Organic Substrate Packaging for Electric Vehicle Applications

Solid State Circuit Breakers (SSCBs) are an attractive protection solution for their arcless current interruption and fast actuation speeds over mechanical breakers. This paper proposes a Bidirectional SSCB (BSSCB) with a thermally defined and digitally controlled current time profile for fault protection in EV and other low-voltage DC systems. The paper proposes an organic packaging approach utilizing flex circuitry to develop a reliable, cost-effective power module for BSSCBs. The paper studies transient heat transfer in the power modules using finite element analysis (FEA). An RC themal ladder network is extracted to define a fusing curve. To demonstrate and verify the design, a 1kV/50 A SiC MOSFET BSSCB prototype is fabricated and tested, having a power density of 60 W/cm3 and 4x reduction in form factor over presently researched breakers. Also, given are results for 750 V/150 A operation showing interruption in 2.4 μs.

organic power packaging↗

DOE OSTI2025

Randomized Adiabatic Quantum Linear Solver Algorithm with Optimal Complexity Scaling and Detailed Running Costs

Solving linear systems of equations is a fundamental problem with a wide variety of applications across many fields of science, and there is increasing effort to develop quantum linear solver algorithms. Subaşı et al. [Phys. Rev. Lett. 122, 060504 (2019)] proposed a randomized algorithm inspired by adiabatic quantum computing, based on a sequence of random Hamiltonian simulation steps, with suboptimal scaling in the condition number 𝜅 of the linear system and the target error 𝜖. Here we go beyond these results in several ways. Firstly, using filtering [Lin and Tong, Quantum 4, 361 (2020)] and Poissonization techniques [Cunningham and Roland, ArXiv:2406.03972 (2024)], the algorithm complexity is improved to the optimal scaling 𝑂⁡(𝜅⁢log (1/𝜖))—an exponential improvement in 𝜖, and a shaving of a log 𝜅 scaling factor in 𝜅. Secondly, the algorithm is further modified to achieve constant factor improvements, which are vital as we progress towards hardware implementations on fault-tolerant devices. We introduce a cheaper randomized walk operator method replacing Hamiltonian simulation—which also removes the need for potentially challenging classical precomputations; randomized routines are sampled over optimized random variables; circuit constructions are improved. We obtain a closed formula rigorously upper bounding the expected number of times one needs to apply a block-encoding of the linear system matrix to output a quantum state encoding the solution to the linear system. The upper bound is 837⁢𝜅 at 𝜖 = 10 −10 for Hermitian matrices.

97 MATHEMATICS AND COMPUTING↗

NASA NTRS1984

Self-Checking Memory Interface

Memory-interface integrated circuit not only detects errors in data from other circuits but also detects errors within itself. Memory-interface chip encodes 16-bit words with Hamming code for single-error correction or double-error detection. Chip used in fault-tolerant computers under development by NASA.

Sievers, M. W.↗