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A simple technique to estimate the channel temperature of a generic AlGaN/GaN HEMTs on SiC or Sapphire, while incorporating temperature dependence of the thermal conductivity is presented. The procedure is validated b y comparing it's predictions with the experimentally measured temperatures in devices presented in three recently published articles.
Advances in wurtzite nitride ferroelectrics of Al 1-x M x N ( M = Sc or B) have led to novel capabilities, which must be integrated into existing fabrication processes. In the case of electronics operating > 200°C, a movement toward SiC-based platforms enables better performance over conventional Si, primarily due to the higher bandgap and lower intrinsic carrier concentration of SiC. Hence, the challenge is to develop a deposition process to integrate Al 1-x M x M x N ferroelectrics with elevated temperature-compatible materials for high temperature electronics such as the non-volatile memory component. We demonstrate epitaxial Al M N/Mo/SiC heterostructures, which provides both the crystalline and surface features that promote high-quality ferroelectric nitride film growth. Omega scans of the Mo (110) reflection exhibit a full width at half max of < 0.02° (40 arc sec) and the (0002) peak of the subsequently grown nitride film had a value of 1.1° for 160 nm thick Al 0.7 Sc 0.3 N and 1.3° for 400 nm thick Al 0.94 B 0.06 N. The crystallographic relationships found between the Al M N, Mo, and SiC layers indicate an advancement in sputter deposition of epitaxial films. Ferroelectric switching is also shown at 400 °C in both samples via polarization-electric field hysteresis and pulsed measurements, which exhibited P r values >100 μC cm -2 and E c between 3 and 4 M V cm -1 , despite a large presence of oxygen in both Al M N films ranging between 4 and 5 at.%, revealed by compositional analysis. This study demonstrates the process for synthesizing high-crystal quality ferroelectric nitride films, which can be used in extremely high temperature applications.
Porous silicon carbide is fabricated according to techniques which result in a significant portion of nanocrystallites within the material in a sub 10 nanometer regime. There is described techniques for passivating porous silicon carbide which result in the fabrication of optoelectronic devices which exhibit brighter blue luminescence and exhibit improved qualities. Based on certain of the techniques described porous silicon carbide is used as a sacrificial layer for the patterning of silicon carbide. Porous silicon carbide is then removed from the bulk substrate by oxidation and other methods. The techniques described employ a two-step process which is used to pattern bulk silicon carbide where selected areas of the wafer are then made porous and then the porous layer is subsequently removed. The process to form porous silicon carbide exhibits dopant selectivity and a two-step etching procedure is implemented for silicon carbide multilayers.
Arkansas Power Electronics International (APEI), Inc., is developing a high-efficiency, radiation-hardened 3.8-kW SiC power supply for the PPU of Hall effect thrusters. This project specifically targets the design of a PPU for the high-voltage Hall accelerator (HiVHAC) thruster, with target specifications of 80- to 160-V input, 200- to 700-V/5A output, efficiency greater than 96 percent, and peak power density in excess of 2.5 kW/kg. The PPU under development uses SiC junction field-effect transistor power switches, components that APEI, Inc., has irradiated under total ionizing dose conditions to greater than 3 MRad with little to no change in device performance.
Abstract Establishing connections between material impurities and charge transport properties in emerging electronic and quantum materials, such as wide‐bandgap semiconductors, demands new diagnostic methods tailored to these unique systems. Many such materials host optically‐active defect centers which offer a powerful in situ characterization system, but one that typically relies on the weak spin‐electric field coupling to measure electronic phenomena. In this work, charge‐state sensitive optical microscopy is combined with photoelectric detection of an array of nitrogen‐vacancy (NV) centers to directly image the flow of charge carriers inside a diamond optoelectronic device, in 3D and with temporal resolution. Optical control is used to change the charge state of background impurities inside the diamond on‐demand, resulting in drastically different current flow such as filamentary channels nucleating from specific, defective regions of the device. Conducting channels that control carrier flow, key steps toward optically reconfigurable, wide‐bandgap optoelectronics are then engineered using light. This work might be extended to probe other wide‐bandgap semiconductors (SiC, GaN) relevant to present and emerging electronic and quantum technologies.
Long lived memory would transform Venus landers & missions. Venus durable memory demonstrated in earlier HOTTech with impractically high power and low bit capacity. This project seeks to develop and demonstrate the world’s first Venus-durable low power memory device (Non-Volatile Random Access Memory (NVRAM) to enhance extended Venus surface missions.
The goal of this project is to develop packaging technologies for making high-temperature, high-density, and low-profile wide-bandgap (WBG) power electronics modules for electric drives. These modules are aimed at enabling the DOE’s University Consortium to reach its 2025 inverter targets of ≥ 100 kW/L and ≤ 2.7 $/kW. The specific objectives are to: design and fabricate SiC half-bridge power modules with double-sided cooling and parasitic inductances < 5 nH, heat flux density > 400 W/cm 2 , and working junction temperature of 200 o C; design, fabricate, and deliver a gate driver with double-sided cooled modules for the construction of a 100 kW/L inverter at Oak Ridge National Lab; and design and prototype intelligent gate drivers with integrated current sensor and a low-profile DC-DC power supply with air-core transformer for testing power modules at 200 o C junction temperature. We followed an iterative technical approach of design, simulation, fabrication, and testing of various versions of modules, current sensors, and power supply. The state-of-the-art silicon carbide devices rated at 1.2 kV and 149 A were packaged by sintered-silver bonding on an aluminum nitride direct-bond-copper substrate for high thermal conductivity, high working temperature, and high joint reliability. Porous silver posts were used to interconnect the device’s source pads to the other direct-bond-copper substrate for low mechanical stresses, ease of manufacturing, and double-sided cooling. A current sensor based on package parasitic inductance was developed to measure switching current. A dynamic feedback scheme was developed to compensate the effect of parasitic resistance and temperature variation. A constant-current class-E dc-dc converter with air-core transformer was developed. Air-core transformer was used due to the unavailability of magnetic core at high temperatures. Gate driver and power supply were integrated with the double-side cooled, high temperature SiC power modules for testing the modules at 200 o C junction temperature. Double-pulse and continuous testing of the integrated technologies validated the design and fabrication of the three component technologies. Throughout the project, we overcame the challenge for design verification caused by low prototyping yield, which then helped train the graduate students, the future workforce, to learn the engineering know-how for low-cost manufacturing of reliable products. Below is a summary of the major accomplishments of this project: development of a prototyping process for fabricating double-side cooled (1200 V, 149 A) SiC phase-leg modules capable of working to 200 o C Tj; simulation and experimental verification of the improvement of thermo-mechanical reliability of the double-side cooled SiC phase-leg module by using rigid encapsulant; design and experimental validation of a current sensor based on package parasitic inductance and a compensation solution for eliminating the effect of parasitic resistance; design and experimental validation of a low-profile power supply with six-output air-core transformer for gate driver; functional demonstration of a SiC phase-leg module integrated with its gate driver, current sensor, and an air-core power supply at 200 o C Tj in a double-pulse switching test setup and Buck converter continuous test setup; successful completion of six PhD and two MS students who are or will work at Apple Inc., Tesla Inc., Wolfspeed Inc., Microchip Inc., Monolithic Power Systems Inc., and LG Magna Inc.
In recent years, there has been increasing interest in developing detectors which are sensitive to sub-GeV dark matter and low-energy events from coherent neutrino scattering. Due to carbon’s light atomic weight and its tendency to form crystals with high-energy, long-lived phonon modes, carbon-based crystals (including diamond and silicon carbide (SiC)) present themselves as natural target materials for scattering-based searches in this regime. Here, we present our preliminary results in adapting our TES-based detectors to these substrates, specifically 4-H SiC and polycrystalline diamond. We focus on our fabrication efforts, specifically tuning the transition temperature (T C ) of tungsten films sputtered on these materials, as well as our advancement toward fabricating and testing devices on these substrates.
Careful measurements of the power device characteristics are necessary to accurately estimate a power converter's losses and efficiency. The conventional double-pulse test (DPT) circuit is a well-known method to implement this laboratory characterization of power devices and power modules. However, the switching characteristics of a power device depend on the power electronics circuit in which it is connected as well as the power circuit's physical layout, in addition to the device's internal structure. Hence, the conventional DPT circuit configuration, which is tailored for a standard voltage-source inverter (VSI), is not well-suited for a current-source inverter (CSI). This paper demonstrates a previously-proposed CSI-based DPT measurement technique that is appropriate for normal CSI operation. The characteristics of SiC MOSFETs and series-connected SiC Schottky diodes used in a CSI are measured using this improved technique while taking temperature effects into account to yield more accurate loss predictions. The CSI losses, including the switching and conduction losses of SiC MOSFETs and SiC Schottky diodes, have been modeled using this approach. The total CSI losses and efficiency have been estimated based on the CSI DPT results and loss models.
The purpose of this testing was to obtain total ionizing dose (TID) information about custom-built research prototype silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) capable of prolonged operation in extremely high-temperature (500 degrees Centigrade) environments. The circuits included ring oscillators and operational amplifiers as well as individual n-channel JFETs. This technology is being considered for use in high temperature, high pressure applications such as Long-Lives Surface System Explorer (LLISSE). These devices were developed at NASA Glenn Research Center (GRC). Testing occurred from July 9th-July 13th, 2018.
This paper is focused on a transformer-isolated quadruple active bridge (QAB) dc-dc converter loaded by three full-bridge dc-ac inverters. The QAB functions as a "DC trans-former" (DCX) in the dc-to-three-phase ac module. The QAB outputs provide time-varying power at twice the line frequency, which presents challenges in maintaining zero voltage switching (ZVS) on the secondary sides during low-power portions of the line cycle. It is shown how ZVS can be achieved in a phase, even at zero-power transfer, using a relatively small circulating current provided by the magnetizing inductance of the high-frequency transformer. The approach is particularly effective in high-voltage applications using SiC MOSFETs, where reductions in switching loss outweigh additional conduction losses due to the circulating currents. A detailed analysis of ZVS switching waveforms at the zero power transfer is presented, including effects of nonlinear device capacitances. Analytical expressions are given for the optimal values of the magnetizing inductance and dead times of the QAB primary and secondary bridges. The approach is verified by experimental results on a 600 V, 4 kW prototype, demonstrating greater than 98.5% efficiency from 1 kW to 4 kW, with a peak efficiency of 99.0%. Compared to conventionally operated prototype, a 54% reduction in total loss is achieved at rated power.
Packaging innovations are needed for medium-voltage wide bandgap power semiconductor modules to enable their adaptation in grid applications. A unique challenge for packaging medium-voltage power modules is managing the trade-off between insulation demand and heat dissipation. The focus of this work was on developing a packaging innovation that improves the module heat dissipation and offers more flexibility to its insulation design. Two strategies were explored for the packaging of an 8-kV SiC diode rectifier module:(1) double-side cooling and (2) sintered-silver bonding. Double-side cooling was realized by using short metal posts rather than long and thin wire bonds for device interconnection, forming a low-profile package with devices sandwiched between two insulated metal substrates. Sintered-silver bonding enabled the devices to function reliably at over 250 °C. Simulations of the packaged module showed a low interconnect inductance of 2.67 nH and a 50% less heat transfer coefficient required to cool the chips. Prototypes of the module were fabricated, and preliminary electrical testing results validated the package design.
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Paralleled dies in a power module could have instability issues during high current switching transients. Here, the instability is caused by the differential-mode oscillation among paralleled MOSFETs. Conventional analyses of paralleled MOSFETs’ stability are normally limited to a single operating point, which ignores the influences of the switching trajectory and nonlinear device parameters on stability. This article reveals that the switching trajectory can significantly influence parallel stability. The analysis is improved by solving eigenvalues of state-space modeling system matrices of all operating points that the switching trajectory goes through considering nonlinear device parameters. Higher voltage and current stresses result in greater real parts of complex eigenvalues, which explains why the paralleled MOSFETs are more unstable with higher voltage and current stresses. To improve stability in solid-state circuit breaker applications, we propose a method to manipulate the switching trajectory to avoid the unstable region where the conventional hard switching trajectory normally goes through. Experimental results show that the turn- off current capability can be increased from ~five times of rated current with the gate oscillation using the conventional turn- off trajectory to ~ten times of rated current without the gate oscillation using the optimal turn- off trajectory.
In this paper, an automated controller for an integrated, reconfigurable dc-dc converter for plugin electric vehicles (EVs) is presented. The integrated converter combines both an interleaved boost converter and dual active bridge (DAB) converter, sharing magnetics and switching devices. The converter switches between operating modes using the existing battery management system (BMS) contactors. The integrated converter operates in isolated DAB mode during battery charging operation. During traction operation, the integrated converter is operated in interleaved boost mode for heavy load and DAB mode during light load, high voltage operation. An online transition algorithm is used to transition from interleaved boost mode to DAB mode with minimal bus distortion. The automated controller selects the operating mode and inverter bus voltage at different torque-speed conditions to get maximum overall traction drive efficiency. An experimental prototype of the integrated converter demonstrates the automated controller functionality.
Wide bandgap devices are key enablers for high power density traction inverters. A highly integrated wide bandgap (WBG) power module enables higher temperature operation, higher inverter efficiency and overall smaller die area with the same power delivery. However, it requires careful design of the power module to take advantage of all the superior material properties that silicon carbide (SiC) provides over conventional silicon (Si) Insulated Gate Bipolar Transistor (IGBT) based design. This project developed an efficient and densely packed SiC power module for an automotive traction inverter application. Extensive study was performed to select the best performing SiC die considering a wide range of temperature variation, suitability to integrate into target packaging, robust body diode performance and overall high electrical efficiency. Multiple design ideas were explored to achieve lower stray inductance for both power loop and signal loop, uniform current distribution, compact form factor, and very high thermal performance. The final power module package includes all six inverter switches in the same module (six-pack) with die sintered at both bottom and top surfaces utilizing high performance substrate to achieve high electrical and thermal performance. Two power module variants were developed using 900 V and 1200 V devices for operating at two different high voltage levels (> 600 V HV battery). Both power modules were comprehensively characterized, and high efficiency operation of the inverter was confirmed through analysis. Finally, a complete functional inverter was built with the 1200V power modules using other essential components (HV capacitors, gate driver board, controller board, current sensor, connectors etc.) and tested using GM’s standard test procedure. There are several challenges associated with adopting WBG devices for high voltage operation. In order to assess and mitigate those challenges, GM and subrecipients of this project have conducted multiple detailed studies. This includes phase current reconstruction using integrated Rogowski coil, device junction temperature estimation using on-state gate resistance, modeling and testing the effect of high voltage and fast switching on motor insulation and bearings, partial discharge inception voltage measurement under different environmental conditions. Findings of all these studies are summarized in this report.
Abstract This paper describes a new method for direct measurement and evaluation of the inhomogeneous electrostatic vector field with translational symmetry in electro-optic materials exhibiting the Pockels effect. It is based on the evaluation of maximum transmittance of low intensity light passing through a sample under a voltage bias. Here, the sample is located between rotating crossed polarizers, and camera images are obtained at each point to determine the electric field. The evaluation procedure is demonstrated using data acquired on a CdZnTeSe quasi-hemispheric semiconductor gamma-ray detector. In addition to CdTe-related compounds, the method can be used for various other materials showing $$\overline{4}3m$$ 4 ¯ 3 m symmetry such as GaAs, CdTe, GaP, 3C-SiC, and ZnS. Furthermore, it can be generalized to other crystalline materials showing the Pockels effect. The method can be used to probe the space charge and the electric field in several kinds of electronic components and devices, as well as provide useful data on the role of defects, contact configurations and other surface and bulk inhomogeneities in the material that can affect the distribution of the internal electric field.
We have been investigating the effect of screw dislocation and other structural defects on the electrical properties of SiC. SiC is a wide-bandgap semiconductor that is currently received much attention due to its favorable high temperature behavior and high electric field breakdown strength. Unfortunately, the current state-of-the-art crystal growth and device processing methods produce material with high defect densities, resulting in a limited commercial viability