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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 361 records · Page 20
All sourcesNASA NTRSDOE OSTI
NASA NTRS2005

Variable electronic shutter in CMOS imager with improved anti smearing techniques

A leakage compensated snapshot imager provides a number of different aspects to prevent smear and other problems in a snapshot imager. The area where the imager is formed may be biased in a way that prevents photo carriers including electrons and holes from reaching a storage area. In addition, a number of different aspects may improve the efficiency. The capacitance per unit area of the storage area may be one, two or more orders of magnitude greater than the capacitance per-unit area of the photodiode. In addition, a ratio between photodiode capacitance and storage area capacitance is maintained larger than 0.7.

Pain, Bedabrata↗
NASA NTRS2004

High-speed on-chip windowed centroiding using photodiode-based CMOS imager

A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

Pain, Bedabrata↗
NASA NTRS1995

Method for characterizing the upset response of CMOS circuits using alpha-particle sensitive test circuits

A method for predicting the SEU susceptibility of a standard-cell D-latch using an alpha-particle sensitive SRAM, SPICE critical charge simulation results, and alpha-particle interaction physics. A technique utilizing test structures to quickly and inexpensively characterize the SEU sensitivity of standard cell latches intended for use in a space environment. This bench-level approach utilizes alpha particles to induce upsets in a low LET sensitive 4-k bit test SRAM. This SRAM consists of cells that employ an offset voltage to adjust their upset sensitivity and an enlarged sensitive drain junction to enhance the cell's upset rate.

Buehler, Martin G.↗
NASA NTRS2007

Increasing the dynamic range of CMOS photodiode imagers

A multiple-step reset process and circuit for resetting a voltage stored on a photodiode of an imaging device. A first stage of the reset occurs while a source and a drain of a pixel source-follower transistor are held at ground potential and the photodiode and a gate of the pixel source-follower transistor are charged to an initial reset voltage having potential less that of a supply voltage. A second stage of the reset occurs after the initial reset voltage is stored on the photodiode and the gate of the pixel source-follower transistor and the source and drain voltages of the pixel source-follower transistor are released from ground potential thereby allowing the source and drain voltages of the pixel source-follower transistor to assume ordinary values above ground potential and resulting in a capacitive feed-through effect that increases the voltage on the photodiode to a value greater than the initial reset voltage.

Pain, Bedabrata↗
NASA NTRS2009

Radiation Testing on State-of-the-Art CMOS: Challenges, Plans, and Preliminary Results

At GOMAC 2007 and 2008, we discussed a variety of challenges for radiation testing of modern semiconductor devices and technologies [1, 2]. In this presentation, we provide more specific details in this on-going investigation focusing on out-of-the-box lessons observed for providing radiation effects assurances as well as preliminary test results.

LaBel, Kenneth A.↗
NASA NTRS2011

CMOS active pixel sensor type imaging system on a chip

A single chip camera which includes an .[.intergrated.]. .Iadd.integrated .Iaddend.image acquisition portion and control portion and which has double sampling/noise reduction capabilities thereon. Part of the .[.intergrated.]. .Iadd.integrated .Iaddend.structure reduces the noise that is picked up during imaging.

Fossum, Eric R.↗
NASA NTRS2013

CMOS-Compatible SOI MESFETS for Radiation-Hardened DC-to-DC Converters

A radiation-tolerant transistor switch has been developed that can operate between 196 and +150 C for DC-to-DC power conversion applications. A prototype buck regulator component was demonstrated to be performing well after a total ionizing dose of 300 krad(Si). The prototype buck converters showed good efficiencies at ultra-high switching speeds in the range of 1 to 10 MHz. Such high switching frequency will enable smaller, lighter buck converters to be developed as part of the next project. Switching regulators are widely used in commercial applications including portable consumer electronics.

Thornton, Trevor↗
NASA NTRS2013

The DUV Stability of Superlattice-Doped CMOS Detector Arrays

In this paper, we present experimental results and band structure calculations that illuminate the unique properties of superlattice-doped detectors. Numerical band structure calculations are presented to analyze the dependencies of surface passivation on dopant profiles and interface trap densities (Figure 3). Experiments and calculations show that quantum-engineered surfaces, grown at JPL by low temperature molecular beam epitaxy, achieve a qualitative as well as quantitative uniqueness in their near-immunity to high densities of surface and interface traps.

doped silicon surfaces↗
NASA NTRS2015

Sparsely-Bonded CMOS Hybrid Imager

A method and device for imaging or detecting electromagnetic radiation is provided. A device structure includes a first chip interconnected with a second chip. The first chip includes a detector array, wherein the detector array comprises a plurality of light sensors and one or more transistors. The second chip includes a Read Out Integrated Circuit (ROIC) that reads out, via the transistors, a signal produced by the light sensors. A number of interconnects between the ROIC and the detector array can be less than one per light sensor or pixel.

Cunningham, Thomas J.↗
NASA NTRS2015

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor - System-on-a-Chip

Hardness assurance test results of Intel state-of-the-art 14nm Broadwell U-series processor System-on-a-Chip (SoC) for total dose are presented, along with first-look exploratory results from trials at a medical proton facility. Test method builds upon previous efforts by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

14nm↗
NASA NTRS2015

Preliminary Radiation Testing of a State-of-the-Art Commercial 14nm CMOS Processor/System-on-a-Chip

Hardness assurance test results of Intel state-of-the-art 14nm “Broadwell” U-series processor / System-on-a-Chip (SoC) for total ionizing dose (TID) are presented, along with exploratory results from trials at a medical proton facility. Test method builds upon previous efforts [1] by utilizing commercial laptop motherboards and software stress applications as opposed to more traditional automated test equipment (ATE).

microprocessor↗