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DOE OSTI2023

Wafer-Scale Synthesis of 2D Materials by an Amorphous Phase-Mediated Crystallization Approach

The interest in the wafer-scale growth of two-dimensional (2D) materials, including transition metal dichalcogenides (TMDCs), has been rising for transitioning from lab-scale devices to commercial-scale systems. Among various synthesis techniques, physical vapor deposition, such as pulsed laser deposition (PLD), has shown promise for the wafer-scale growth of 2D materials. However, due to the high volatility of chalcogen atoms (e.g., S and Se), films deposited by PLD usually suffer from a lack of stoichiometry and chalcogen deficiency. To mitigate this issue, excess chalcogen is necessary during the deposition, which results in problems like uniformity or not being repeatable. This study demonstrates a condensed-phase or amorphous phase-mediated crystallization (APMC) approach for the wafer-scale synthesis of 2D materials. This method uses a room-temperature PLD process for the deposition and formation of amorphous precursors with controlled thicknesses, followed by a post-deposition crystallization process to convert the amorphous materials to crystalline structures. This approach maintains the stoichiometry of the deposited materials throughout the deposition and crystallization process and enables the large-scale synthesis of crystalline 2D materials (e.g., MoS 2 and WSe 2 ) on Si/SiO 2 substrates, which is critical for future wafer-scale electronics. We show that the thickness of the layers can be digitally controlled by the number of laser pulses during the PLD phase. Optical spectroscopy is used to monitor the crystallization dynamics of amorphous layers as a function of annealing temperature. The crystalline quality, domain sizes, and the number of layers were explored using nanoscale and atomistic characterization (e.g., AFM, STEM, and EDS) along with electrical characterization to explore process–structure–performance relationships. Finally, this growth technique is a promising method that could potentially be adopted in conventional semiconductor industries for wafer-scale manufacturing of next-generation electronic and optoelectronic devices.

2D electronics↗

DOE OSTI2023

High-throughput manufacturing of epitaxial membranes from a single wafer by 2D materials-based layer transfer process

Layer transfer techniques have been extensively explored for semiconductor device fabrication as a path to reduce costs and to form heterogeneously integrated devices. These techniques entail isolating epitaxial layers from an expensive donor wafer to form freestanding membranes. However, current layer transfer processes are still low-throughput and too expensive to be commercially suitable. Here we report a high-throughput layer transfer technique that can produce multiple compound semiconductor membranes from a single wafer. We directly grow two-dimensional (2D) materials on III–N and III–V substrates using epitaxy tools, which enables a scheme comprised of multiple alternating layers of 2D materials and epilayers that can be formed by a single growth run. Each epilayer in the multistack structure is then harvested by layer-by-layer mechanical exfoliation, producing multiple freestanding membranes from a single wafer without involving time-consuming processes such as sacrificial layer etching or wafer polishing. Moreover, atomic-precision exfoliation at the 2D interface allows for the recycling of the wafers for subsequent membrane production, with the potential for greatly reducing the manufacturing cost.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

DOE OSTI2021

200 mm sensor development using bonded wafers

Sensors fabricated from high resistivity, float zone, silicon material have been the basis of vertex detectors and trackers for the last 30 years. The areas of these devices have increased from a few square cm to > 200m 2 for the existing CMS tracker. High Luminosity Large Hadron Collider (HL-LHC), CMS and ATLAS tracker upgrades will each require more than 200 m 2 of silicon and the CMS High Granularity Calorimeter (HGCAL) will require more than 600 m 2 . The cost and complexity of assembly of these devices is related to the area of each module, which in turn is set by the size of the silicon sensors. In addition to large area, the devices must be radiation hard, which requires the use of sensors thinned to 200 microns or less. The combination of wafer thinning and large wafer diameter is a significant technical challenge, and is the subject of this work. In this paper we describe work on development of thin sensors on 200 mm wafers using wafer bonding technology. Results of development runs with float zone, Silicon-on-Insulator and Silicon-Silicon bonded wafer technologies are reported.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2025

Wafer-Free Crystalline Silicon Solar Cells (CRADA Final Report)

This CRADA project, based on the DOE Solar Energy Technologies Office (SETO) Solar Prize Voucher program, helped Leap Photovoltaics to develop methodologies to immobilize Si particles by permanently attaching them to an Al-coated substrate and thereby forming carrier-selective electrical contacts to the Si particles. The bigger goal was to help Leap Photovoltaics develop these immobilized and contacted particle arrays into relatively efficient, inexpensive, and industrially relevant solar cells. By using Si particles instead of wafers in a solar cell absorber layer, one can avoid costs associated with growing monocrystalline Si ingots, then diamond-sawing them into wafers, then processing wafers into cells – a mainstream practice in today's high-efficiency Si cell and module technology. Monocrystalline or polycrystalline Si particles can be obtained in various ways: for example, Si kerf from wafer sawing is monocrystalline; recycled Si cell wafers can be ball-milled into particles; particles can be grown using various gas-phase techniques (mostly from SiH4). These Si particles can be assembled onto a substrate and serve as an absorber layer for the solar cell, absorbing photons to generate photocarriers. The challenge with this technique is to collect photocarriers from individual Si particles, with separation of photogenerated electrons to the negative cell’s electrode and positive photogenerated holes to the positive electrode. Therefore, each particle must have two isolated, carrier-selective contacts: one for electrons and one for holes. Plus, particles need to be immobilized onto a solid substrate. The goal of this work was focused on the immobilization of Si particles and creating hole-selective contact to them at the same time, using industrially relevant Si photovoltaic (PV) cell technology: screen printing of Al back-surface field electrodes. This is used in the mainstream Propane Education and Research Council (PERC) technology for hole-collecting contacts at the back of the cell. The work performed at NREL consisted of screen printing of Al metal paste on substrates, spreading Si particles onto it, and thermally processing the structures to form hole-collecting contacts. The final structures were investigated by scanning electron microscopy (SEM) after focused ion beam (FIB) cross-sectioning and polishing. The work was done jointly by NREL staff and Leap Photovoltaics (Leap PV) employees stationed at NREL. The samples were then taken to Leap PV for further processing. Training the Leap PV employee on various NREL techniques (laser cutting, screen printing, thermal processing, characterization) was part of the scope.

14 SOLAR ENERGY↗

DOE OSTI2024

Acoustics-based noninvasive wafer defect detection

Techniques are provided for detecting wafer defects. Example techniques include exciting a wafer using an acoustic signal to cause the wafer to exhibit vibrations, measuring one or more of linear frequency response metrics or nonlinear frequency responses metrics associated with the vibrations, and identifying any defects in the wafer based at least in part on one or more of the linear frequency response metrics or nonlinear frequency responses metrics. In embodiments, the wafer includes bismuth telluride (Bi 2 Te 3 ).

Pantea, Cristian↗

DOE OSTI2020

High-yield growth kinetics and spatial mapping of single-walled carbon nanotube forests at wafer scale

Emerging commercial applications of vertically aligned, single-walled carbon nanotube (SWCNT) “forests” require synthesis that minimizes nanotube diameter while maximizing number density across substrate areas exceeding centimeter scale. To address this need, we synthesized SWCNT forests on full silicon wafers with notable reproducibility and uniformity, and co-optimized growth for small diameters and high densities across large areas to access new territory in this 3D parameter space. We mapped the spatial uniformity of key structural features using Raman microscopy, synchrotron X-ray scattering, and Rutherford backscattering spectrometry. Low C 2 H 2 flux over sub-nm Fe/Mo catalysts produced small-diameter SWCNTs (2.1 nm) at high number densities (2.26 × 10 12 cm -2 ) on wafers up to 6 in. Although removing Mo resulted in larger SWCNT diameters and lower densities (<0.7 × 10 12 cm -2 ), mass conversion rates from C 2 H 2 to SWCNT product were high and remarkably invariant for catalyst compositions and densities (i.e., 47.7% or 1.30 × 10 6 % g-catalyst -1 on 4-in. wafers). These carbon conversion efficiencies far exceed typical benchtop reactors and are on par with the best reported literature values. Our detailed elucidation of correlations among structural characteristics within this resource-efficient process is expected to guide future scale-up efforts of SWCNT forest growth beyond wafer scale.

36 MATERIALS SCIENCE↗

DOE OSTI2023

Integrated Ion-Exchange Membrane Resin Wafer Assemblies for Aromatic Organic Acid Separations Using Electrodeionization

Aromatic acids, such as p-coumaric acid, are valuable chemical intermediates that are used in the specialty chemical industries because they are precursors to phenylpropanoid compounds. The separation of p-coumaric acid from fermentation broths is a critical step in the biochemical production process and more broadly the circular carbon economy. Electrodeionization (EDI) has been applied toward separations of low-carbon chain acids, but purifying p-coumaric acid has been challenging due to fouling and irreversible binding with ion-exchange membranes and resins. Here, we report a new membrane wafer assembly (MWA) consisting of laminated ion exchange membranes to porous ionomer-binder resin wafers for EDI. The MWAs in an EDI stack showed a 7-fold increase in p-coumaric acid capture while also using 70% less specific energy consumption when benchmarked against state-of-the-art resin wafer EDI modules. The more efficient p-coumaric acid recovery was ascribed to (i) the 38% reduction in interfacial transport resistance between the membrane and resin wafer and (ii) using imidazolium anion exchange membranes and ionomer binders in the MWA. MD simulations revealed enhanced transport rates for p-coumarate in imidazolium ionomers through π–π interactions. As a result, adopting the new MWA significantly reduced the amount of ion-exchange membranes in EDI and may lead to drastic capital cost savings.

42 ENGINEERING↗

DOE OSTI2022

Generation of selective single-mode guided waves by d 36 type piezoelectric wafer

In general, mixed modes and dispersion of guided wave occur at any excitation frequency, while single modes are needed for effective nondestructive evaluation of structures. In this work, we present an approach to generate a selective single-mode guided wave in plate-like structures by exploiting the unique directionality of the d 36 type piezoelectric wafer and the symmetry of fundamental guided wave modes. Specifically, we devise a unified fundamental shear horizontal (SH 0 ) wave/fundamental antisymmetric mode (A 0 ) wave directional transducer pair by attaching the d 36 type piezoelectric wafers back to back on the opposite sides of the plate to provide selective, directional single-mode guided waves for actuation and sensing. Originally, the d 36 -type piezoelectric wafer, poled and cut from the lead magnesium niobate-lead titanate crystal, produces a mixture of the in-plane SH 0 (symmetric) mode and out-of-plane A 0 (asymmetric) and S 0 (symmetric) modes. By applying the in-phase or out-of-phase applied electrical field to the coupled d 36 -type piezoelectric wafer pair, our devised approach generates selective single modes, SH 0 or A 0 , respectively, to propagate in the structure. We describe the theoretical development of our approach and conduct both numerical simulations and laboratory experiments for validations.

42 ENGINEERING↗

DOE OSTI2023

Nature of contaminants introduced in silicon wafers during molecular beam epitaxy chamber annealing

Epitaxial monolithic III–V/Si tandem solar cells are one of the most promising technologies to be adopted by the industry after the efficiency of the current market dominating single junction silicon solar cell saturates at its fundamental limit. One of the key limitations of this technology is the degradation of silicon wafers during in situ annealing in the molecular beam epitaxy chamber. Determining the nature of contaminants in this process is key to improve the efficiency of epitaxial tandem solar cells. However, to date, the nature of contaminants from molecular beam epitaxy chambers remains unknown. In this work, we use photoluminescence imaging, lifetime spectroscopy, and deep level transient spectroscopy to measure the electronic properties of extrinsic impurities incorporated during annealing in the molecular beam epitaxy chamber. Photoluminescence images reveal that at least two impurities diffuse into silicon wafers during molecular beam epitaxy annealing. One is highly localized, while the other one is distributed uniformly across the whole wafer. Phosphorus diffusion is found to confine the localized impurity within the diffused layer but is ineffective at preventing the indiffusion of other impurities. Lifetime spectroscopy shows that metastable impurities with characteristic similar to Cr and CrB in our molecular beam epitaxy annealed silicon wafers. No evidence of Fe or FeB was observed. The emission rates and concentrations of the electrically active defects were measured with deep-level transient spectroscopy: The emission rates of detected defects do not match that of known Cr-related defects.

36 MATERIALS SCIENCE↗

DOE OSTI2023

Specifications and pre-production of n + -in-p large-format strip sensors fabricated in 6-inch silicon wafers, ATLAS18, for the Inner Tracker of the ATLAS Detector for High-Luminosity Large Hadron Collider

Abstract The ATLAS experiment is constructing new all-silicon inner tracking system for HL-LHC. The strip detectors cover the radial extent of 40 to 100 cm. A new approach is adopted to use p-type silicon material, making the readout in n + -strips, so-called n + -in-p sensors. This allows for enhanced radiation tolerance against an order of magnitude higher particle fluence compared to the LHC. To cope with varying hit rates and occupancies as a function of radial distance, there are two barrel sensor types, the short strips (SS) for the inner 2 and the long strips (LS) for the outer 2 barrel cylinders, respectively. The barrel sensors exhibit a square, 9.8 × 9.8 cm 2 , geometry, the largest possible sensor area from a 6-inch wafer. The strips are laid out in parallel with a strip pitch of 75.5 μm and 4 or 2 rows of strip segments. The strips are AC-coupled and biased via polysilicon resistors. The endcap sensors employ a “stereo-annulus” geometry exhibiting a skewed-trapezoid shapes with circular edges. They are designed in 6 unique shapes, R0 to R5, corresponding to progressively increasing radial extents and which allows them to fit within the petal geometry and the 6-inch wafer maximally. The strips are in fan-out geometry with an in-built rotation angle, with a mean pitch of approximately 75 μm and 4 or 2 rows of strip segments. The eight sensor types are labeled as ATLAS18xx where xx stands for SS, LS, and R0 to R5. According to the mechanical and electrical specifications, CAD files for wafer processing were laid out, following the successful designs of prototype barrel and endcap sensors, together with a number of optimizations. A pre-production was carried out prior to the full production of the wafers. The quality of the sensors is reviewed and judged excellent through the test results carried out by vendor. These sensors are used for establishing acceptance procedures and to evaluate their performance in the ATLAS collaboration, and subsequently for pre-production of strip modules and stave and petal structures.

Instruments & Instrumentation↗

DOE OSTI2025

Wafer-scale waveguide sidewall roughness scattering loss characterization by image processing

Photonic integrated circuits (PICs) are vital for developing affordable, high-performance optoelectronic devices that can be manufactured at an industrial scale, driving innovation and efficiency in various applications. Optical loss of modes in thin film waveguides and devices is a critical measure of their performance. Thin film growth, lithography, masking, and etching processes are imperfect processes that introduce significant sidewall and top-surface roughness and cause dominating optical losses in waveguides and photonic structures. This roughness, as perturbations couple light from guided to far-field radiation modes, leads to scattering losses that can be estimated from theoretical models. Typically, with UV-based lithography, sidewall roughness is significantly larger than wafer-top surface roughness. Atomic force microscopy (AFM) imaging measurement gives a 3D and high-resolution roughness profile, but the measurement is inconvenient, costly, and unscalable for large-scale PICs and at wafer-scale. Here, we evaluate the sidewall roughness profile based on 2D high-resolution scanning electron microscope (SEM) imaging. We characterized the loss on two homemade nitride and oxide films on 3-inch silicon wafers with 12 waveguide devices on each and correlated the scattering loss estimated from a 2D image-based sidewall profile and theoretical Payne model. The lowest loss of guided fundamental transverse electric (TE 0 ) mode is found at 0.075 dB/cm at 633 nm across 24 devices, a record at visible wavelength. Our work shows 100% success (edge continuity span exceeding 95% of image width/height) in edge detection in image processing of all images to estimate autocorrelation function and optical mode loss. These demonstrations offer valuable insights into waveguide sidewall roughness and a comparison of experimental and 2D SEM image processing based loss estimations with applications in loss characterization at wafer-scale PICs.

Khurana, Mohit (ORCID:0000000207898672)↗

DOE OSTI2022

Excess carrier concentration in silicon devices and wafers: How bulk properties are expected to accelerate light and elevated temperature degradation

Light and elevated temperature induced degradation (LeTID) is accelerated nearly linearly by the presence of excess carriers. It is therefore important to understand how excess carrier concentration (Δn) changes as a function of exposure conditions, materials properties, and sample structure. We simulate Δn as a function of wafer thickness and bulk minority carrier lifetime (τ) in solar cells and wafers using SCAPS and Quokka3. We also derive closed-form analytic expressions. For wafers, there is a near-linear relationship between Δn and τ or thickness, whereas for solar cells, Δn in the bulk may become limited by rear surface recombination. Thus, LeTID may progress more quickly in wafers than in cells, with a stronger dependence on τ. When comparing experiments, observed degradation rates must be corrected between samples or conditions to account for differences in Δn. This study demonstrates three tools to estimate the magnitude of such corrections, which can aid in the quantitative interpretation of LeTID data and performance predictions. Finally, while each tool yields similar results, there are advantages to each approach that must be weighed in terms of simplicity of inputs versus sophistication of treatment. Incomplete specification of back contact characteristics in commercial products is identified as an important contributor to uncertainty in expected LeTID rates.

36 MATERIALS SCIENCE↗

DOE OSTI2022

Multiplication of freestanding III-V semiconductor membranes from a single wafer by alternating growth with amorphous graphene interlayer

Freestanding single-crystalline III-V compound semiconductors are important building blocks for functional devices due to their high electron mobilities, a wide range of bandgaps, and excellent optoelectronic properties. Despite efforts to produce such membranes by detaching epitaxial layers from donor wafers, current methods suffer from either slow processes or poor material quality. Here, we demonstrate a technique to grow and harvest multiple epitaxial membranes with extremely high throughput at the wafer scale. For this, a process to directly grow amorphous graphene on III-V substrates in metal-organic chemical vapor deposition reactors is developed, which enables an advanced remote epitaxy scheme comprised of multiple alternating layers of amorphous graphene and III-V epitaxial layers that can be formed by a single epitaxy run. Each epilayer in the multi-stack structure is then harvested by layer-by-layer peeling, producing multiple freestanding membranes with unprecedented throughput from a single wafer. Because amorphous graphene provides a weak van der Waals interface that allows peeling at the interface without damaging the epilayer or the substrate, wafers can be reused for subsequent membrane production. Therefore, this work represents a meaningful step toward high-throughput and low-cost production of single-crystal membranes that can be heterointegrated.

Han, Ne Myo↗

DOE OSTI2022

Multiplication of freestanding III-V semiconductor membranes from a single wafer by alternating growth with amorphous graphene interlayer

Han, Ne Myo↗

DOE OSTI2024

Trap Passivation for Reducing On-Resistance and Saturation Voltage in Wafer-Bonded InGaAs-Channel/GaN-Drain Vertical FETs

High frequency and high power are the driving forces behind semiconductor transistor technology. However, conventional devices have the tradeoff of either being high speed or high breakdown—but not both. Wafer-bonded current aperture vertical electron transistors (BAVETs) help eliminate the tradeoff by combining a high-speed III-As channel to a high-breakdown III-N drift region. The device presented herein comprises of an InAlAs gate-barrier/InGaAs channel, wafer-bonded to an InGaN/GaN drift region, with the InGaAs/InGaN interface referred to as the wafer-bonded interface (WBI). The electronic behavior of WBIs is yet less known but necessary in realizing the potential of a BAVET. Herein, strong trap activity at the WBI is shown to be the cause of abnormally high saturation voltage ( V DS_SAT ) in BAVETs. The traps cause unintentional space charge (SC) region in the drain region of the device. This causes a drain resistance, a higher ON-resistance ( R ON ), and a higher V DS_SAT . Here, the challenge is overcome by hydrogen passivation of traps at WBI by using a p-doping for the InAlAs layer, which reduces the trap-charge concentration at the WBI. Consequently, the width of the SC region is reduced and a reduction in V DS_SAT is demonstrated, wherein it reduces from >12 to 5 V.

36 MATERIALS SCIENCE↗

DOE OSTI2023

Nanosecond Laser Drying in Wafer Foundries for Significant Energy Efficiency Improvement

Surface drying is a critical process in microelectronics wafer fabrication. In order to reduce and eliminate watermarks, many surface drying processes have been studied and used. Most of the wafer foundries currently use drying processes based on Isopropyl Alcohol (IPA), which causes serious safety (fire), health, environmental, and energy efficiency issues. The long-term goal of this project is to develop a fast, effective, chemical-free, and extremely energy efficient wafer drying technology that employs nanosecond laser-induced sub-surface evaporation and explosion. The objectives of this project are to 1) experimentally develop and verify the laser surface drying method, explore and identify how and to what extent various physical parameters influence the drying efficiency and effectiveness; and 2) understand and optimize the underlying thermodynamics in the proposed laser surface drying, including micro/nanoscale sub-surface superheating, evaporation, explosion, and photo/thermochemical bond breaking via atomistic modeling and experimental characterization. Toward these objectives, five tasks have been accomplished successfully, including 1) develop in-lab laser surface drying setup and study the effect of varied laser parameters, 2) use multiscale hybrid-modeling to study and understand the physics of water behavior during drying toward process optimization, 3) investigate the effect of drying conditions on the drying effectiveness, 4) develop a large-scale laser drying scanning system with automatic scanning, and 5) conduct large-scale simulation to study the effect of dopant level and develop strategies for system development toward industry deployment.

42 ENGINEERING↗

DOE OSTI2025

Hexagonal Boron Nitride: Physical Properties, Hydride Vapor‐Phase Epitaxy Growth of Large‐Diameter Quasi‐Bulk Wafers and Applications

Hexagonal boron nitride ( h ‐BN), with its ultrawide bandgap and 2D structure, holds an immense promise for advanced semiconductor applications. Scaling bulk crystals to large‐diameter wafers, crucial for complex device fabrication, remains a challenge with high temperature, high pressure, and metal flux solution methods. To address this, recent efforts have focused on hydride vapor‐phase epitaxy (HVPE) for producing large diameter thick h ‐BN quasi‐bulk wafers, reaching hundreds of micrometers. These HVPE‐grown quasi‐bulk crystals exhibit excellent c ‐axis long‐range order. Notably, the in‐plane mobility‐lifetime products for both electrons and holes surpass 10 −4 cm 2 V −1 , which are two orders of magnitude greater than the out‐of‐plane (vertical) values, highlighting the potential for high‐performance devices leveraging superior lateral transport. Lateral detectors fabricated from 100 μm thick B‐10 enriched h‐ BN wafers have achieved a record 60% thermal neutron detection efficiency. Based on its physical properties, h‐ BN appears to be an outstanding material of choice for light‐triggered electronic power switches capable of supporting high ‐ voltage and high ‐ power operations. These recent advancements in large‐diameter h ‐BN quasi‐bulk crystal growth, enabled by HVPE, pave the way for applications spanning deep UV photonics, high‐power electronics, high‐efficiency neutron detection, and quantum information technologies, establishing h ‐BN as both a versatile active semiconductor and an ideal substrate.

Jiang, Hongxing [Department of Electrical and Comp↗

DOE OSTI2020

Sub-micrometer random-pyramid texturing of silicon solar wafers with excellent surface passivation and low reflectance

Select emerging solar cell technologies, ranging from very narrow screen-printed fingers to perovskite/silicon tandems, would benefit from a reduction of the height of the standard pyramidal texture of monocrystalline silicon wafers to below 1 μm. However, fabricating such small surface features usually compromises the requisite low reflectance and high passivation quality. Through systematic design of experiments, we demonstrate that conventional alkaline-based wet-chemical etching processes can be tuned to produce dense, spatially homogeneous, and uniformly sized sub-micrometer pyramids. Precise texture size can be further controlled by adding potassium silicate to the texturing solution to effectively slow the pyramid growth rate and promote nucleation. With pyramid size distribution data—extracted from multiple atomic force microscopy images across each wafer—we demonstrate 16 nanotextures with average pyramid sizes ranging from 62 to 512 nm, with the largest having only 0.3% of its pyramids taller than 1 μm. Six of the nanotextures exhibit light trapping and surface defect densities comparable to state-of-the-art microtextured wafers. In conclusion, the best nanotexture achieved an AM1.5G-weighted reflectance of 11.8% and a minority-carrier lifetime of 3.4 ms after passivation with amorphous silicon, demonstrating that smaller textures need not deteriorate solar cell performance.

14 SOLAR ENERGY↗