Results for “submodule” — Page 2

DOE OSTI2021

Multiscale Electrothermal Design of a Modular Multilevel Converter for Grid-Tied Applications

As a key feature of modular multilevel converters (MMCs), a large number of semiconductor devices are employed in the converter and distributed over a stack of submodules. Each submodule has a strict temperature limit that imposes constraints on the operating range of the converter. Different loading conditions/losses in the submodules lead to unavoidable temperature variations inside the MMC, which consequently affect the system-level performance and reliability. This paper is focused on the electrothermal analysis and design of a medium-voltage silicon carbide (SiC)-based MMC system, from submodule power semiconductors to the overall MMC system integration of multiple submodules. Loss calculations are performed to estimate the cooling requirements and aid thermal design at different levels. The performance of forced-air cooling approach is analyzed within a numerical modeling framework. Maximum temperature of the SiC power modules is predicted using numerical tools. Thermal design of the MMC cabinet with various arrangement of air inlet(s) and outlet(s) is investigated and compared from a cooling performance perspective.

CFD↗

DOE OSTI2021

Controlling selectivity of modular microbial biosynthesis of butyryl-CoA-derived designer esters

Short-chain esters have broad utility as flavors, fragrances, solvents, and biofuels. Controlling selectivity of ester microbial biosynthesis has been an outstanding metabolic engineering problem. In this study, we enabled the de novo fermentative microbial biosynthesis of butyryl-CoA-derived designer esters (e.g., butyl acetate, ethyl butyrate, butyl butyrate) in Escherichia coli with controllable selectivity. Using the modular design principles, we generated the butyryl-CoA-derived ester pathways as exchangeable production modules compatible with an engineered chassis cell for anaerobic production of designer esters. We designed these modules derived from an acyl-CoA submodule (e.g., acetyl-CoA, butyryl-CoA), an alcohol submodule (e.g., ethanol, butanol), a cofactor regeneration submodule (e.g., NADH), and an alcohol acetyltransferase (AAT) submodule (e.g., ATF1, SAAT) for rapid module construction and optimization by manipulating replication (e.g., plasmid copy number), transcription (e.g., promoters), translation (e.g., codon optimization), pathway enzymes, and pathway induction conditions. To further enhance production of designer esters with high selectivity, we systematically screened various strategies of protein solubilization using protein fusion tags and chaperones to improve the soluble expression of multiple pathway enzymes. Finally, our engineered ester-producing strains could achieve 19-fold increase in butyl acetate production (0.64 g/L, 96% selectivity), 6-fold increase in ethyl butyrate production (0.41 g/L, 86% selectivity), and 13-fold increase in butyl butyrate production (0.45 g/L, 54% selectivity) as compared to the initial strains. Altogether, this study presented a generalizable framework to engineer modular microbial platforms for anaerobic production of butyryl-CoA-derived designer esters from renewable feedstocks.

59 BASIC BIOLOGICAL SCIENCES↗

DOE OSTI2020

A Novel Voltage Balancing Control With dv/dt Reduction for 10-kV SiC MOSFET-Based Medium Voltage Modular Multilevel Converter

Using high voltage (HV) silicon carbide (SiC) power semiconductors in a modular multilevel converter (MMC) is promising because it results in fewer submodules and lower switching loss compared to conventional Si based solutions. The nearest level pulsewidth modulation (NL-PWM) is commonly used in the MMC for medium voltage applications. However, with the NL-PWM and existing voltage balancing control, there are many submodules that switch their modes in a control cycle, resulting in a high dv/dt during the deadtime of the power semiconductor, which could be multiple times of the dv/dt of the single device. This poses great challenges on the noise immunity and insulation design in the MMC using HV SiC devices, which have very fast switching speed. A novel voltage balancing control, which ensures only two submodules switch their modes in a control cycle, is proposed in this article, limiting the maximum dv/dt to the dv/dt of a single power semiconductor and also maintaining the voltage balance performance. Furthermore, the proposed voltage balancing control is experimentally validated in a 10-kV SiC mosfet based MMC with four submodules per arm.

42 ENGINEERING↗

DOE OSTI2020

Capacitor Voltage Ripple Estimation and Optimal Sizing of Modular Multi-Level Converters for Variable-Speed Drives

This article deals with the sizing of submodule capacitors for modular multilevel converters (MMCs) used for variable speed drives for medium voltage and high voltage electric machines. Variable speed drives are required to run over a wide frequency range from zero to a few hundred Hz or even over 1 kHz. Under low frequency operation (<30 Hz), a large current ripple flowing through the MMC submodule capacitors will cause significant capacitor voltage fluctuation. This article proposes an optimal submodule capacitor selection method based on the common-mode voltage injection. The proposed sizing model includes two functions: 1) accurately estimating the capacitor voltage ripple based on the drive system parameters; and 2) identifying the minimum capacitance of the submodule capacitors based on the allowed maximum capacitor voltage fluctuations. Simulation and experimental results show that the error between the actual and estimated values of the voltage fluctuation is within 3% using the proposed model.

42 ENGINEERING↗

NASA NTRS1985

Amorphous silicon photovoltaic modules and test devices design, fabrication and testing

In July of 1984, Hughes and JPL initiated a contract for Hughes to design, fabricate and test 10 thin film Amorphous Silicon (a-Si) photovoltaic power modules. These modules were to be 1 ft x 4 ft in size. They were to be preceded by the delivery of 10 a-Si 4 in. square test devices. This effort is very timely since thin film PV development has progressed to the point where intermediate load power applications are on the horizon. It is important to know if current a-Si submodule design and manufacturing processes yield a product that is compatible with the packaging needed to meet a 20 to 30 year life span expectancy. The term submodule is assigned to an interconnected assembly of 28 a-Si cells deposited on a 1 foot square glass superstrate. These assemblies are equipped with electrical terminations, i.e., copper tabs at the four corners of the inverted submodules. It is these submodules that are to be interconnected and packaged into power modules, as opposed to the interconnected individual crystalline cells packaged into todays PV modules. A discussion of the fabrication methods and results follows.

Vanleeuwen, M.↗

NASA NTRS1985

Outdoor performance testing of thin-film devices

The Advanced Systems Research Group supports the photovoltaic advanced R&D (PV AR&D) project by providing outdoor (global) testing of PV cells, submodules, modules, and arrays. The group also provides in house engineering and analysis to identify and determine how technical issues such as cell/module/system adaptations, long term stability, reliability, economics, materials availability, safety, and environmental impacts affect the development and ultimate use of advanced PV thin film, innovative cell, and material technologies. A major thrust of the research effort is to develop and utilize instrumentation and procedures for monitoring and analyzing PV cells and submodules including outdoor performance and stability testing and life cycle accelerated stress testing. To accomplish the above, the solar energy research institute (SERI) outdoor PV test facility was established in 1982. The group has designed testing systems and analysis procedures for, and has tested, numerous amorphous silicon thin film submodules provided by SERI subcontractors and has performed long term outdoor stability tests on CdS/CuIr Se sub 2 and hydrogen passivated silicon solar cells. A significant contribution from this facility over the past year was the testing of large area amorphous silicon submodules.

Source record↗

NASA NTRS1988

The 30-GHz monolithic receive module

The fourth year progress is described on a program to develop a 27.5 to 30 GHz GaAs monolithic receive module for spaceborne-communication antenna feed array applications, and to deliver submodules for experimental evaluation. Program goals include an overall receive module noise figure of 5 dB, a 30 dB RF to IF gain with six levels of intermediate gain control, a five bit phase shifter, and a maximum power consumption of 250 mW. Submicron gate length single and dual gate FETs are described and applied in the development of monolithic gain control amplifiers and low noise amplifiers. A two-stage monolithic gain control amplifier based on ion implanted dual gate MESFETs was designed and fabricated. The gain control amplifier has a gain of 12 dB at 29 GHz with a gain control range of over 13 dB. A two-stage monolithic low noise amplifier based on ion implanted MESFETs which provides 7 dB gain with 6.2 dB noise figure at 29 GHz was also developed. An interconnected receive module containing LNA, gain control, and phase shifter submodules was built using the LNA and gain control ICs as well as a monolithic phase shifter developed previously under this program. The design, fabrication, and evaluation of this interconnected receiver is presented. Progress in the development of an RF/IF submodule containing a unique ion implanted diode mixer diode and a broadband balanced mixer monolithic IC with on-chip IF amplifier and the initial design of circuits for the RF portion of a two submodule receiver are also discussed.

Bauhahn, P.↗

NASA NTRS1993

NEP power subsystem modeling

The Nuclear Electric Propulsion (NEP) system optimization code consists of a master module and various submodules. Each of the submodules represents a subsystem within the total NEP power system. The master module sends commands and input data to each of the submodules and receives output data back. Rocketdyne was responsible for preparing submodules for the power conversion (both K-Rankine and Brayton), heat rejection, and power management and distribution.

Harty, Richard B.↗

DOE OSTI2022

Hardware Design of a 13.8-kV/3-MVA PV Plus Storage Solid-State Transformer (PVS-SST)

Not provided.

Engineering↗

DOE OSTI2021

Hardware Design of Medium Voltage SiC-Based Modular Multilevel Converters for Grid-Tied Applications

This paper presents a design of a 10 kV silicon carbide (SiC) MOSFET based modular multilevel converter (MMC). The MMC functions as the interconnection between a 24 kV dc bus and a 13. SkV distribution grid. This paper focuses on the hardware design of the MMC and its submodules. The gate driver, auxiliary power supply and bus bur in submodules are major components that need to meet high dv/dt immunity and high insulation voltage requirements. The gate driver achieves over 200 kV/us common mode transient immunity (CMTI). Its associated auxiliary power supply is based on an on-board transformer with over 30 kV insulation capability and 1.4 pF barrier capacitance. The busbar achieves less than 11 kV/cm electric field in the air to avoid partial discharges. Validation tests of the MMC submodule were performed by double pulse tests at 5 kV and buck converter tests at3 kV, 52A (peak). Reliable operations were achieved in validation tests.

auxiliary power supply↗

NASA NTRS1989

Large liquid rocket engine transient performance simulation system

Phase 1 of the Rocket Engine Transient Simulation (ROCETS) program consists of seven technical tasks: architecture; system requirements; component and submodel requirements; submodel implementation; component implementation; submodel testing and verification; and subsystem testing and verification. These tasks were completed. Phase 2 of ROCETS consists of two technical tasks: Technology Test Bed Engine (TTBE) model data generation; and system testing verification. During this period specific coding of the system processors was begun and the engineering representations of Phase 1 were expanded to produce a simple model of the TTBE. As the code was completed, some minor modifications to the system architecture centering on the global variable common, GLOBVAR, were necessary to increase processor efficiency. The engineering modules completed during Phase 2 are listed: INJTOO - main injector; MCHBOO - main chamber; NOZLOO - nozzle thrust calculations; PBRNOO - preburner; PIPE02 - compressible flow without inertia; PUMPOO - polytropic pump; ROTROO - rotor torque balance/speed derivative; and TURBOO - turbine. Detailed documentation of these modules is in the Appendix. In addition to the engineering modules, several submodules were also completed. These submodules include combustion properties, component performance characteristics (maps), and specific utilities. Specific coding was begun on the system configuration processor. All functions necessary for multiple module operation were completed but the SOLVER implementation is still under development. This system, the Verification Checkout Facility (VCF) allows interactive comparison of module results to store data as well as provides an intermediate checkout of the processor code. After validation using the VCF, the engineering modules and submodules were used to build a simple TTBE.

Mason, J. R.↗

DOE OSTI2021

Quantum Computer-Aided Design: Digital Quantum Simulation of Quantum Processors

With the increasing size of quantum processors, submodules that constitute the processor hardware will become too large to accurately simulate on a classical computer. Therefore, one would soon have to fabricate and test each new design primitive and parameter choice in time-consuming coordination between design, fabrication, and experimental validation. Here we show how one can design and test the performance of next-generation quantum hardware—by using existing quantum computers. Focusing on superconducting transmon processors as a prominent hardware platform, we compute the static and dynamic properties of individual and coupled transmons. We show how the energy spectra of transmons can be obtained by variational hybrid quantum-classical algorithms that are well suited for near-term noisy quantum computers. In addition, single- and two-qubit gate simulations are demonstrated via Suzuki-Trotter decomposition. Our methods pave a promising way towards designing candidate quantum processors when the demands of calculating submodule properties exceed the capabilities of classical computing resources.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2023

Active Fault Current Limiting Control for Half-Bridge MMC in HVDC Systems

DC faults of MMC can result in a significantly large fault current due to the discharge of submodule capacitors. The fault current not only risks damaging the MMC but also demands a considerable breaking capacity from the dc circuit breaker (DCCBs). This paper introduces two novel active fault current limiting methods (AFCLs), namely virtual impedance-based and energy control-based AFCL. The first method utilizes circulating current feedforward, which introduces a virtual arm impedance to suppress the rate of rise of the fault current. Meanwhile, the second method relies on the control of the internally stored energy of the MMC to automatically minimize the number of submodules that discharge during a dc-side fault. Therefore, both the dc-side current and the MMC arm current can be effectively suppressed after the occurrence of the fault. The proposed methods do not require fault detection and their response is proportional to the rate of rise in the fault current. Simulation case studies are presented to demonstrate the proposed methods.

active current limiting control↗

DOE OSTI2019

DC Impedance Model of MMC Considering Capacitor Voltage and Circulating Current Dynamics

The modular multilevel converter (MMC) is regarded as a competitive choice for future dc grids at high and medium voltage levels. To study the dc grid stability, a few MMC dc impedance models have been proposed, but their accuracy is limited by the assumption of ideal submodule voltage or neglecting the circulating current control. In this paper, a more accurate MMC dc impedance model is developed considering both the submodule capacitor voltage and circulating current dynamics. Simulation and experiment results indicate that the developed model matches with the actual MMC better than state-of-art models and can predict the dc system stability correctly.

Kong, Le↗

DOE OSTI2020

Multi-Scale Thermal Analysis for Design of SiC-Based Medium Voltage Motor Drive: Preprint

This paper describes a multi-scale thermal analysis approach for the design of an air-cooled 1.7-kV SiC MOSFET-based medium-voltage variable-speed motor drive. The National Renewable Energy Laboratory supported the project objectives by providing thermal management design support to the project partner The Ohio State University (OSU). The scope of the models and limited resources required efficient and flexible thermal models to be developed. Two modeling techniques are described that significantly reduced model run time and enabled more complex models to be run faster while retaining needed accuracy. The first technique uses the effectiveness-NTU method to extract convection boundary conditions from a computational fluid dynamics (CFD) model that can be applied to a fast-running finite element analysis model. The second is a porous media technique that enables system-level CFD simulations that incorporate effects from heat exchangers (e.g., pin fin heat sinks) that run in a fraction of the time required for fully resolved CFD simulations. The multi-scale approach to the thermal analysis enabled fast and accurate simulation for the converter design ranging from the die level up to the full system with 36 submodules. The modeling results were validated against experimental data from system tests performed by OSU.

DIRECT ENERGY CONVERSION↗

DOE OSTI2019

Integrated Electric Drive with HV 2 Modular Electric Machine and SiC Based Power Converters (Final Report)

An innovative high performance, high speed electric drive is designed, fabricated and tested. The drive is based on the modular multilevel converter (MMC) topology and is synthesized using power electronic building blocks (submodules) that utilize the newest generation of silicon-carbide (SiC) semiconductors. Power modules from two suppliers are investigated, characterized and the one showing better performance selected. A prototype MMC submodule is designed, built and tested in the lab. Simultaneously, control hardware and software are implemented and tested using real-time simulators. After verification of each of the subsystems, all subsystems are integrated to form a DC/AC converter-based drive. Multiple configurations are assembled and tested, and operation in variable voltages and frequencies, up to 4,160 V (line-to-line, rms), 140 A (rms) and 0-1,000 Hz is achieved. The efficiency of the drive system accomplished in the project is higher than 99.2% and the volume is 70% smaller than that of state-of-the art drives made using conventional technologies.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

DOE OSTI2023

Code Coverage Status of ARC Code-DIF3D

The Argonne Reactor Code (ARC) software system supports users in their fast reactor design goals by providing neutronic, thermal-hydraulic, and structural analysis capabilities. DIF3D plays a pivotal role in the ARC system as the primary homogenized assembly neutronic calculation methodology for fast reactor problems. Over its 40 years history, ARC software usage with DIF3D has been applied to numerous fast and thermal spectrum reactor analysis projects with good to excellent comparison against experiments. With continued improvement of computation resources, many of the geometry modeling capabilities in DIF3D that were primarily used in low order schemes are not really needed anymore. Today, the diffusion and transport capabilities of DIF3D-VARIANT are primarily used in the reactor design process with some scattered usage of DIF3D-FD and DIF3D-Nodal. In recent work, the DIF3D software verification was completed for DIF3D-FD and DIF3D-VARIANT on the geometry options used in the Versatile Test Reactor project. While we can be confident that these capabilities of DIF3D are well used and thus trusted, it does not demonstrate that all possible input options of DIF3D are actually working, but just those that were tested as part of VTR are and that they are correct. Thus, the purpose of the present work is to identify a set of test problems for DIF3D and assess the code coverage of DIF3D for those test problems. The goal is to document what parts of the existing DIF3D code are touched by the set of test problems and which are not. Because the verification work done on DIF3D-VARIANT and DIF3D-FD was focused on the most common uses of DIF3D for fast reactor analysis, the code coverage assessment of those capabilities is the highest priority. This will ensure that nothing is being missed by the existing verification test problems that DIF3D relies upon. The DIF3D-Nodal capability will also be inspected for code coverage as part of this work to further ensure that regular regression testing of DIF3D will trap any likely errors the end user might experience with the DIF3D software. The code coverage analysis of DIF3D was performed with the Code Coverage Tool of the Intel Fortran compiler which requires modifications to the compilation of DIF3D. The detailed coverage tables are given for each submodule of DIF3D separately, and for the submodules which are primarily developed for DIF3D, most of the source files could be at least partially touched. Most of the uncovered parts/files could be easily ignored, because they are either for error message and debugging output or obviously not needed by DIF3D. Out of the entire source codes of DIF3D, only a few uncovered modules deserve further investigation.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2025

Code Coverage Status of the ARC Code DIF3D

The Argonne Reactor Code (ARC) software system supports users in their fast reactor design goals by providing neutronic, thermal-hydraulic, and structural analysis capabilities. DIF3D plays a pivotal role in the ARC system as the primary homogenized assembly neutronic calculation methodology for fast reactor problems. Over its 40 years history, ARC software usage with DIF3D has been applied to numerous fast and thermal spectrum reactor analysis projects with good to excellent comparison against experiments. With continued improvement of computation resources, many of the geometry modeling capabilities in DIF3D that were primarily used in low order schemes are not really needed anymore. Today, the diffusion and transport capabilities of DIF3D-VARIANT are primarily used in the reactor design process with some scattered usage of DIF3D-FD and DIF3D-Nodal. In recent work, the DIF3D software verification was completed for DIF3D-FD and DIF3D-VARIANT on the geometry options used in the Versatile Test Reactor project. While we can be confident that these capabilities of DIF3D are well used and thus trusted, it does not demonstrate that all possible input options of DIF3D are actually working, but just those that were tested as part of VTR are and that they are correct. Thus, the purpose of the present work is to identify a set of test problems for DIF3D and assess the code coverage of DIF3D for those test problems. The goal is to document what parts of the existing DIF3D code are touched by the set of test problems and which are not. Because the verification work done on DIF3D-VARIANT and DIF3D-FD was focused on the most common uses of DIF3D for fast reactor analysis, the code coverage assessment of those capabilities is the highest priority. This will ensure that nothing is being missed by the existing verification test problems that DIF3D relies upon. The DIF3D-Nodal capability will also be inspected for code coverage as part of this work to further ensure that regular regression testing of DIF3D will trap any likely errors the end user might experience with the DIF3D software. The code coverage analysis of DIF3D was performed with the Code Coverage Tool of the Intel Fortran compiler which requires modifications to the compilation of DIF3D. The detailed coverage tables are given for each submodule of DIF3D separately, and for the submodules which are primarily developed for DIF3D, most of the source files could be at least partially touched. Most of the uncovered parts/files could be easily ignored, because they are either for error message and debugging output or obviously not needed by DIF3D. Out of the entire source codes of DIF3D, only a few uncovered modules deserve further investigation.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗