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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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An optical correlation technique for the nondestructive evaluation of printed circuit board solder joints was evaluated. Reliable indications of induced stress levels in solder joint lead wires are achievable. Definite relations between the inherent strength of a solder joint, with its associated ability to survive stress, are demonstrable.
The popularity of emerging miniaturized Chip Scale Packages (CSPs) is rapidly growing because of their benefits and smaller size.
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This paper will compare three different CSP concepts as well as their assembly reliability.
The JPL-led MicrotypeBGA Consortium of enterprises representing government agencies and private companies have jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
The JPL-led CSP Consortium of enterprises representing government agencies and private companies has jointed together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
Different aspects of advanced surface mount package technology have been investigated. Three key areas included the assembly reliability of conventional Surface Mount (SM), Ball Grid Arrays (BGAs), and Chip Scale Packages (CSPs).
This paper reviews many factors that affect interconnect reliability of commercial-off-the-shelf (COSTS) chip scale package (CSP) assemblies.
A JPL-led chip scale package (CSP) Consortium, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
The JPL-led MicrotypBGA Consortium of enterprises representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
This paper will present failure characteristics of the assemblies up to 7,000 cycles.
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This paper reviews the accelerated thermal cycling test methods that are currently used by industry to characterize the interconnect reliability of commercial-off-the-shelf (COTS) ball grid array (BGA) and chip scale package (CSP) assemblies.
Reviews the many factors that affect interconnect reliability of emerging chip scale package (CSP) assemblies. These include: package type, package build, board design, and assembly variables.
Team members representing government agencies and private companies have joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.
This paper reviews the package trend towards further miniaturization of emerging chip scale package (CSP).
The test results for numerous chip scale package assembly performed under MicrotypeBGA Consortium led by the Jet Propulsion Laboratory have been published previously.