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K.E. Martus,O.J. Orient,A Three-mesh gate is used in a time-of-flight(TOF) apparatus to analyze the Velocity of positive ions. Test results and a theoretical description are presented of an effect arising from trapping ions between meshes of a two gate TOF velocity analyzer. The entrapped ions produce a side peak in the TOF spectra corresponding to faster ions.
The Common Habitat is a large, long-duration habitat that uses an SLS core stage Liquid Oxygen (LOX) tank as its primary structure. Measuring 8.4 meters in diameter and 15 meters in length, it is manufactured as a habitat and launched as such into space. It is intended for use on the Moon as part of a permanently occupied outpost, on Mars as part of an outpost that will be occupied for hundreds of days at a time, and in deep space as part of the Deep Space Exploration Vehicle where it will support crewed missions up to 1200 days in duration. A study of internal orientation and crew size resulted in a Common Habitat configuration sized for a crew of eight with a three-deck horizontal orientation. The Common Habitat Vertical Translation System provides a means for transporting crew and cargo between decks in a Common Habitat spacecraft in gravity levels varying from 0g to 1g. A crowdsourcing campaign was conducted through the GrabCAD platform to initially solicit ideas for restraints and mobility aids, including vertical translation. Four of the five top responses repeated ideas that would be incorporated into features of the Vertical Translation System. The first was a safety barrier (to prevent falls into the opening between decks) that could collapse to form a floor surface covering the opening when not in use. The second idea was a folding ladder that could be stowed in the ceiling when not in use. The third idea was an elevator platform that could traverse the ladder. Several key driving requirements were established for the Vertical Translation System: it may not penetrate into or through the lower deck; it must work on the Earth, Moon, Mars, and in microgravity; it must be easy to operate; it must enable translation of any item that can fit through the Common Habitat’s 40” x 60” hatches, inclusive of suited and unsuited crew with any degree of incapacitation and any equipment or cargo item; and it must include three component systems – deploying floor / safety barriers, a deployable ladder, and an elevator platform. Additional requirements were established for each of the component systems. The safety barriers must form a roughly 40-inch tall, complete wall enclosure on all four sides when deployed; it must include an easy to open gate that allows access to/from the ladder when deployed; and when retracted, the safety barrier must form a smooth, load-bearing floor that can be walked on, and wheeled objects can be rolled across in gravity, without being a trip hazard. The deployable ladder must be composed of multiple ladders that work together; it must stow in the ceiling when not in use; and it must not penetrate into the 40” x 60” vertical passage corridor. The elevator platform must work with the deployable ladder system; it must be able to bridge any gap in ladders between decks; it must stop at each deck flush with the deck surface; it must be capable of transporting an incapacitated crew member as a single rescuer operation; it must be capable of transporting a full-size subsystems pallet; it must function as an elevator for a crew member carrying large objects; it must have safety functions to prevent falls from the platform, or crew/cargo collisions with edges of hatch openings, or entanglement with ladder rungs/structure; it must stow when not in use; and it must autonomously both connect itself to the ladder and deploy itself to any deck where needed when called (e.g., a crew member on any deck can call for the platform and it must connect itself to the ladders without assistance and translate to the requestor’s deck). These requirements were developed into a system concept with the assistance of a NASA Pathways Intern who also added the requirement to size the design based on the use of commercial components, using existing motors and other mechanisms to ensure that the resulting system could be inexpensively produced. The Floor and Safety Barrier consists of four panels, two roughly 40 inches long and two roughly 60 inches long that can fold into the floor on top of each other when not in use. The uppermost panel is load bearing and acts as the floor surface. When deployed, they connect with each other to form a rigid barrier surrounding the vertical passageway. One of the panels contains a hinged gate that can be opened when deployed to allow for access to/from the passageway. The Deploying Ladder consists of two ladder segments, one mounted on the ceiling of the lower deck and the other mounted on the ceiling of the mid deck. A rotating mechanism is mounted on the ladder to allow it to rotate into a horizontal position against the ceiling for stowage, or down to a vertical position for use. A second rotating mechanism is built into the ladder, allowing the rungs to rotate. A toothed surface intended to work with the elevator platform covers the front of the ladder rails and the top and bottom of the rails are designed to be flush when aligned with another ladder segment. The elevator platform is essentially a motorized, self-propelled deck. It has a mechanism that holds it in contact with the ladder rails and drives itself against the toothed surface. This mechanism allows the elevator platform to ascend or descend the ladder. In order to stow the platform when not in use, a set of short ladder rails (without rungs) are mounted to the ceiling of the mid deck. When the mid deck ladder is stowed, it is flush with these rails and the platform can drive itself onto those short rails for stowage. An additional mechanism on the platform can pitch its deck surface 90 degrees, such that when the ladder is to be stowed, the platform can fold up against the ceiling. As a consequence of the ladder and elevator platform design, the opening between decks in the Common Habitat was enlarged to ensure that the elevator platform can accept a payload up to 40”x60” in dimension.
Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.
One of the main goals of astrobiology is to understand the origin of cellular life. In the absence of any record of the earliest ancestors of contemporary cells, protocells, the most direct way to test our understanding of their characteristics is to construct laboratory models of protocells. Such efforts, currently underway in the NASA Astrobiology Program, are accompanied by computational studies aimed at explaining self-organization of simple molecules into ordered structures and developing designs of molecules that are capable of performing protocellular functions. Many of these functions, such as importing nutrients, capturing and storing energy, and responding to changes in the environment, are carried out by proteins bound to membranes. We use computer simulations to address the following, questions about these proteins: (1) How do small proteins (peptides) organize themselves into ordered structures at water-membrane interfaces and insert into membranes? (2) How do peptides aggregate to form membrane-spannin(y structures (e.g., channels)? (3) By what mechanisms do such aggregates perform their functions? The simulations are performed using the molecular dynamics (MD) method. In this method, Newton's equations of motion for each atom in the system are solved iteratively. At each time step, the forces exerted on each atom by the remaining atoms are evaluated by dividing them into two parts. Short-range forces are calculated directly in real space while long-range forces are evaluated in reciprocal space, usually using a particle-mesh algorithm which is of order O(NlnN). Currently, a time step of 2 femtoseconds is typically used, thereby making studies of problems occurring on multi-nanosecond time scales (10(exp 6) - 10(exp 8) time steps) accessible. To address a broader range of problems, simulations need to be extended by three orders of magnitude. Such an extension requires both algorithmic improvements and codes scalable to a large number of parallel processors. Work in this direction is in progress. Two specific series of simulations that demonstrate how peptides self-organize and function in membranes are discussed. In one series of simulations, it was shown that nonpolar peptides, disordered in water, translocate to the nonpolar interior of the membrane and, simultaneously, fold into two different helical structures, which remain in equilibrium. Once in the membrane, the peptides can readily change their orientation, especially in response to local electric fields. This structural and orientational flexibility of peptides with changing conditions may have provided a mechanism of transmitting signals between the environment and the interior of the protocell. In another series of simulations, the mechanism by which a simple protein channel efficiently mediates proton transport across membranes was investigated. This process is a key step in cellular bioenergetics. In the channel under study, proton transport is gated by four histidines that occlude the channel pore. The simulations demonstrate that protons move through the gate by a "shuttle" mechanism, wherein one histidine is protonated on the extracellular side and, subsequently, the proton bound on the opposite side is released.
Triode is constructed from rectangular filament made of near-intrinsic n-type silicon. Collector and emitter are formed on opposite faces of filament and are spaced approximately 0.13 mm apart. Gate electrodes are alloyed to filament and extend longitudinally along midsection of other two opposite sides, approximately 0.06 mm apart.
Single-event effect (SEE) radiation test results are presented for various trench-gate power MOSFETs. The heavy-ion response of the first (and only) radiation-hardened trench-gate power MOSFET is evaluated: the manufacturer SEE response curve is verified and importantly, no localized dosing effects are measured, distinguishing it from other, non-hardened trench-gate power MOSFETs. Evaluations are made of n-type commercial and both n- and p-type automotive grade trench-gate device using ions comparable to of those on the low linear energy transfer (LET) side of the iron knee of the galactic cosmic ray spectrum, to explore suitability of these parts for missions with higher risk tolerance and shorter duration, such as CubeSats. Part-to-part variability of SEE threshold suggests testing with larger sample sizes and applying more aggressive derating to avoid on-orbit failures. The n-type devices yielded expected localized dosing effects including when irradiated in an unbiased (0-V) configuration, adding to the challenge of inserting these parts into space flight missions.
A 256 word by 8-bit random access memory chip was developed utilizing p channel, metal gate metal-nitride-oxide-silicon (MNOS) technology; with operational characteristics of a 2.5 microsecond read cycle, a 6.0 microsecond write cycle, 800 milliwatts of power dissipation; and retention characteristics of 10 to the 8th power read cycles before data refresh and 5000 hours of no power retention. Design changes were implemented to reduce switching currents that caused parasitic bipolar transistors inherent in the MNOS structure to turn on. Final wafer runs exhibited acceptable yields for a die 250 mils on a side. Evaluation testing was performed on the device in order to determine the maturity of the device. A fixed gate breakdown mechanism was found when operated continuously at high temperature.
Special designs of two types of electronic components transistors and transmission lines have been conceived to optimize the performances of these components as parts of waveguide-embedded differential-amplifier monolithic microwave integrated circuits (MMICs) of the type described in the immediately preceding article. These designs address the following two issues, the combination of which is unique to these particular MMICs: Each MMIC includes a differential double-strip transmission line that typically has an impedance between 60 and 100 W. However, for purposes of matching of impedances, transmission lines having lower impedances are also needed. The transistors in each MMIC are, more specifically, one or more pair(s) of InP-based high-electron-mobility transistors (HEMTs). Heretofore, it has been common practice to fabricate each such pair as a single device configured in the side-to-side electrode sequence source/gate/drain/gate/source. This configuration enables low-inductance source grounding from the sides of the device. However, this configuration is not suitable for differential operation, in which it is necessary to drive the gates differentially and to feed the output from the drain electrodes differentially. The special transmission-line design provides for three conductors, instead of two, in places where lower impedance is needed. The third conductor is a metal strip placed underneath the differential double-strip transmission line. The third conductor increases the capacitance per unit length of the transmission line by such an amount as to reduce the impedance to between 5 and 15 W. In the special HEMT-pair design, the side-to-side electrode sequence is changed to drain/gate/source/gate/ drain. In addition, the size of the source is reduced significantly, relative to corresponding sizes in prior designs. This reduction is justified by the fact that, by virtue of the differential configuration, the device has an internal virtual ground, and therefore there is no need for a low-resistance contact between the source and the radio-frequency circuitry. The source contact is needed only for DC biasing. These designs were implemented in a single-stage-amplifier MMIC. In a test at a frequency of 305 GHz, the amplifier embedded in a waveguide exhibited a gain of 0 dB; after correcting for the loss in the waveguide, the amplifier was found to afford a gain of 0.9 dB. In a test at 220 GHz, the overall gain of the amplifier- and-waveguide assembly was found to be 3.5 dB.
Test results are presented for normally-off 4H-SiC Static Induction Transistors (SITs) intended for power switching and are among the first normally-off such devices realized in SiC. At zero gate bias, the gate p-n junction depletion layers extend far enough into the conduction channel to cut off the channel. Application of forward gate bias narrows the depletion regions, opening up the channel to conduction by majority carriers. In the present devices, narrow vertical channels get pinched by depletion regions from opposite sides. Since the material is SiC, the devices are usable at temperatures above 150 C. Static curve and pulse mode switching observations were done at selected temperatures up to 200 C on a device with average static characteristics from a batch of similar devices. Gate and drain currents were limited to about 400 mA and 3.5 A, respectively. The drain voltage was limited to roughly 300 V, which is conservative for this 600 V rated device. At 23 C, 1 kW, or even more, could be pulse mode switched in 65 ns (10 to 90 percent) into a 100 load. But at 200 C, the switching capability is greatly reduced in large part by the excessive gate current required. Severe collapse of the saturated drain-to-source current was observed at 200 C. The relation of this property to channel mobility is reviewed.
Collection of mathematical models includes second-order effects in n-channel, enhancement-mode, metal-oxide-semiconductor field-effect transistors (MOSFET's). When dimensions of circuit elements relatively large, effects neglected safely. However, as very-large-scale integration of microelectronic circuits leads to MOSFET's shorter or narrower than 2 micrometer, effects become significant in design and operation. Such computer programs as widely-used "Simulation Program With Integrated Circuit Emphasis, Version 2" (SPICE 2) include many of these effects. In second-order models of n-channel, enhancement-mode MOSFET, first-order gate-depletion region diminished by triangular-cross-section deletions on end and augmented by circular-wedge-cross-section bulges on sides.
Theoretical analysis and some experiments have shown that the silicon-on-insulator (SOI) 4-gate transistors known as G4-FETs can be used as building blocks of four-quadrant analog voltage multiplier circuits. Whereas a typical prior analog voltage multiplier contains between six and 10 transistors, it is possible to construct a superior voltage multiplier using only four G4-FETs. A G4-FET is a combination of a junction field-effect transistor (JFET) and a metal oxide/semiconductor field-effect transistor (MOSFET). It can be regarded as a single transistor having four gates, which are parts of a structure that affords high functionality by enabling the utilization of independently biased multiple inputs. The structure of a G4-FET of the type of interest here (see Figure 1) is that of a partially-depleted SOI MOSFET with two independent body contacts, one on each side of the channel. The drain current comprises of majority charge carriers flowing from one body contact to the other that is, what would otherwise be the side body contacts of the SOI MOSFET are used here as the end contacts [the drain (D) and the source (S)] of the G4-FET. What would otherwise be the source and drain of the SOI MOSFET serve, in the G4-FET, as two junction-based extra gates (JG1 and JG2), which are used to squeeze the channel via reverse-biased junctions as in a JFET. The G4-FET also includes a polysilicon top gate (G1), which plays the same role as does the gate in an accumulation-mode MOSFET. The substrate emulates a fourth MOS gate (G2). By making proper choices of G4-FET device parameters in conjunction with bias voltages and currents, one can design a circuit in which two input gate voltages (Vin1,Vin2) control the conduction characteristics of G4-FETs such that the output voltage (Vout) closely approximates a value proportional to the product of the input voltages. Figure 2 depicts two such analog multiplier circuits. In each circuit, there is the following: The input and output voltages are differential, The multiplier core consists of four G4- FETs (M1 through M4) biased by a constant current sink (Ibias), and The G4-FETs in two pairs are loaded by two identical resistors (RL), which convert a differential output current to a differential output voltage. The difference between the two circuits stems from their input and bias configurations. In each case, provided that the input voltages remain within their design ranges as determined by considerations of bias, saturation, and cutoff, then the output voltage is nominally given by Vout = kVin1Vin2, where k is a constant gain factor that depends on the design parameters and is different for the two circuits. In experimental versions of these circuits constructed using discrete G4- FETs and resistors, multiplication of voltages in all four quadrants (that is, in all four combinations of input polarities) was demonstrated, and deviations of the output voltages from linear dependence on the input voltages were found to amount to no more than a few percent. It is anticipated that in fully integrated versions of these circuits, the deviations from linearity will be made considerably smaller through better matching of devices.
The Tropical Rainfall Measuring Mission was a new concept of measuring rainfall over the global tropics using a combination of instruments, including the first weather radar to be flown in space. An important objective of the mission was to obtain profiles of latent heat in order to initialize large-scale circulation models and to understand the relationship between short-term climate changes in relation to rainfall variability. The idea originated in the early 1980's from scientists at the Goddard Space Flight Center/NASA who had been involved with attempts to measure rain with a passive microwave instrument on Nimbus 5 and had compared its results with rain falling in the area covered by the GATE1 radar ships. Using an imaginary satellite flying over the GATE ships, scientists showed that a satellite with an inclined orbit of 30-35 degrees could obtain monthly rainfalls with a sampling error of less than 10 percent over 5 degree by 5 degree areas. The Japanese proposed that they could build a nadir-scanning rain radar for the satellite. Vern Suomi was excited by this mission from the outset, since he recognized the great importance of adequate rainfall measurements over the tropical oceans. He was a charter member of the Science Steering Team and prepared a large part of the Report. While the mission attracted strong support in the science community, it was opposed by some of the high-level NASA management who feared its competition for funds with some much larger Earth Science satellites. Vern was able to overcome this opposition and to generate Congressional support, so that the Project finally got underway on both sides of the Pacific in 1991. The paper will discuss the design of the satellite, its data system and ground validation program. TP.NM was successfully launched in late 1997. Early results will be described. 1 GATE stands for GARP Atlantic Tropical Experiment and GARP stands for Global Atmospheric Research Program.
SpaceWire is used in the control and data interface for an instrument on a pair of small satellites, one of which was launched in summer 2017. The instrument SpaceWire interface is implemented in a Field Programmable Gate Array as an instantiated core controlled by a LEON3FT CPU, which is also implemented as an instantiated core. The UT699 processor in the flight computer provides the spacecraft side’s SpaceWire interface. A simple message based protocol consisting of four message types was defined, based on existing SpaceWire standards. One was for passing commands to and responses from the instrument in the form of text strings similar to those from a system console where each line of text is passed in a SpaceWire message. Another was for passing spacecraft time to the instrument. The third was for transferring files using a subset of the Remote Memory Access Protocol (RMAP). The fourth was for retrieving science data from the instrument. A set of user application programming interface (API) routines provided an abstracted interface to both the serial console (used during debug) and the SpaceWire device interface. Early instrument development and testing was done with a set of utilities that controlled a Star-Dundee USB-SpaceWire brick providing a user interface similar to a serial console terminal emulator with the addition of file and data transfers. Later in the integration and test process, these utilities were integrated with the COSMOS ground systems software used for spacecraft control, providing a seamless transition from standalone instrument tests to benchtop flat-sat test and full spacecraft level tests.
Output of latching four-input open-collector NAND gate is connected to isolating reed relay and intersection pushbutton. In matrix assembly, edge and corner circuits will require fewer gates, since they originate control lines. Collective row or column reset buttons operate on respective control-line originating points, and control-board disable switch operates on line connecting ground side of all intersection pushbuttons.
The designs of the 512 x 512 pixel and 2048 x 2048 pixel CCD sensors developed for scientific imaging are described. Both sensors are manufactured using the three phase, three level polysilicon gate technology, and the architecture of the chips is series-parallel-series. The components of the two different on-chip amplifiers are examined. The sensors are thinned and operated in the back side illumination mode to ensure the highest quantum efficiency. The performances of a number of front side illuminated devices and two thinned rear illuminated chips are evaluated. It is observed that the sensors equal or exceed their proposed charge transfer efficiency of 0.99999, the noise level of 2 e- and 20 e- at 50 kp/s, the quantum efficiency of 40 percent at 400 microns and 70 percent at 700 microns, and of the well capacity of greater than 500 ke-/pixel.
To our knowledge, previous observations of cloud boundaries have been limited to studies of cloud bases with ceilometers, cloud tops with satellites, and intermittent reports by aircraft pilots. Comprehensive studies that simultaneously record information of cloud top and cloud base, especially in multiple layer cases, have been difficult, and require the use of active remote sensors with range-gated information. In this study, we examined a 4-week period during which the NOAA Wave Propagation Laboratory (WPL) 8-mm radar and the Pennsylvania State University (PSU) 3-mm radar operated quasi-continuously, side by side. By quasi-continuously, we mean that both radars operated during all periods when cloud was present, during both daytime and nighttime hours. Using this data, we develop a summary of cloud boundaries for the month of November for a single location in the mid-continental United States.
A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the dopings and the lower supply potentials in area I can be tailored to optimize imager performance. In area I, the device layer includes an n+ -doped silicon layer on which is grown an n-doped silicon layer. A p-doped silicon layer is grown on top of the n -doped layer. The total imaging device thickness is the sum of the thickness of the n+, n, and p layers. A pixel photodiode is formed between a surface n+ implant, a p implant underneath it, the aforementioned p layer, and the n and n+ layers. Adjacent to the diode is a gate for transferring photogenerated charges out of the photodiode and into a floating diffusion formed by an implanted p+ layer on an implanted n-doped region. Metal contact pads are added to the back-side for providing back-side bias.
Integral membrane proteins perform such essential cellular functions as transport of ions, nutrients and waste products across cell walls, transduction of environmental signals, regulation of cell fusion, recognition of other cells, energy capture and its conversion into high-energy compounds. In fact, 30-40% of genes in modem organisms codes for membrane proteins. Although contemporary membrane proteins or their functional assemblies can be quite complex, their transmembrane fragments are usually remarkably simple. The most common structural motif for these fragments is a bundle of alpha-helices, but occasionally it could be a beta-barrel. In a series of molecular dynamics computer simulations we investigated self-organizing properties of simple membrane proteins based on these structural motifs. Specifically, we studied folding and insertion into membranes of short, nonpolar or amphiphatic peptides. We also investigated glycophorin A, a peptide that forms sequence-specific dimers, and a transmembrane aggregate of four identical alpha-helices that forms an efficient and selective voltage-gated proton channel was investigated. Many peptides are attracted to water-membrane interfaces. Once at the interface, nonpolar peptides spontaneously fold to a-helices. Whenever the sequence permits, peptides that contain both polar and nonpolar amino also adopt helical structures, in which polar and nonpolar amino acid side chains are immersed in water and membrane, respectively. Specific identity of side chains is less important. Helical peptides at the interface could insert into the membrane and adopt a transmembrane conformation. However, insertion of a single helix is unfavorable because polar groups in the peptide become completely dehydrated upon insertion. The unfavorable free energy of insertion can be regained by spontaneous association of peptides in the membrane. The first step in this process is the formation of dimers, although the most common are aggregates of 4-7 helices. The helices could arrange themselves such that they formed pores capable of transporting ions and small molecules across membranes. Stability of transmembrane aggregates of simple proteins is often only marginal and, therefore, it can be regulated by environmental signals or small sequence modifications in the region of interhelical interactions. A key step in the earliest evolution of membrane proteins was the emergence of selectivity for specific substrates. Many channels could become selective if one or only a few properly chosen amino acids are properly placed along the channel, acting as filters or gates. This is a convenient evolutionary solution because it does not require imposing conditions on the whole sequence.