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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2022

Progress in Near-Equilibrium Ammonothermal (NEAT) Growth of GaN Substrates for GaN-on-GaN Semiconductor Devices

This paper reviews the near-equilibrium ammonothermal (NEAT) growth of bulk gallium nitride (GaN) crystals and reports the evaluation of 2″ GaN substrates and 100 mmbulk GaN crystal grown in our pilot production reactor. Recent progress in oxygen reduction enabled growing NEAT GaN substrates with lower residual oxygen, coloration, and optical absorption. The oxygen concentration was approximately 2 × 1018 cm−2, and the optical absorption coefficient was 1.3 cm−1 at 450 nm. Maps of full-width half maximum (FWHM) of X-ray diffraction rocking curveswere generated for grown crystals and finished wafers. The X-ray rocking curve maps confirmed high-quality and uniform microstructure across the entire surface of the bulk crystals and substrates. The average FWHM of the 50 best bulk crystals from the recent batch was 28 ± 4 arcsec for the 002 diffraction and 34 ± 5 arcsec for the 201 diffraction, with an average radius of curvature of 20 m. X-ray topography measured on both sides of the bulk crystals implied that the density of dislocations wasreduced by one order of magnitude during the NEAT growth. A typical NEAT GaN substrate shows dislocation density of about 2 × 105 cm−2.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Electrostatic harvester device

An electrostatic harvester device for charging an energy storage device is provided. The electrostatic harvester device comprises an inductor, a variable capacitor device, a semiconductor device, and a plurality of transistors. The inductor is operable to receive electric charge and store the electric charge. The variable capacitor device is configured to receive electric charge from the inductor and to change capacitance in response to physical stimulation. The semiconductor device is operable to allow electric current to flow from the variable capacitor device. The transistors are operable to connect at least two of the aforementioned devices. At least one of the transistors comprises at least one of gallium nitride or aluminum gallium nitride.

Wilson, Amy Charlene↗
DOE OSTI2024

Thermal scanning probe and laser lithography for patterning nanowire based quantum devices

Semiconductor nanowire (NW) quantum devices offer a promising path for the pursuit and investigation of topologically-protected quantum states, and superconducting and spin-based qubits that can be controlled using electric fields. Theoretical investigations into the impact of disorder on the attainment of dependable topological states in semiconducting nanowires with large spin–orbit coupling and g-factor highlight the critical need for improvements in both growth processes and nanofabrication techniques. In this work, we used a hybrid lithography tool for both the high-resolution thermal scanning probe lithography and high-throughput direct laser writing of quantum devices based on thin InSb nanowires with contact spacing of 200 nm. Electrical characterization demonstrates quasi-ballistic transport. The methodology outlined in this study has the potential to reduce the impact of disorder caused by fabrication processes in quantum devices based on 1D semiconductors.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Semiconductor power device including wire or ribbon bonds over device active region

A semiconductor power device including a base plate; an input lead; an output lead; a field effect transistor (FET) power die disposed over the base plate, wherein the FET power die includes a set of source fingers, a set of drain fingers, and a set of gate fingers disposed directly over an active region, wherein the gate fingers are configured to receive an input signal from the input lead, and wherein the FET power die is configured to process the input signal to generate an output signal at the drain fingers for routing to the output lead; and electrical conductors (wirebonds or ribbons) bonded to the source and/or drain directly over the active region of the FET power die. The electrical conductors produce additional thermal paths between the active region and the base plate for thermal management of the FET power die.

42 ENGINEERING↗
DOE OSTI2024

Atomic Precision Processing of Two-Dimensional Materials for Next-Generation Microelectronics

The growth of the information era economy is driving the pursuit of advanced materials for microelectronics, spurred by exploration into “Beyond CMOS” and “More than Moore” paradigms. Atomically thin 2D materials, such as transition metal dichalcogenides (TMDCs), show great potential for next-generation microelectronics due to their properties and defect engineering capabilities. This perspective delves into atomic precision processing (APP) techniques like atomic layer deposition (ALD), epitaxy, atomic layer etching (ALE), and atomic precision advanced manufacturing (APAM) for the fabrication and modification of 2D materials, essential for future semiconductor devices. Additive APP methods like ALD and epitaxy provide precise control over composition, crystallinity, and thickness at the atomic scale, facilitating high-performance device integration. Subtractive APP techniques, such as ALE, focus on atomic-scale etching control for 2D material functionality and manufacturing. In APAM, modification techniques aim at atomic-scale defect control, offering tailored device functions and improved performance. Achieving optimal performance and energy efficiency in 2D material-based microelectronics requires a comprehensive approach encompassing fundamental understanding, process modeling, and high-throughput metrology. Finally, the outlook for APP in 2D materials is promising, with ongoing developments poised to impact manufacturing and fundamental materials science. Integration with advanced metrology and codesign frameworks will accelerate the realization of next-generation microelectronics enabled by 2D materials.

36 MATERIALS SCIENCE↗
DOE OSTI2024

Science challenges and research opportunities for plasma applications in microelectronics

Low-temperature plasmas (LTPs) are essential to manufacturing devices in the semiconductor industry, from creating extreme ultraviolet photons used in the most advanced lithography to thin film etching, deposition, and surface modifications. It is estimated that 40%–45% of all process steps needed to manufacture semiconductor devices use LTPs in one form or another. LTPs have been an enabling technology in the multidecade progression of the shrinking of device dimensions, often referred to as Moore’s law. New challenges in circuit and device design, novel materials, and increasing demands to achieve environmentally benign processing technologies require advances in plasma technology beyond the current state-of-the-art. The Department of Energy Office of Science Fusion Energy Sciences held a workshop titled Plasma Science for Microelectronics Nanofabrication in August 2022 to discuss the plasma science challenges and technical barriers that need to be overcome to continue to develop the innovative plasma technologies required to support and advance the semiconductor industry. One of the key outcomes of the workshop was identifying a set of priority research opportunities (PROs) to focus attention on the most strategic plasma science challenges to address to benefit the semiconductor industry. For each PRO, scientific challenges and recommended strategies to address those challenges were identified. Furthermore, this article summarizes the PROs identified by the workshop participants.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same

An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.

42 ENGINEERING↗
DOE OSTI2021

Optical coupler for heterogeneous integration

In an optical apparatus, an introduced semiconductor device is heterointegrated on a silicon-based platform containing a silicon-based waveguide. A polymeric waveguide is optically coupled to the introduced semiconductor device and overlies at least a portion of the silicon-based waveguide. The polymeric waveguide is conformed as a multimode interference (MMI) coupler between the introduced semiconductor device and the silicon-based waveguide. At least the polymeric waveguide, and in embodiments, also the silicon-based waveguide, is tapered with a shape that effectuates optical coupling to the silicon-based waveguide.

Gehl, Michael↗
DOE OSTI2021

A perspective on the electro-thermal co-design of ultra-wide bandgap lateral devices

Fundamental research and development of ultra-wide bandgap (UWBG) semiconductor devices are under way to realize next-generation power conversion and wireless communication systems. Devices based on aluminum gallium nitride (AlxGa1-xN, x is the Al composition), ..beta..-phase gallium oxide (..beta..-Ga2O3), and diamond give promise to the development of power switching devices and radio frequency power amplifiers with higher performance and efficiency than commercial wide bandgap semiconductor devices based on gallium nitride (GaN) and silicon carbide (SiC). However, one of the most critical challenges for the successful deployment of UWBG device technologies is to overcome adverse thermal effects that impact the device performance and reliability. Overheating of UWBG devices originates from the projected high power density operation and poor intrinsic thermal properties of AlxGa1-xN and ..beta..-Ga2O3. This Perspective delineates the need and process for the "electro-thermal co-design" of laterally configured UWBG electronic devices and provides a comprehensive review of current state-of-the-art thermal characterization methods, device thermal modeling practices, and both device- and package-level thermal management solutions.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗