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At least 37 records · Page 2

TRIGA: Telecommunications Protocol Processing Subsystem Using Reconfigurable Interoperable Gate Arrays

We present the Telecommunications protocol processing subsystem using Reconfigurable Interoperable Gate Arrays (TRIGA), a novel approach that unifies fault tolerance, error correction coding and interplanetary communication protocol off-loading to implement CCSDS File Delivery Protocol and Datalink layers. The new reconfigurable architecture offers more than one order of magnitude throughput increase while reducing footprint requirements in memory, command and data handling processor utilization, communication system interconnects and power consumption.

protocol processing hardware engine↗

Space-Based Reconfigurable Software Defined Radio Test Bed Aboard International Space Station

The National Aeronautical and Space Administration (NASA) recently launched a new software defined radio research test bed to the International Space Station. The test bed, sponsored by the Space Communications and Navigation (SCaN) Office within NASA is referred to as the SCaN Testbed. The SCaN Testbed is a highly capable communications system, composed of three software defined radios, integrated into a flight system, and mounted to the truss of the International Space Station. Software defined radios offer the future promise of in-flight reconfigurability, autonomy, and eventually cognitive operation. The adoption of software defined radios offers space missions a new way to develop and operate space transceivers for communications and navigation. Reconfigurable or software defined radios with communications and navigation functions implemented in software or VHDL (Very High Speed Hardware Description Language) provide the capability to change the functionality of the radio during development or after launch. The ability to change the operating characteristics of a radio through software once deployed to space offers the flexibility to adapt to new science opportunities, recover from anomalies within the science payload or communication system, and potentially reduce development cost and risk by adapting generic space platforms to meet specific mission requirements. The software defined radios on the SCaN Testbed are each compliant to NASA's Space Telecommunications Radio System (STRS) Architecture. The STRS Architecture is an open, non-proprietary architecture that defines interfaces for the connections between radio components. It provides an operating environment to abstract the communication waveform application from the underlying platform specific hardware such as digital-to-analog converters, analog-to-digital converters, oscillators, RF attenuators, automatic gain control circuits, FPGAs, general-purpose processors, etc. and the interconnections among different radio components.

Communications↗

Fault tolerant hypercube computer system architecture

A fault-tolerant multiprocessor computer system of the hypercube type comprising a hierarchy of computers of like kind which can be functionally substituted for one another as necessary is disclosed. Communication between the working nodes is via one communications network while communications between the working nodes and watch dog nodes and load balancing nodes higher in the structure is via another communications network separate from the first. A typical branch of the hierarchy reporting to a master node or host computer comprises, a plurality of first computing nodes; a first network of message conducting paths for interconnecting the first computing nodes as a hypercube. The first network provides a path for message transfer between the first computing nodes; a first watch dog node; and a second network of message connecting paths for connecting the first computing nodes to the first watch dog node independent from the first network, the second network provides an independent path for test message and reconfiguration affecting transfers between the first computing nodes and the first switch watch dog node. There is additionally, a plurality of second computing nodes; a third network of message conducting paths for interconnecting the second computing nodes as a hypercube. The third network provides a path for message transfer between the second computing nodes; a fourth network of message conducting paths for connecting the second computing nodes to the first watch dog node independent from the third network. The fourth network provides an independent path for test message and reconfiguration affecting transfers between the second computing nodes and the first watch dog node; and a first multiplexer disposed between the first watch dog node and the second and fourth networks for allowing the first watch dog node to selectively communicate with individual ones of the computing nodes through the second and fourth networks; as well as, a second watch dog node operably connected to the first multiplexer whereby the second watch dog node can selectively communicate with individual ones of the computing nodes through the second and fourth networks. The branch is completed by a first load balancing node; and a second multiplexer connected between the first load balancing node and the first and second watch dog nodes, allowing the first load balancing node to selectively communicate with the first and second watch dog nodes.

Madan, Herb S.↗

High-performance mass storage system for workstations

Reduced Instruction Set Computer (RISC) workstations and Personnel Computers (PC) are very popular tools for office automation, command and control, scientific analysis, database management, and many other applications. However, when using Input/Output (I/O) intensive applications, the RISC workstations and PC's are often overburdened with the tasks of collecting, staging, storing, and distributing data. Also, by using standard high-performance peripherals and storage devices, the I/O function can still be a common bottleneck process. Therefore, the high-performance mass storage system, developed by Loral AeroSys' Independent Research and Development (IR&D) engineers, can offload a RISC workstation of I/O related functions and provide high-performance I/O functions and external interfaces. The high-performance mass storage system has the capabilities to ingest high-speed real-time data, perform signal or image processing, and stage, archive, and distribute the data. This mass storage system uses a hierarchical storage structure, thus reducing the total data storage cost, while maintaining high-I/O performance. The high-performance mass storage system is a network of low-cost parallel processors and storage devices. The nodes in the network have special I/O functions such as: SCSI controller, Ethernet controller, gateway controller, RS232 controller, IEEE488 controller, and digital/analog converter. The nodes are interconnected through high-speed direct memory access links to form a network. The topology of the network is easily reconfigurable to maximize system throughput for various applications. This high-performance mass storage system takes advantage of a 'busless' architecture for maximum expandability. The mass storage system consists of magnetic disks, a WORM optical disk jukebox, and an 8mm helical scan tape to form a hierarchical storage structure. Commonly used files are kept in the magnetic disk for fast retrieval. The optical disks are used as archive media, and the tapes are used as backup media. The storage system is managed by the IEEE mass storage reference model-based UniTree software package. UniTree software will keep track of all files in the system, will automatically migrate the lesser used files to archive media, and will stage the files when needed by the system. The user can access the files without knowledge of their physical location. The high-performance mass storage system developed by Loral AeroSys will significantly boost the system I/O performance and reduce the overall data storage cost. This storage system provides a highly flexible and cost-effective architecture for a variety of applications (e.g., realtime data acquisition with a signal and image processing requirement, long-term data archiving and distribution, and image analysis and enhancement).

Chiang, T.↗

Programming methodology for a general purpose automation controller

The General Purpose Automation Controller is a multi-processor architecture for automation programming. A methodology has been developed whose aim is to simplify the task of programming distributed real-time systems for users in research or manufacturing. Programs are built by configuring function blocks (low-level computations) into processes using data flow principles. These processes are activated through the verb mechanism. Verbs are divided into two classes: those which support devices, such as robot joint servos, and those which perform actions on devices, such as motion control. This programming methodology was developed in order to achieve the following goals: (1) specifications for real-time programs which are to a high degree independent of hardware considerations such as processor, bus, and interconnect technology; (2) a component approach to software, so that software required to support new devices and technologies can be integrated by reconfiguring existing building blocks; (3) resistance to error and ease of debugging; and (4) a powerful command language interface.

Sturzenbecker, M. C.↗

Design for an integrated discipline operations control center for Space Station Freedom

This paper presents selected features of a human factors oriented plan for a Space Station Freedom (SSF) ground Discipline Operations Center (DOC) that is integrated with other work areas used by multidisciplinary life scientists. This combined facility is referred to as an integrated DOC or IDOC. This plan is based upon the assumption that there will be a constantly changing array of specialized equipment and procedures used by life sciences principal investigators (PI) on the ground which must be linked to SSF through various DOC systems. Other sites will also be able to communicate with SSF (Anon., 1992). It is also assumed that cost reduction will be a major design consideration and that one integrated structure will be less expensive to build and operate than two separate ones. Since both the DOC personnel and PIs will need to communicate with the flight crew aboard SSF, the general interconnect architecture of the PIs' communication linkage is considered here. Key human factor design elements of this plan include: a candidate facility layout which accommodates three (3), multipurpose, rapidly reconfigurable work areas (suites) and consequent user traffic flow considerations, a multimedia telecommunications support capability, functional (human) traffic flow, optimized internal illumination and acoustics requirements, selected volumetric and safety requirements, and other architectural design parameters.

Haines, Richard F.↗

Standardized Modular Power Interfaces for Future Space Explorations Missions

Earlier studies show that future human explorations missions are composed of multi-vehicle assemblies with interconnected electric power systems. Some vehicles are often intended to serve as flexible multi-purpose or multi-mission platforms. This drives the need for power architectures that can be reconfigured to support this level of flexibility. Power system developmental costs can be reduced, program wide, by utilizing a common set of modular building blocks. Further, there are mission operational and logistics cost benefits of using a common set of modular spares. These benefits are the goals of the Advanced Exploration Systems (AES) Modular Power System (AMPS) project. A common set of modular blocks requires a substantial level of standardization in terms of the Electrical, Data System, and Mechanical interfaces. The AMPS project is developing a set of proposed interface standards that will provide useful guidance for modular hardware developers but not needlessly constrain technology options, or limit future growth in capability. In 2015 the AMPS project focused on standardizing the interfaces between the elements of spacecraft power distribution and energy storage. The development of the modular power standard starts with establishing mission assumptions and ground rules to define design application space. The standards are defined in terms of AMPS objectives including Commonality, Reliability-Availability, Flexibility-Configurability and Supportability-Reusability. The proposed standards are aimed at assembly and sub-assembly level building blocks. AMPS plans to adopt existing standards for spacecraft command and data, software, network interfaces, and electrical power interfaces where applicable. Other standards including structural encapsulation, heat transfer, and fluid transfer, are governed by launch and spacecraft environments and bound by practical limitations of weight and volume. Developing these mechanical interface standards is more difficult but an essential part of defining physical building blocks of modular power. This presentation describes the AMPS projects progress towards standardized modular power interfaces.

Spacecraft Power↗

Space Station power system autonomy demonstration

The Systems Autonomy Demonstration Program (SADP) represents NASA's major effort to demonstrate, through a series of complex ground experiments, the application and benefits of applying advanced automation technologies to the Space Station project. Lewis Research Center (LeRC) and Marshall Space Flight Center (MSFC) will first jointly develop an autonomous power system using existing Space Station testbed facilities at each center. The subsequent 1990 power-thermal demonstration will then involve the cooperative operation of the LeRC/MSFC power system with the Johnson Space Center (JSC's) thermal control and DMS/OMS testbed facilities. The testbeds and expert systems at each of the NASA centers will be interconnected via communication links. The appropriate knowledge-based technology will be developed for each testbed and applied to problems requiring intersystem cooperation. Primary emphasis will be focused on failure detection and classification, system reconfiguration, planning and scheduling of electrical power resources, and integration of knowledge-based and conventional control system software into the design and operation of Space Station testbeds.

Kish, James A.↗

Highly parallel reconfigurable computer architecture for robotic computation having plural processor cells each having right and left ensembles of plural processors

In a computer having a large number of single-instruction multiple data (SIMD) processors, each of the SIMD processors has two sets of three individual processor elements controlled by a master control unit and interconnected among a plurality of register file units where data is stored. The register files input and output data in synchronism with a minor cycle clock under control of two slave control units controlling the register file units connected to respective ones of the two sets of processor elements. Depending upon which ones of the register file units are enabled to store or transmit data during a particular minor clock cycle, the processor elements within an SIMD processor are connected in rings or in pipeline arrays, and may exchange data with the internal bus or with neighboring SIMD processors through interface units controlled by respective ones of the two slave control units.

Fijany, Amir↗

Autonomous In-space Construction, Maintenance, and Reconfiguration Using Programmable Meta-Material

NASA ARC's Coded Structures Laboratory (CSL) is developing autonomous construction, maintenance, and reconfiguration technologies to meet long-duration and deep space infrastructure needs, in accordance with long-term NASA goals of "in-space reliance" and "mass-less exploration." We seek to achieve these capabilities by utilizing a "programmable meta-material" approach that integrates emerging advances in materials (mechanical meta-materials), manufacturing (cooperative mobile robotics), and autonomy (multi-agent planning algorithms). Through the ARMADAS project, we have shown assembly of high-performance engineered cellular materials using multiple cooperating mobile robotic assemblers. In this paper, we describe how such a programmable meta-material architecture may shift the paradigm of how we design, build, manufacture, and operate future space infrastructure and assets. The core of a programmable meta-material architecture consists of 3 main technology sub-areas: the structure, the assembly agents, and the assembly algorithms. We co-design these systems to ensure an adaptable system that can create and reconfigure structures from a base set of building block components. From this core technology, we can branch out and expand the capability of the system through additional secondary component types and robotic agents to perform activities such as inspections, maintenance, repair, payload installation, or perform power and communications interconnect. As these technologies mature, future designers will be able to utilize the system to rapidly integrate and operate assets in space or on planetary surfaces from a set of well-tested part library, or create their own modules to integrate into the system. A core trait to the development of this system is the automation approach. Because of the modular and functional discrete (pixel-like) nature of the structural system, a diverse set of powerful algorithms for analysis, planning, and simulation can be adapted and leveraged to optimize construction, maintenance, and dynamic reorganization (as hardware with programmable form and function). With an ability to free the design space from launch vehicle constraints and fundamentally shift how a mission is designed and conducted, we discuss the influence of a programmable meta-material architecture on mission design, build, and operations. For the "design phase", we discuss project lifecycle effects, costs, time, and performance. For the "build phase", we discuss reusability, ISRU, manufacturing, material logistics, and scalability. And for "operations", we discuss autonomy, maintenance and upgrades, reliability, and reconfiguration. Autonomy and modularity are the primary enabling traits of this system. Engineering systems that utilize a modular and reconfiguration building block approach such as digital communication and computation systems, currently lead all other areas of technology in size and complexity scalability. NASA is extending the benefits and flexibility of digital systems to hardware systems, to optimize materials lifecycle management and expand our space exploration mission capabilities.

in space assembly↗

Stackable Form-Factor Peripheral Component Interconnect Device and Assembly

A stackable form-factor Peripheral Component Interconnect (PCI) device can be configured as a host controller or a master/target for use on a PCI assembly. PCI device may comprise a multiple-input switch coupled to a PCI bus, a multiplexor coupled to the switch, and a reconfigurable device coupled to one of the switch and multiplexor. The PCI device is configured to support functionality from power-up, and either control function or add-in card function.

Somervill, Kevin M.↗

Radiation-Tolerant, SpaceWire-Compatible Switching Fabric

Current and future near-Earth and deep space exploration programs and space defense programs require the development of robust intra-spacecraft serial data transfer electronics that must be reconfigurable, fault-tolerant, and have the ability to operate effectively for long periods of time in harsh environmental conditions. Existing data transfer systems based on state-of-the-art serial data transfer protocols or passive backplanes are slow, power-hungry, and poorly reconfigurable. They provide limited expandability and poor tolerance to radiation effects and total ionizing dose (TID) in particular, which presents harmful threats to modern submicron electronics. This novel approach is based on a standard library of differential cells tolerant to TID, and patented, multi-level serial interface architecture that ensures the reliable operation of serial interconnects without application of a data-strobe or other encoding techniques. This proprietary, high-speed differential interface presents a lowpower solution fully compatible with the SpaceWire (SW) protocol. It replaces a dual data-strobe link with two identical independent data channels, thus improving the system s tolerance to harsh environments through additional double redundancy. Each channel incorporates an automatic line integrity control circuitry that delivers error signals in case of broken or shorted lines.

Katzman, Vladimir↗

Wireless Sensor Network Handles Image Data

To relay data from remote locations for NASA s Earth sciences research, Goddard Space Flight Center contributed to the development of "microservers" (wireless sensor network nodes), which are now used commercially as a quick and affordable means to capture and distribute geographical information, including rich sets of aerial and street-level imagery. NASA began this work out of a necessity for real-time recovery of remote sensor data. These microservers work much like a wireless office network, relaying information between devices. The key difference, however, is that instead of linking workstations within one office, the interconnected microservers operate miles away from one another. This attribute traces back to the technology s original use: The microservers were originally designed for seismology on remote glaciers and ice streams in Alaska, Greenland, and Antarctica-acquiring, storing, and relaying data wirelessly between ground sensors. The microservers boast three key attributes. First, a researcher in the field can establish a "managed network" of microservers and rapidly see the data streams (recovered wirelessly) on a field computer. This rapid feedback permits the researcher to reconfigure the network for different purposes over the course of a field campaign. Second, through careful power management, the microservers can dwell unsupervised in the field for up to 2 years, collecting tremendous amounts of data at a research location. The third attribute is the exciting potential to deploy a microserver network that works in synchrony with robotic explorers (e.g., providing ground truth validation for satellites, supporting rovers as they traverse the local environment). Managed networks of remote microservers that relay data unsupervised for up to 2 years can drastically reduce the costs of field instrumentation and data rec

Source record↗

Optical Interconnection Via Computer-Generated Holograms

Method of free-space optical interconnection developed for data-processing applications like parallel optical computing, neural-network computing, and switching in optical communication networks. In method, multiple optical connections between multiple sources of light in one array and multiple photodetectors in another array made via computer-generated holograms in electrically addressed spatial light modulators (ESLMs). Offers potential advantages of massive parallelism, high space-bandwidth product, high time-bandwidth product, low power consumption, low cross talk, and low time skew. Also offers advantage of programmability with flexibility of reconfiguration, including variation of strengths of optical connections in real time.

Liu, Hua-Kuang↗

Development of a Multi-bus, Multi-source Reconfigurable Stirling Radioisotope Power System Test Bed

The National Aeronautics and Space Administration (NASA) has typically used Radioisotope Thermoelectric Generators (RTG) as their source of electric power for deep space missions. A more efficient and potentially more cost effective alternative to the RTG, the high efficiency 110 watt Stirling Radioisotope Generator 110 (SRG110) is being developed by the Department of Energy (DOE), Lockheed Martin (LM), Stirling Technology Company (STC) and NASA Glenn Research Center (GRC). The SRG110 consists of two Stirling convertors (Stirling Engine and Linear Alternator) in a dual-opposed configuration, and two General Purpose Heat Source (GPHS) modules. Although Stirling convertors have been successfully operated as a power source for the utility grid and as a stand-alone portable generator, demonstration of the technology required to interconnect two Stirling convertors for a spacecraft power system has not been attempted. NASA GRC is developing a Power System Test Bed (PSTB) to evaluate the performance of a Stirling convertor in an integrated electrical power system application. This paper will describe the status of the PSTB and on-going activities pertaining to the PSTB in the NASA Thermal-Energy Conversion Branch of the Power and On-Board Propulsion Technology Division.

Coleman, Anthony S.↗

Electronic Switch Arrays for Managing Microbattery Arrays

Integrated circuits have been invented for managing the charging and discharging of such advanced miniature energy-storage devices as planar arrays of microscopic energy-storage elements [typically, microscopic electrochemical cells (microbatteries) or microcapacitors]. The architecture of these circuits enables implementation of the following energy-management options: dynamic configuration of the elements of an array into a series or parallel combination of banks (subarrarys), each array comprising a series of parallel combination of elements; direct addressing of individual banks for charging/or discharging; and, disconnection of defective elements and corresponding reconfiguration of the rest of the array to utilize the remaining functional elements to obtain the desited voltage and current performance. An integrated circuit according to the invention consists partly of a planar array of field-effect transistors that function as switches for routing electric power among the energy-storage elements, the power source, and the load. To connect the energy-storage elements to the power source for charging, a specific subset of switches is closed; to connect the energy-storage elements to the load for discharging, a different specific set of switches is closed. Also included in the integrated circuit is circuitry for monitoring and controlling charging and discharging. The control and monitoring circuitry, the switching transistors, and interconnecting metal lines are laid out on the integrated-circuit chip in a pattern that registers with the array of energy-storage elements. There is a design option to either (1) fabricate the energy-storage elements in the corresponding locations on, and as an integral part of, this integrated circuit; or (2) following a flip-chip approach, fabricate the array of energy-storage elements on a separate integrated-circuit chip and then align and bond the two chips together.

Mojarradi, Mohammad↗

Magnetic field re-arrangement after prominence eruption

It has long been known that magnetic reconnection plays a fundamental role in a variety of solar events. Although mainly invoked in flare problems, large scale loops interconnecting active regions, evolving coronal hole boundaries, the solar magnetic cycle itself, provide different evidence of phenomena which involve magnetic reconnection. A further example might be given by the magnetic field rearrangement which occurs after the eruption of a prominence. Since most often a prominence reforms after its disappearance and may be observed at about the same position it occupied before erupting, the magnetic field has to undergo a temporary disruption of relax back, via reconnection, to a configuration similar to the previous one. The above sequence of events is best observable in the case of two ribbon (2-R) flares but most probably is associated with all filament eruptions. Even if the explanation of the magnetic field rearrangement after 2-R flares in terms of reconnection is generally accepted, the lack of a 3-dimensional model capable of describing the field reconfiguration, has prevented, up to now, a thorough analysis of its topology as traced by H alpha/x ray loops. A numerical technique is presented which enables oneto predict and visualize the reconnected configuration, at any time, and therefore allows one to make a significant comparison of observations and model predictions throughout the whole process.

Kopp, R. A.↗

SpaceCube v2.0 Space Flight Hybrid Reconfigurable Data Processing System

This paper details the design architecture, design methodology, and the advantages of the SpaceCube v2.0 high performance data processing system for space applications. The purpose in building the SpaceCube v2.0 system is to create a superior high performance, reconfigurable, hybrid data processing system that can be used in a multitude of applications including those that require a radiation hardened and reliable solution. The SpaceCube v2.0 system leverages seven years of board design, avionics systems design, and space flight application experiences. This paper shows how SpaceCube v2.0 solves the increasing computing demands of space data processing applications that cannot be attained with a standalone processor approach.The main objective during the design stage is to find a good system balance between power, size, reliability, cost, and data processing capability. These design variables directly impact each other, and it is important to understand how to achieve a suitable balance. This paper will detail how these critical design factors were managed including the construction of an Engineering Model for an experiment on the International Space Station to test out design concepts. We will describe the designs for the processor card, power card, backplane, and a mission unique interface card. The mechanical design for the box will also be detailed since it is critical in meeting the stringent thermal and structural requirements imposed by the processing system. In addition, the mechanical design uses advanced thermal conduction techniques to solve the internal thermal challenges.The SpaceCube v2.0 processing system is based on an extended version of the 3U cPCI standard form factor where each card is 190mm x 100mm in size The typical power draw of the processor card is 8 to 10W and scales with application complexity. The SpaceCube v2.0 data processing card features two Xilinx Virtex-5 QV Field Programmable Gate Arrays (FPGA), eight memory modules, a monitor FPGA with analog monitoring, Ethernet, configurable interconnect to the Xilinx FPGAs including gigabit transceivers, and the necessary voltage regulation. The processor board uses a back-to-back design methodology for common parts that maximizes the board real estate available. This paper will show how to meet the IPC 6012B Class 3A standard with a 22-layer board that has two column grid array devices with 1.0mm pitch. All layout trades such as stack-up options, via selection, and FPGA signal breakout will be discussed with feature size results. The overall board design process will be discussed including parts selection, circuit design, proper signal termination, layout placement and route planning, signal integrity design and verification, and power integrity results. The radiation mitigation techniques will also be detailed including configuration scrubbing options, Xilinx circuit mitigation and FPGA functional monitoring, and memory protection.Finally, this paper will describe how this system is being used to solve the extreme challenges of a robotic satellite servicing mission where typical space-rated processors are not sufficient enough to meet the intensive data processing requirements. The SpaceCube v2.0 is the main payload control computer and is required to control critical subsystems such as autonomous rendezvous and docking using a suite of vision sensors and object avoidance when controlling two robotic arms.

Xilinx FPGA↗