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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS2002

Mountain-Top-to-Mountain-Top Optical Link Demonstration

A mountain-top-to-mountain-top optical communications demonstration was conducted between the JPL Table Mountain Facility (TMF), Wrightwood, California, and Strawberry Peak (SP), Lake Arrowhead, California, during the months of August and September of 2000. The link was nearly horizontal at an altitude of 2 km and spanned a range of 46.8 km. A 780-nm multibeam beacon broadcast from TMF was received by the JPL Optical Communications Demonstrator (OCD) located at SP. The received beacon was utilized as a pointing reference to retransmit an 852-nm communications laser beam, modulated at 400 Mb/s by a PN7 pseudo-random bit stream (PRBS) sequence. The long atmospheric path resulted in atmospheric-turbulence-induced angle-of-arrival fluctuations of the beacon at the OCD aperture. A .ne-steering control loop was used to track the resulting beacon centroid motion and update the pointing of the communications laser beam transmitted from SP to TMF. Fried parameters, or r0, inferred from focal spot sizes received at SP were 4 to 5 cm whereas, using the spot sizes received at TMF, they were 2 to 3 cm. In both cases, theory predicts larger r0 values. The predicted angle-of-arrival fluctuations compare well with measured rms displacements exhibited by the focal spots at either end of the link. An uncompensated error of ~1.1 rad in the x-axis and ~2 rad in the y-axis was obtained using centroid data logged by the OCD. Average bit-error rates of 10-5 were recorded for extended periods of time. An atmospheric coherence length r0 of 3 to 5 cm was inferred using the focal-plane spot size measured on the CCD tracking sensor and compared to a predicted value of 5 to 7 cm using reasonable atmospheric models. The irradiance bounds required for the CCD tracking sensor to perform centroiding was found to range from 2000 to 3000 integrated pixel counts, although a more reliable range was 600 to 3000, indicating a dynamic range of 6 to 11 dB. The motion of the spot on the focal plane was also recorded and yielded rms angle-of-arrival-induced focal-plane displacement of 9 to 11 m, compared to a predicted value of 7.8 to 11 m. The irradiance measurements made with the OCD clearly indicate that best tracking performance is obtained when the mean received signal is 2000 to 2200 counts. The best tracking performance resulted in an rms uncompensated error of 1.1 rad. The uncompensated error appeared to increase with either an increase or decrease in mean beacon-signal level. The rms uncompensated error determined by deriving the beacon displacement power spectral density from the beacon centroid-versustime data and the rejection function of the control loop yielded a higher value of 3.4 rad.

Biswas, A.↗
NASA NTRS1984

Fast decoding techniques for extended single-and-double-error-correcting Reed Solomon codes

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. For example, some 256K-bit dynamic random access memories are organized as 32K x 8 bit-bytes. Byte-oriented codes such as Reed Solomon (RS) codes provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special high speed decoding techniques for extended single and double error correcting RS codes. These techniques are designed to find the error locations and the error values directly from the syndrome without having to form the error locator polynomial and solve for its roots.

Costello, D. J., Jr.↗
NASA NTRS1979

Electrical Characterization of the RCA CDP1822SD Random Access Memory, Volume 1, Appendix a

Electrical characteristization tests were performed on 35 RCA CDP1822SD, 256-by-4-bit, CMOS, random access memories. The tests included three functional tests, AC and DC parametric tests, a series of schmoo plots, rise/fall time screening, and a data retention test. All tests were performed on an automated IC test system with temperatures controlled by a thermal airstream unit. All the functional tests, the data retention test, and the AC and DC parametric tests were performed at ambient temperatures of 25 C, -20 C, -55 C, 85 C, and 125 C. The schmoo plots were performed at ambient temperatures of 25 C, -55 C, and 125 C. The data retention test was performed at 25 C. Five devices failed one or more functional tests and four of these devices failed to meet the expected limits of a number of AC parametric tests. Some of the schmoo plots indicated a small degree of interaction between parameters.

Klute, A.↗
NASA NTRS1979

Electrical Evaluation of RCA MWS5001D Random Access Memory, Volume 1

Electrical characterization and qualification tests were performed on the RCA MWS5001D, 1024 by 1-bit, CMOS, random access memory. Characterization tests were performed on five devices. The tests included functional tests, AC parametric worst case pattern selection test, determination of worst-case transition for setup and hold times and a series of schmoo plots. The qualification tests were performed on 32 devices and included a 2000 hour burn in with electrical tests performed at 0 hours and after 168, 1000, and 2000 hours of burn in. The tests performed included functional tests and AC and DC parametric tests. All of the tests in the characterization phase, with the exception of the worst-case transition test, were performed at ambient temperatures of 25, -55 and 125 C. The worst-case transition test was performed at 25 C. The preburn in electrical tests were performed at 25, -55, and 125 C. All burn in endpoint tests were performed at 25, -40, -55, 85, and 125 C.

Klute, A.↗
NASA NTRS1978

A wide bandwidth CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. CCD shift register memories (8K bit) were used to construct a feasibility model 128 K-bit buffer memory system. Serial data that can have rates between 150 kHz and 4.0 MHz can be stored in 4K-bit, randomly-accessible memory blocks. Peak power dissipation during a data transfer is less than 7 W, while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. System expansion to accommodate parallel inputs or a greater number of memory blocks can be performed in a modular fashion. Since the control logic does not increase proportionally to increase in memory capacity, the power requirements per bit of storage can be reduced significantly in a larger system.

Siemens, K.↗
NASA NTRS2010

Scaled CMOS Technology Reliability Users Guide

The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. A methodology on how to accomplish this and techniques for deriving the expected product-level reliability on commercial memory products are provided.Competing mechanism theory and the multiple failure mechanism model are applied to the experimental results of scaled SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope (beta)=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and their key parameters.

Microelectronics Reliability↗
NASA NTRS1990

32-Bit-Wide Memory Tolerates Failures

Electronic memory system of 32-bit words corrects bit errors caused by some common type of failures - even failure of entire 4-bit-wide random-access-memory (RAM) chip. Detects failure of two such chips, so user warned that ouput of memory may contain errors. Includes eight 4-bit-wide DRAM's configured so each bit of each DRAM assigned to different one of four parallel 8-bit words. Each DRAM contributes only 1 bit to each 8-bit word.

Buskirk, Glenn A.↗
NASA NTRS1977

Minimax decoding of cyclic block codes

A minimax decoding algorithm utilizing soft bit detection of an (n,k) cyclic block code is described which will permit the correction of up to n-k bit errors interspersed at random locations throughout the block. The decoding solution consists of: (1) identifying the ordered soft bit set and, (2) finding the minimum order solution to the resulting syndrome equations where the nonzero error vector components are constrained to be a subset of the soft bit set. An efficient implementation of the decoding operation is described. In essence, this algorithm focuses the correction capability of the code on those bit positions which have the lowest a posteriori probabilities of correct detection.

Greene, E. P.↗
NASA NTRS2004

Four-Channel PC/104 MIL-STD-1553 Circuit Board

The mini bus interface card (miniBIC) is the first four-channel electronic circuit board that conforms to MIL-STD-1553 and to the electrical-footprint portion of PC/104. [MIL-STD-1553 is a military standard that encompasses a method of communication and electrical- interface requirements for digital electronic subsystems connected to a data bus. PC/104 is an industry standard for compact, stackable modules that are fully compatible (in architecture, hardware, and software) with personal-computer data- and power-bus circuitry.] Prior to the development of the miniBIC, only one- and two-channel PC/104 MIL-STD-1553 boards were available. To obtain four channels, it was necessary to include at least two boards in a PC/104 stack. In comparison with such a two-board stack, the miniBIC takes up less space, consumes less power, and is more reliable. In addition, the miniBIC includes 32 digital input/output channels. The miniBIC (see figure) contains four MIL-STD-1553B hybrid integrated circuits (ICs), four transformers, a field-programmable gate array (FPGA), and an Industry Standard Architecture (ISA) interface. Each hybrid IC includes a MILSTD-1553 dual transceiver, memory-management circuitry, processor interface logic circuitry, and 64Kx16 bits of shared static random access memory. The memory is used to configure message and data blocks. In addition, 23 16-bit registers are available for (1) configuring the hybrid IC for, and starting it in, various modes of operation; (2) reading the status of the functionality of the hybrid IC; and (3) resetting the hybrid IC to a known state. The miniBIC can operate as a remote terminal, bus controller, or bus monitor. The FPGA provides the chip-select and data-strobe signals needed for operation of the hybrid ICs. The FPGA also receives interruption signals and forwards them to the ISA bus. The ISA interface connects the address, data, and control interfaces of the hybrid ICs to the ISA backplane. Each channel is, in effect, a MIL-STD-1553 interface that can operate either independently of the others or else as a redundant version of one of the others. The transformer in each channel provides electrical isolation between the rest of the miniBIC circuitry and the bus to which that channel is connected.

Cox, Gary L.↗
NASA NTRS2018

Randomizer for High Data Rates

NASA as well as a number of other space agencies now recognize that the current recommended CCSDS randomizer used for telemetry (TM) is too short. When multiple applications of the PN8 Maximal Length Sequence (MLS) are required in order to fully cover a channel access data unit (CADU), spectral problems in the form of elevated spurious discretes (spurs) appear. Originally the randomizer was called a bit transition generator (BTG) precisely because it was thought that its primary value was to insure sufficient bit transitions to allow the bit/symbol synchronizer to lock and remain locked. We, NASA, have shown that the old BTG concept is a limited view of the real value of the randomizer sequence and that the randomizer also aids in signal acquisition as well as minimizing the potential for false decoder lock. Under the guidelines we considered here there are multiple maximal length sequences under GF(2) which appear attractive in this application. Although there may be mitigating reasons why another MLS sequence could be selected, one sequence in particular possesses a combination of desired properties which offsets it from the others.

randomizer↗
NASA NTRS2018

Randomizer for High Data Rates

NASA as well as a number of other space agencies now recognize that the current recommended CCSDS randomizer used for telemetry (TM) is too short. When multiple applications of the PN8 Maximal Length Sequence (MLS) are required in order to fully cover a channel access data unit (CADU), spectral problems in the form of elevated spurious discretes (spurs) appear. Originally the randomizer was called a bit transition generator (BTG) precisely because it was thought that its primary value was to insure sufficient bit transitions to allow the bit/symbol synchronizer to lock and remain locked. We, NASA, have shown that the old BTG concept is a limited view of the real value of the randomizer sequence and that the randomizer also aids in signal acquisition as well as minimizing the potential for false decoder lock. Under the guidelines we considered here there are multiple maximal length sequences under GF(2) which appear attractive in this application. Although there may be mitigating reasons why another MLS sequence could be selected, one sequence in particular possesses a combination of desired properties which offsets it from the others.

primitive polynomials↗
NASA NTRS1991

Magnet/Hall-Effect Random-Access Memory

In proposed magnet/Hall-effect random-access memory (MHRAM), bits of data stored magnetically in Perm-alloy (or equivalent)-film memory elements and read out by using Hall-effect sensors to detect magnetization. Value of each bit represented by polarity of magnetization. Retains data for indefinite time or until data rewritten. Speed of Hall-effect sensors in MHRAM results in readout times of about 100 nanoseconds. Other characteristics include high immunity to ionizing radiation and storage densities of order 10(Sup6)bits/cm(Sup 2) or more.

Wu, Jiin-Chuan↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype ICs with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3-and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient.

Silicon Carbide↗
NASA NTRS2015

Processing and Prolonged 500 C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC's with two levels of metal interconnect capable of prolonged operation at 500 C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 C. A 3-stage oscillator functioned for over 3000 hours at 500 C in air ambient. Improved reproducibility remains to be accomplished.

JFET↗
NASA NTRS1983

Massively parallel processor computer

An apparatus for processing multidimensional data with strong spatial characteristics, such as raw image data, characterized by a large number of parallel data streams in an ordered array is described. It comprises a large number (e.g., 16,384 in a 128 x 128 array) of parallel processing elements operating simultaneously and independently on single bit slices of a corresponding array of incoming data streams under control of a single set of instructions. Each of the processing elements comprises a bidirectional data bus in communication with a register for storing single bit slices together with a random access memory unit and associated circuitry, including a binary counter/shift register device, for performing logical and arithmetical computations on the bit slices, and an I/O unit for interfacing the bidirectional data bus with the data stream source. The massively parallel processor architecture enables very high speed processing of large amounts of ordered parallel data, including spatial translation by shifting or sliding of bits vertically or horizontally to neighboring processing elements.

Fung, L. W.↗
NASA NTRS1974

Basic memory module

Construction and electrical characterization of the 4096 x 2-bit Basic Memory Module (BMM) are reported for the Space Ultrareliable Modular Computer (SUMC) program. The module uses four 2K x 1-bit N-channel FET, random access memory chips, called array chips, and two sense amplifier chips, mounted and interconnected on a ceramic substrate. Four 5% tolerance power supplies are required. At the Module, the address, chip select, and array select lines require a 0-8.5 V MOS signal level. The data output, read-strobe, and write-enable lines operate at TTl levels. Although the module is organized as 4096 x 2 bits, it can be used in a 8196 x 1-bit application with appropriate external connections. A 4096 x 1-bit organization can be obtained by depopulating chips.

Tietze, F. C.↗
NASA NTRS1968

Pseudonoise (PN) synchronization of data system with derivation of clock frequency from received signal for clocking receiver PN generator

A digital communicating system for automatically synchronizing signals for data detection is described. The systems consists of biphase modulating a subcarrier frequency by the binary data and transmitting a carrier phase modulated by this signal to a receiver, where coherent phase detection is employed to recover the subcarrier. Data detection is achieved by providing, in the receiver, a demodulated reference which is in synchronism with the unmodulated subcarrier in transmitting system. The output of the detector is passed through a matched filter where the signal is integrated over a bit period. As a result, random noise components are averaged out, so that the probability of detecting the correct data transmitted is maximized.

Couvillon, L. A., Jr.↗