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A magic-state-free architecture for early fault-tolerant quantum computers
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Quantum Software Engineering (Dagstuhl Seminar 24512)
The Dagstuhl Seminar 24512 on "Quantum Software Engineering" was held from December 15 to 20, 2024. It brought together 26 participants from industry and academia from 13 different countries, including senior and junior researchers as well as practitioners in the field of Quantum Software Engineering. The aim of the seminar was to advance software engineering methods and tools for the engineering of hybrid quantum systems by promoting personal interaction and open discussion among researchers who are already working in this emerging area of knowledge. The first day of the seminar was devoted to the topic "When software engineering meets quantum mechanics", while the second day focused on "Quantum software engineering and its challenges." During both days, 16 invited presentations were given. The rest of the seminar was organized into three working groups to address the topics "Quantum Software Design, Modelling and Architecturing", "Adaptive Hybrid Quantum Systems", and "Quantum Software Quality Assurance". The seminar was a very fruitful experience for all participants both in terms of scientific outcomes and in terms of the personal relationships that were generated to jointly address future experiences.
Logical error rates for the surface code under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions
With fault-tolerant quantum computing (FTQC) on the horizon, it is critical to understand sources of logical errors in plausible hardware implementations of quantum error-correcting codes. Detailed error modeling of computational instructions on particular FTQC architectures will enable the better prediction of error propagation in FT-encoded quantum circuits while revealing where greater attention is needed in hardware design. In this work, we consider logical error rates for the surface code implemented on a hypothetical grid-based trapped-ion quantum charge-coupled device architecture. Specifically, we construct logical channels for the idling surface code and examine its diamond error under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions. We include the coherent dephasing noise that is known to accumulate during physical qubit idling and transport in these systems, determining idling and transport durations using the time-resolved output of an open-source trapped-ion surface code compiler. To estimate expectation values of logical Pauli observables following hardware circuits containing non-Clifford sources of noise, we utilize a Monte Carlo technique to sample from an underlying quasiprobability distribution of Clifford circuits that we independently simulate in a phase-sensitive fashion. We verify error suppression up to code distance 𝑑 = 11 at coherent dephasing rates near and below those of current-generation trapped-ion quantum computers and find that logical error rates align with those of analogous fully stochastic simulations in this regime. Exploring higher dephasing rates at 𝑑 = 3−5, we find evidence for growing coherent rotations about all three logical Pauli axes, increased diagonal logical error process matrix elements relative to those of stochastic simulations, and a reduced dephasing rate threshold. Overall, our work paves a way toward realistic hardware emulation of small fault-tolerant quantum processes, e.g., members of an FTQC instruction set.
Unconventional compute methods and future challenges for superconducting digital computing
Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.
Fault-Tolerant Operation of Bosonic Qubits with Discrete-Variable Ancillae
Fault-tolerant quantum computation with bosonic qubits often necessitates the use of noisy discrete-variable ancillae. In this work, we establish a comprehensive and practical fault-tolerance framework for such a hybrid system and synthesize it with fault-tolerant protocols by combining bosonic quantum error correction (QEC) and advanced quantum control techniques. We introduce essential building blocks of error-corrected gadgets by leveraging ancilla-assisted bosonic operations using a generalized variant of path-independent quantum control. Using these building blocks, we construct a universal set of error-corrected gadgets that tolerate a single-photon loss and an arbitrary ancilla fault for four-legged cat qubits. Notably, our construction requires only dispersive coupling between bosonic modes and ancillae, as well as beam-splitter coupling between bosonic modes, both of which have been experimentally demonstrated with strong strengths and high accuracy. Moreover, each error-corrected bosonic qubit is comprised of only a single bosonic mode and a three-level ancilla, featuring the hardware efficiency of bosonic QEC in the full fault-tolerant setting. We numerically demonstrate the feasibility of our schemes using current experimental parameters in the circuit-QED platform. Finally, we present a hardware-efficient architecture for fault-tolerant quantum computing by concatenating the four-legged cat qubits with an outer qubit code utilizing only beam-splitter couplings. Our estimates suggest that the overall noise threshold can be reached using existing hardware. These developed fault-tolerant schemes extend beyond their applicability to four-legged cat qubits and can be adapted for other rotation-symmetrical codes, offering a promising avenue toward scalable and robust quantum computation with bosonic qubits. Published by the American Physical Society 2024
High-fidelity remote entanglement of trapped atoms mediated by time-bin photons
Abstract Photonic interconnects between quantum processing nodes are likely the only way to achieve large-scale quantum computers and networks. The bottleneck in such an architecture is the interface between well-isolated quantum memories and flying photons. We establish high-fidelity entanglement between remotely separated trapped atomic qubit memories, mediated by photonic qubits stored in the timing of their pulses. Such time-bin encoding removes sensitivity to polarization errors, enables long-distance quantum communication, and is extensible to quantum memories with more than two states. Using a measurement-based error detection process and suppressing a fundamental source of error due to atomic recoil, we achieve an entanglement fidelity of 97% and show that fundamental limits due to atomic recoil still allow fidelities in excess of 99.9%.
Analog-to-digital converter based on voltage-controlled superconducting devices
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.
LLRF System Analysis for the Fermilab PIP-II LINAC
Developing long-lived quantum processing units (QPUs) capable of supporting high-fidelity quantum operations is a crucial challenge on the path toward fault-tolerant quantum computing. TESLA-shaped superconducting RF (SRF) cavities, known for photon relaxation times on the order of seconds, provide an excellent foundation for 3D QPUs and quantum memory. This talk presents a novel design that leverages TESLA cavity modes coupled to ancillary transmon qubits, optimized to preserve coherence and control. By carefully engineering the package geometry, optimizing Hamiltonian parameters, and minimizing lossy participation ratios, we achieve photon relaxation times of over 16 ms and 20 ms for the two cavity modes, representing a significant improvement over previous multimode quantum memories. Despite the reduced coupling between the qubit and cavity modes, which is necessary to preserve long lifetimes, the platform supports robust and universal control schemes that are not limited by low coupling strength. We will also discuss how this architecture can lead to scalable, modular quantum computing systems.
Hybrid Oscillator-Qubit Quantum Processors: Instruction Set Architectures, Abstract Machine Models, and Applications
This tutorial offers a pedagogical guide to hybrid quantum processors that integrate discrete-variable (DV) qubits and continuous-variable (CV) oscillators. Aimed at computer scientists, engineers, and physicists, it provides an overview of the experimental, algorithmic, and architectural aspects of this novel and rapidly developing hardware model. Experimental realizations of this model include superconducting, trapped-ion, and neutral-atom platforms. By combining DV and CV components, hybrid oscillator-qubit processors enable a powerful new paradigm that offers complementary strengths for quantum control, error correction, computation, and simulation. Working toward the goal of a full-stack system connecting applications to CV-DV hardware, we define and formulate abstract machine models and instruction set architectures. These essential abstractions enable codesign of hardware and software, and resource estimation for exploring the potential of current and future hardware for computational and simulation tasks. Using these abstractions, we present both new and existing examples that illustrate the benefits of hybrid CV-DV processors relative to traditional DV-only hardware in computation as well as quantum simulation of physical models. Examples include algorithms for transferring states between DV and CV systems, performing the quantum Fourier transform, and simulation of lattice gauge theories. Relative to qubit-only hardware, the bosonic degrees of freedom natively available in hybrid architectures can substantially reduce the circuit complexity of simulations for physical models containing bosons. A key technique is the extension of quantum signal processing ideas to CV-DV systems. This work is intended to serve as a timely and comprehensive guide to this relatively unexplored yet promising approach to quantum computation and to provide a road map to guide future development.
Uncertain quantum computing futures and potential energy and physical resource impacts at scale
Considerable attention has recently focused on the vast energy and water demands of supercomputing, namely large-scale data centers that underpin artificial intelligence (AI), one of the great disruptors of contemporary society. Looking ahead some years from now, quantum computing is poised to disrupt established computing paradigms once again. Scientists and engineers are now working intensely to bring this century-old dream of physicists to fruition. Yet, as quantum computers begin to be integrated with classical supercomputing architectures, the implications for energy and physical resource use also need to be understood, especially how they compare to today’s AI data centers. These impacts have not yet been quantified by the research community – a notable gap in the literature, even if commercial-scale deployment of Quantum-Accelerated Computing Infrastructure (QuACI) is not expected for a few more years. This study is the first to conduct such an assessment. Using publicly available information from academic sources and private industry, we characterize multiple configurations of superconducting qubit-based, fault-tolerant quantum computers (FTQC) that could plausibly be deployed at scale in the 2030s and into the 2040s. By parameterizing these FTQC systems at a process level, we conduct a prospective scenario analysis to quantify their energy and physical resource needs. While these estimates are uncertain, given the current state of quantum technologies and their unknown future trajectories, important insights can already be drawn. One key finding is that while the electricity needs for a fleet of FTQCs are within the bounds of previous modeling studies that have explored high electricity demand futures, the needs for certain physical resources, namely water and helium-3, could pose bottlenecks to QuACI scale-up.
Cybersecurity Considerations for Emerging Energy Technologies
AI, cloud computing, post-quantum cryptography, zero-trust architectures, microgrids, and virtual power plants. What do these things have in common? They are all emerging technologies in the clean energy space that will be a critical part of grid modernization efforts. As we work towards clean energy and decarbonization targets, these technologies, developed to solve real-world problems, will help us reach goals and achieve new efficiencies as the paradigm of grid operation shifts. However, there are growing concerns about the cybersecurity risks associated with these trending topics as they are used in critical infrastructure applications. This talk will cover gaps, challenges, and opportunities for the secure implementation of grid modernization solutions and novel energy applications of state-of-the-art networking and communications. Proactive risk mitigation strategies, including the application of cyber-informed engineering, will be discussed. Practical applications of these techniques will help provide countermeasures to the impact of cyberattacks on critical infrastructure technologies in a new, digitized grid landscape.
Distributed quantum approximate optimization algorithm on a quantum-centric supercomputing architecture
Quantum approximate optimization algorithm (QAOA) has shown promise in solving combinatorial optimization problems by providing quantum speedup on near-term gate-based quantum computing systems. However, QAOA faces challenges for high-dimensional problems due to the large number of qubits required and the complexity of deep circuits, limiting its scalability for real-world applications. In this study, we present a distributed QAOA (DQAOA), which leverages distributed computing strategies to decompose a large computational workload into smaller tasks that require fewer qubits and shallower circuits than are necessary to solve the original problem. These sub-problems are processed using a combination of high-performance and quantum computing resources. The global solution is iteratively updated by aggregating sub-solutions, allowing convergence toward the optimal solution. We demonstrate that DQAOA can handle considerably large-scale optimization problems (e.g., 1000-bit problem), achieving a high solution quality and short time-to-solution, outperforming existing strategies. Furthermore, we realize DQAOA on a quantum-centric supercomputing architecture, paving the way for practical applications of gate-based quantum computers in real-world optimization tasks. To extend DQAOA’s applicability to materials science, we further develop an active learning algorithm integrated with our DQAOA (AL-DQAOA), which involves machine learning, DQAOA, and active data production in an iterative loop. We successfully optimize photonic structures using AL-DQAOA, indicating that solving real-world optimization problems using gate-based quantum computing is feasible. We expect the proposed DQAOA to be applicable to a wide range of optimization problems and AL-DQAOA to find broader applications in material design.
QECC-Synth: A Layout Synthesizer for Quantum Error Correction Codes on Sparse Architectures
Quantum Error Correction (QEC) codes are essential for achieving fault-tolerant quantum computing (FTQC). However, their implementation faces significant challenges due to disparity between required dense qubit connectivity and sparse hardware architectures. Current approaches often either underutilize QEC circuit features or focus on manual designs tailored to specific codes and architectures, limiting their capability and generality. In response, we introduce QECC-Synth, an automated compiler for QEC code implementation that addresses these challenges. We leverage the ancilla bridge technique tailored to the requirements of QEC circuits and introduces a systematic classification of its design space flexibilities. We then formalize this problem using the MaxSAT framework to optimize these flexibilities. Evaluation shows that our method significantly outperforms existing methods while demonstrating broader applicability across diverse QEC codes and hardware architectures.
SIREN: Scaling Ion-Traps by REquiring iNnovative Heterogenous Integration
The SIREN (Scaling Ion Traps by Requiring iNnovative heterogenous integration) project explores the feasibility of heterogeneous integration (HI) as a transformative approach to scaling ion traps, a critical technology for advancing quantum computers and atomic clocks. Traditional ion trap architectures face significant challenges in scalability due to limitations in optical access, fabrication techniques, and material constraints. SIREN addresses these challenges by leveraging HI, which combines different materials and fabrication processes to create more complex and efficient ion trap structures. HI integrated structures can be manufactured without compromising the process to maintain compatibility to ion traps. This project focuses on integrating a separately fabricated waveguide with a fully functional ion trap. The respective alignment between the pieces needs to be accurate to less than 2 µm to ensure that the light from the waveguide can overlap with the trapping region. The fine alignment must also be maintained through an ultra-high vacuum bake, a critical step in preparing an ion trap experiment. The project's outcomes suggest that heterogeneous integration is a promising pathway for overcoming current scalability barriers, paving the way for the next generation of quantum technologies. SIREN's findings contribute significantly to the field, offering a scalable solution that could accelerate the development of practical quantum computers and highly accurate atomic clocks.
Multi-Agent Control Planes for Quantum Networks: A Scalable Architecture for Autonomous Quantum Internet Management
Quantum networks are expected to enable distributed quantum computing, secure communication, and global entanglement distribution. However, operating such networks presents significant challenges, including stochastic quantum processes, fragile entanglement resources, dynamic topology, and cross-layer control requirements. Current quantum network control architectures largely rely on centralized or hierarchical controllers inspired by classical software-defined networking (SDN). While effective for small testbeds, these approaches face scalability, latency, and reliability limitations as quantum networks grow. This paper proposes a multi-agent control plane architecture for quantum networks. In this design, intelligent software agents operate at quantum nodes, repeaters, and orchestration layers, collectively managing entanglement generation, routing, purification, and scheduling. The distributed intelligence of the agent system allows the network to adapt dynamically to quantum hardware variability and environmental noise. We argue that multi-agent systems provide significant advantages over centralized control approaches, including scalability, resilience, local autonomy, and real-time adaptation. The paper discusses architectural design principles, agent coordination mechanisms, and research challenges in deploying multi-agent control planes for the emerging quantum Internet.
Quantum Computing Strategy 2026
Quantum computing (QC) is a rapidly maturing technology with the potential for revolutionary impacts on stockpile stewardship science and national security. Recent developments in fault-tolerant architectures have compressed vendor roadmaps, and predictions of a production-ready quantum computer by the mid-2030s are becoming increasingly credible. This strategy provides a roadmap for integrating QC into the Advanced Simulation and Computing (ASC) program by investing in four strategic focus areas: 1. Develop Capabilities in Mission-Relevant Quantum Applications: ASC will prioritize developing quantum-ready applications in mission areas that have shown significant promise for quantum advantage, including simulations of materials in extreme environments, nuclear dynamics, solving linear and nonlinear partial differential equations, and uncertainty quantification. These applications directly support stockpile stewardship science and modernization objectives. 2. Conduct R&D in Algorithms, Software, and Hardware: Sustained research into quantum algorithms, robust software tools, and quantum hardware is essential. ASC will develop efficient quantum algorithms; invest in quantum compilers, debuggers, and performance tools; and explore specialized quantum hardware tailored to NNSA’s unique requirements. 3. Engage with Vendors and Partners: Early and active collaboration with commercial quantum hardware vendors and academic partners is critical. Through testbeds, co-design agreements, and quantum demonstration facilities, ASC will influence hardware design, gain early access to emerging technologies, and ensure that quantum platforms evolve to meet mission needs. 4. Build Knowledge, Experience, and Workforce: Expanding and upskilling the quantum-trained workforce is essential to long-term success. This includes hiring, internal training, university outreach, and postdoctoral support to ensure ASC maintains the expertise required to operate, program, and integrate quantum systems as they become available. While quantum computing will never replace classical computing, it has the potential to solve certain problems with speed and accuracy that would be unachievable using any conceivable classical high-performance computing (HPC) system. By investing strategically in QC, ASC will help propel the emergent QC industry, maintain U.S. technological leadership, ensure mission readiness, and position itself to rapidly adopt quantum technologies as they mature.
Carbon-Based Quantum Information Science with Symmetry Protected Topological States (Final Report, DOE-BES award DE-SC0023105)
This research program established the scientific foundation for the rational, bottom-up design, synthesis, isolation, and investigation of symmetry-protected topological (SPT) electron spin qubits embedded in graphene nanoribbons (GNRs). The work focused on integrating atomically precise low-dimensional carbon nanostructures with emerging quantum logic architectures, providing a pathway toward scalable quantum materials for next-generation computing and sensing technologies. A central component of the program was the elucidation of fundamental relationships between real-space molecular architecture, local spin density distributions, electronic band dispersion, and energy level alignment in atomically precise GNR systems. These correlations define key operational parameters of SPT qubits and were systematically investigated to establish quantitative benchmarks against established molecular and solid-state spin qubit platforms. Attention was given to properties critical for quantum device performance, e.g. decoherence times, spectral sharpness of energy transitions, and tunable exchange interactions between spin states. The research demonstrated that these parameters can be engineered with atomic precision through scalable bottom-up synthetic strategies. Theory-guided design played a central role in identifying candidate structures hosting topologically protected spin states. Experimental validation was performed using both ensemble measurements and single-molecule characterization. In addition to advances in quantum materials synthesis, the program developed and applied spin-sensitive scanning probe microscopy techniques capable of directly probing quantum states and dynamic processes with atomic-scale spatial resolution. These capabilities enabled direct observation and characterization of quantum structures at the single-atom level. While the research activities were primarily hypothesis-driven fundamental investigations, the program adopted a comprehensive materials-by-design framework aimed at translating scientific discoveries into technological concepts compatible with scalable and intelligent manufacturing approaches.