Engineering PapersSearch

SEARCH · Engineering Papers

Results for “programmable synthesis”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

31 records · Page 2

Flexible digital modulation and coding synthesis for satellite communications

An architecture and a hardware prototype of a flexible trellis modem/codec (FTMC) transmitter are presented. The theory of operation is built upon a pragmatic approach to trellis-coded modulation that emphasizes power and spectral efficiency. The system incorporates programmable modulation formats, variations of trellis-coding, digital baseband pulse-shaping, and digital channel precompensation. The modulation formats examined include (uncoded and coded) binary phase shift keying (BPSK), quatenary phase shift keying (QPSK), octal phase shift keying (8PSK), 16-ary quadrature amplitude modulation (16-QAM), and quadrature quadrature phase shift keying (Q squared PSK) at programmable rates up to 20 megabits per second (Mbps). The FTMC is part of the developing test bed to quantify modulation and coding concepts.

Vanderaar, Mark

Video image processing

Current technology projections indicate a lack of availability of special purpose computing for Space Station applications. Potential functions for video image special purpose processing are being investigated, such as smoothing, enhancement, restoration and filtering, data compression, feature extraction, object detection and identification, pixel interpolation/extrapolation, spectral estimation and factorization, and vision synthesis. Also, architectural approaches are being identified and a conceptual design generated. Computationally simple algorithms will be research and their image/vision effectiveness determined. Suitable algorithms will be implimented into an overall architectural approach that will provide image/vision processing at video rates that are flexible, selectable, and programmable. Information is given in the form of charts, diagrams and outlines.

Murray, N. D.

Using Pipelined XNOR Logic to Reduce SEU Risks in State Machines

Single-event upsets (SEUs) pose great threats to avionic systems state machine control logic, which are frequently used to control sequence of events and to qualify protocols. The risks of SEUs manifest in two ways: (a) the state machine s state information is changed, causing the state machine to unexpectedly transition to another state; (b) due to the asynchronous nature of SEU, the state machine's state registers become metastable, consequently causing any combinational logic associated with the metastable registers to malfunction temporarily. Effect (a) can be mitigated with methods such as triplemodular redundancy (TMR). However, effect (b) cannot be eliminated and can degrade the effectiveness of any mitigation method of effect (a). Although there is no way to completely eliminate the risk of SEU-induced errors, the risk can be made very small by use of a combination of very fast state-machine logic and error-detection logic. Therefore, one goal of two main elements of the present method is to design the fastest state-machine logic circuitry by basing it on the fastest generic state-machine design, which is that of a one-hot state machine. The other of the two main design elements is to design fast error-detection logic circuitry and to optimize it for implementation in a field-programmable gate array (FPGA) architecture: In the resulting design, the one-hot state machine is fitted with a multiple-input XNOR gate for detection of illegal states. The XNOR gate is implemented with lookup tables and with pipelines for high speed. In this method, the task of designing all the logic must be performed manually because no currently available logic synthesis software tool can produce optimal solutions of design problems of this type. However, some assistance is provided by a script, written for this purpose in the Python language (an object-oriented interpretive computer language) to automatically generate hardware description language (HDL) code from state-transition rules.

Le, Martin

Reviews and syntheses: Arctic fire regimes and emissions in the 21st century

In recent years, the pan-Arctic region has experienced increasingly extreme fire seasons. Fires in the northern high latitudes are driven by current and future climate change, lightning, fuel conditions, and human activity. In this context, conceptualizing and parameterizing current and future Arctic fire regimes will be important for fire and land management as well as understanding current and predicting future fire emissions. The objectives of this review were driven by policy questions identified by the Arctic Monitoring and Assessment Programme (AMAP) Working Group and posed to its Expert Group on Short-Lived Climate Forcers. This review synthesizes current understanding of the changing Arctic and boreal fire regimes, particularly as fire activity and its response to future climate change in the pan-Arctic have consequences for Arctic Council states aiming to mitigate and adapt to climate change in the north. The conclusions from our synthesis are the following. (1) Current and future Arctic fires, and the adjacent boreal region, are driven by natural (i.e. lightning) and human-caused ignition sources, including fires caused by timber and energy extraction, prescribed burning for landscape management, and tourism activities. Little is published in the scientific literature about cultural burning by Indigenous populations across the pan-Arctic, and questions remain on the source of ignitions above 70_ N in Arctic Russia. (2) Climate change is expected to make Arctic fires more likely by increasing the likelihood of extreme fire weather, increased lightning activity, and drier vegetative and ground fuel conditions. (3) To some extent, shifting agricultural land use and forest transitions from forest–steppe to steppe, tundra to taiga, and coniferous to deciduous in a warmer climate may increase and decrease open biomass burning, depending on land use in addition to climate-driven biome shifts. However, at the country and landscape scales, these relationships are not well established. (4) Current black carbon and PM2:5 emissions from wildfires above 50 and 65_ N are larger than emissions from heanthropogenic sectors of residential combustion, transportation, and flaring. Wildfire emissions have increased from 2010 to 2020, particularly above 60_ N, with 56% of black carbon emissions above 65_ N in 2020 attributed to open biomass burning – indicating how extreme the 2020 wildfire season was and how severe future Arctic wildfire seasons can potentially be. (5) What works in the boreal zones to prevent and fight wildfires may not work in the Arctic. Fire management will need to adapt to a changing climate, economic development, the Indigenous and local communities, and fragile northern ecosystems, including permafrost and peatlands. (6) Factors contributing to the uncertainty of predicting and quantifying future Arctic fire regimes include underestimation of Arctic fires by satellite systems, lack of agreement between Earth observations and official statistics, and still needed refinements of location, conditions, and previous fire return intervals on peat and permafrost landscapes. This review highlights that much research is needed in order to understand the local and regional impacts of the changing Arctic fire regime on emissions and the global climate, ecosystems, and pan-Arctic communities.

Arctic

Sequence-invariant state machines

A synthesis method and an MOS VLSI architecture are presented to realize sequential circuits that have the ability to implement any state machine having N states and m inputs, regardless of the actual sequence specified in the flow table. The design method utilizes binary tree structured (BTS) logic to implement regular and dense circuits. The desired state sequence can be hardwired with power supply connections or can be dynamically reallocated if stored in a register. This allows programmable VLSI controllers to be designed with a compact size and performance approaching that of dedicated logic. Results of ICV implementations are reported and an example sequence-invariant state machine is contrasted with implementations based on traditional methods.

Whitaker, Sterling R.

Radiation Mitigation and Power Optimization Design Tools for Reconfigurable Hardware in Orbit

The Reconfigurable Hardware in Orbit (RHinO)project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power inefficiencies. For radiation, a single event Upset (SEU) emulator, persistence analysis tool, and a half-latch removal tool for Xilinx/Virtex-II devices have been created. Research is underway on a persistence mitigation tool and multiple bit upsets (MBU) studies. For power, synthesis level dynamic power visualization and analysis tools have been completed. Power optimization tools are under development and preliminary test results are positive.

French, Matthew

Development of a Crosslink Channel Simulator for Simulation of Formation Flying Satellite Systems

Multi-vehicle missions are an integral part of NASA s and other space agencies current and future business. These multi-vehicle missions generally involve collectively utilizing the array of instrumentation dispersed throughout the system of space vehicles, and communicating via crosslinks to achieve mission goals such as formation flying, autonomous operation, and collective data gathering. NASA s Goddard Space Flight Center (GSFC) is developing the Formation Flying Test Bed (FFTB) to provide hardware-in- the-loop simulation of these crosslink-based systems. The goal of the FFTB is to reduce mission risk, assist in mission planning and analysis, and provide a technology development platform that allows algorithms to be developed for mission hctions such as precision formation flying, synchronization, and inter-vehicle data synthesis. The FFTB will provide a medium in which the various crosslink transponders being used in multi-vehicle missions can be plugged in for development and test. An integral part of the FFTB is the Crosslink Channel Simulator (CCS),which is placed into the communications channel between the crosslinks under test, and is used to simulate on-orbit effects to the communications channel due to relative vehicle motion or antenna misalignment. The CCS is based on the Starlight software programmable platform developed at General Dynamics Decision Systems which provides the CCS with the ability to be modified on the fly to adapt to new crosslink formats or mission parameters.

Hart, Roger

ACSYNT - A standards-based system for parametric, computer aided conceptual design of aircraft

A group of eight US aerospace companies together with several NASA and NAVY centers, led by NASA Ames Systems Analysis Branch, and Virginia Tech's CAD Laboratory agreed, through the assistance of Americal Technology Initiative, in 1990 to form the ACSYNT (Aircraft Synthesis) Institute. The Institute is supported by a Joint Sponsored Research Agreement to continue the research and development in computer aided conceptual design of aircraft initiated by NASA Ames Research Center and Virginia Tech's CAD Laboratory. The result of this collaboration, a feature-based, parametric computer aided aircraft conceptual design code called ACSYNT, is described. The code is based on analysis routines begun at NASA Ames in the early 1970's. ACSYNT's CAD system is based entirely on the ISO standard Programmer's Hierarchical Interactive Graphics System and is graphics-device independent. The code includes a highly interactive graphical user interface, automatically generated Hermite and B-Spline surface models, and shaded image displays. Numerous features to enhance aircraft conceptual design are described.

Jayaram, S.

EHW Approach to Temperature Compensation of Electronics

Efforts are under way to apply the concept of evolvable hardware (EHW) to compensate for variations, with temperature, in the operational characteristics of electronic circuits. To maintain the required functionality of a given circuit at a temperature above or below the nominal operating temperature for which the circuit was originally designed, a new circuit would be evolved; moreover, to obtain the required functionality over a very wide temperature range, there would be evolved a number of circuits, each of which would satisfy the performance requirements over a small part of the total temperature range. The basic concepts and some specific implementations of EHW were described in a number of previous NASA Tech Briefs articles, namely, "Reconfigurable Arrays of Transistors for Evolvable Hardware" (NPO-20078), Vol. 25, No. 2 (February 2001), page 36; Evolutionary Automated Synthesis of Electronic Circuits (NPO- 20535), Vol. 26, No. 7 (July 2002), page 37; "Designing Reconfigurable Antennas Through Hardware Evolution" (NPO-20666), Vol. 26, No. 7 (July 2002), page 38; "Morphing in Evolutionary Synthesis of Electronic Circuits" (NPO-20837), Vol. 26, No. 8 (August 2002), page 31; "Mixtrinsic Evolutionary Synthesis of Electronic Circuits" (NPO-20773) Vol. 26, No. 8 (August 2002), page 32; and "Synthesis of Fuzzy-Logic Circuits in Evolvable Hardware" (NPO-21095) Vol. 26, No. 11 (November 2002), page 38. To recapitulate from the cited prior articles: EHW is characterized as evolutionary in a quasi-genetic sense. The essence of EHW is to construct and test a sequence of populations of circuits that function as incrementally better solutions of a given design problem through the selective, repetitive connection and/or disconnection of capacitors, transistors, amplifiers, inverters, and/or other circuit building blocks. The connection and disconnection can be effected by use of field-programmable transistor arrays (FPTAs). The evolution is guided by a search-andoptimization algorithm (in particular, a genetic algorithm) that operates in the space of possible circuits to find a circuit that exhibits an acceptably close approximation of the desired functionality. The evolved circuits can be tested by mathematical modeling (that is, computational simulation) only, tested in real hardware, or tested in combinations of computational simulation and real hardware.

Stoica, Adrian

Sequence invariant state machines

A synthesis method and new VLSI architecture are introduced to realize sequential circuits that have the ability to implement any state machine having N states and m inputs, regardless of the actual sequence specified in the flow table. A design method is proposed that utilizes BTS logic to implement regular and dense circuits. A given state sequence can be programmed with power supply connections or dynamically reallocated if stored in a register. Arbitrary flow table sequences can be modified or programmed to dynamically alter the function of the machine. This allows VLSI controllers to be designed with the programmability of a general purpose processor but with the compact size and performance of dedicated logic.

Whitaker, S.

AutoBayes/CC: Combining Program Synthesis with Automatic Code Certification: System Description

Code certification is a lightweight approach to formally demonstrate software quality. It concentrates on aspects of software quality that can be defined and formalized via properties, e.g., operator safety or memory safety. Its basic idea is to require code producers to provide formal proofs that their code satisfies these quality properties. The proofs serve as certificates which can be checked independently, by the code consumer or by certification authorities, e.g., the FAA. It is the idea underlying such approaches as proof-carrying code [6]. Code certification can be viewed as a more practical version of traditional Hoare-style program verification. The properties to be verified are fairly simple and regular so that it is often possible to use an automated theorem prover to automatically discharge all emerging proof obligations. Usually, however, the programmer must still splice auxiliary annotations (e.g., loop invariants) into the program to facilitate the proofs. For complex properties or larger programs this quickly becomes the limiting factor for the applicability of current certification approaches.

Whalen, Michael

A Fixed Point VHDL Component Library for a High Efficiency Reconfigurable Radio Design Methodology

Advances in Field Programmable Gate Array (FPGA) technologies enable the implementation of reconfigurable radio systems for both ground and space applications. The development of such systems challenges the current design paradigms and requires more robust design techniques to meet the increased system complexity. Among these techniques is the development of component libraries to reduce design cycle time and to improve design verification, consequently increasing the overall efficiency of the project development process while increasing design success rates and reducing engineering costs. This paper describes the reconfigurable radio component library developed at the Software Defined Radio Applications Research Center (SARC) at Goddard Space Flight Center (GSFC) Microwave and Communications Branch (Code 567). The library is a set of fixed-point VHDL components that link the Digital Signal Processing (DSP) simulation environment with the FPGA design tools. This provides a direct synthesis path based on the latest developments of the VHDL tools as proposed by the BEE VBDL 2004 which allows for the simulation and synthesis of fixed-point math operations while maintaining bit and cycle accuracy. The VHDL Fixed Point Reconfigurable Radio Component library does not require the use of the FPGA vendor specific automatic component generators and provide a generic path from high level DSP simulations implemented in Mathworks Simulink to any FPGA device. The access to the component synthesizable, source code provides full design verification capability:

Hoy, Scott D.