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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

Microprocessor controlled proof-mass actuator

The objective of the microprocessor controlled proof-mass actuator is to develop the capability to mount a small programmable device on laboratory models. This capability will allow research in the active control of flexible structures. The approach in developing the actuator will be to mount all components as a single unit. All sensors, electronic and control devices will be mounted with the actuator. The goal for the force output capability of the actuator will be one pound force. The programmable force actuator developed has approximately a one pound force capability over the usable frequency range, which is above 2 Hz.

Horner, Garnett C.↗
NASA NTRS2004

Evolutionary recovery from radiation induced faults and reconfigurable devices

Radiation hardening technologies for electronics are the conventional approach for survivability in high radiation environments. This paper presents a novel approach based on evolvable hardware. The key idea is to reconfigure a programmable device, in-situ, to compensate, or bypass its degraded or damaged compoenents.

Daud, Taher↗
NASA NTRS1981

An integrated control panel utilizing a programmable varistor-multiplexed dichroic liquid crystal display

Due to the conflicting demands of modern aircraft for increased systems/sensors and the decrease in cockpit panel size, weight, volume, and power, conventional discrete/dedicated methods of display and control are fast becoming obsolete. A means is sought to integrate the control and display into multifunctional programmable devices, thus giving the ability to increase system functions and yet conserve panel space. A potential solution to the control portion of the problem has come to be known as the Integrated Control Panel (ICP) approach. Flat panel display technology and controls using programmable flat panel displays with transparent capacitive touch control overlays offer the largest potential advantages. The flat panel display made of varistor-multiplexed dichroic liquid crystal (LCD) developed by GE in recent years appears to offer the ideal monochrome solution.

Whitton, I. J.↗
NASA NTRS1992

Field programmable gate arrays: Evaluation report for space-flight application

Field Programmable Gate Arrays commonly called FPGA's are the newer generation of field programmable devices and offer more flexibility in the logic modules they incorporate and in how they are interconnected. The flexibility, the number of logic building blocks available, and the high gate densities achievable are why users find FPGA's attractive. These attributes are important in reducing product development costs and shortening the development cycle. The aerospace community is interested in incorporating this new generation of field programmable technology in space applications. To this end, a consortium was formed to evaluate the quality, reliability, and radiation performance of FPGA's. This report presents the test results on FPGA parts provided by ACTEL Corporation.

Sandoe, Mike↗
NASA NTRS2004

Design Space Issues for Intrinsic Evolvable Hardware

This paper discusses the problem of increased programming time for intrinsic evolvable hardware (EM) as the complexity of the circuit grows. As the circuit becomes more complex, then more components will be required and a longer programming string, L, is required. We develop equations for the size of the population, n, and the number of generations required for the population to converge, based on L. Our analytical results show that even though the design search space grows as 2L (assuming a binary programming string), the number of circuit evaluations, n*ngen, only grows as O(Lg3), or slightly less than O(L). This makes evolvable techniques a good tool for exploring large design spaces. The major hurdle for intrinsic EHW is evaluation time for each possible circuit. The evaluation time involves downloading the bit string to the device, updating the device configuration, measuring the output and then transferring the output data to the control processor. Each of these steps must be done for each member of the population. The processing time of the computer becomes negligible since the selection/crossover/mutation steps are only done once per generation. Evaluation time presently limits intrinsic evolvable hardware techniques to designing only small or medium-sized circuits. To evolve large or complicated circuits, several researchers have proposed using hierarchical design or reuse techniques where submodules are combined together to form complex circuits. However, these practical approaches limit the search space of available designs and preclude utilizing parasitic coupling or other effects within the programmable device. The practical approaches also raise the issue of why intrinsic EHW techniques do not easily apply to large design spaces, since the analytical results show only an O(L) complexity growth.

Hereford, James↗
DOE OSTI2023

Near-field imaging and spectroscopy of terahertz resonators and metasurfaces [Invited]

Terahertz (THz) metasurfaces have become a key platform for engineering light-matter interaction at THz frequencies. They have evolved from simple metallic resonator arrays into tunable and programmable devices, displaying ultrafast modulation rates and incorporating emerging quantum materials. The electrodynamics which govern metasurface operation can only be directly revealed at the scale of subwavelength individual metasurface elements, through sampling their evanescent fields. It requires near-field spectroscopy and imaging techniques to overcome the diffraction limit and provide spatial resolution down to the nanoscale. Through a series of case studies, this review provides an in-depth overview of recently developed THz near-field microscopy capabilities for research on metamaterials.

Hale, Lucy L. (ORCID:0000000176544272)↗
NASA NTRS1994

Software-Implemented Fault Tolerance in Communications Systems

Software-implemented fault tolerance (SIFT) is used in many computer-based command, control, and communications (C(3)) systems to provide the nearly continuous availability that they require. In the communications subsystem of Space Station Alpha, SIFT algorithms are used to detect and recover from failures in the data and command link between the Station and its ground support. The paper presents a review of these algorithms and discusses how such techniques can be applied to similar systems found in applications such as manufacturing control, military communications, and programmable devices such as pacemakers. With support from the Tracking and Communication Division of NASA's Johnson Space Center, researchers at the University of Wyoming are developing a testbed for evaluating the effectiveness of these algorithms prior to their deployment. This testbed will be capable of simulating a variety of C(3) system failures and recording the response of the Space Station SIFT algorithms to these failures. The design of this testbed and the applicability of the approach in other environments is described.

Gantenbein, Rex E.↗
NASA NTRS2002

2001 MAPLD International Conference Proceedings

This CD contains the proceedings from the '2001 MAPLD International Conference', held on 11-13 September 2001 at Johns Hopkins University. Sessions included the following: (1) Applications: Military and Aerospace; (2) Design 1: Processors, Logic, and Programmable Devices; (3) Reliability: Devices and The Effects of the Radiation Environment; (4) Design 2: Systems; and (5) Design 3: Fault Tolerance.

Source record↗
NASA NTRS2004

Scalability, Timing, and System Design Issues for Intrinsic Evolvable Hardware

In this paper we address several issues pertinent to intrinsic evolvable hardware (EHW). The first issue is scalability; namely, how the design space scales as the programming string for the programmable device gets longer. We develop a model for population size and the number of generations as a function of the programming string length, L, and show that the number of circuit evaluations is an O(L2) process. We compare our model to several successful intrinsic EHW experiments and discuss the many implications of our model. The second issue that we address is the timing of intrinsic EHW experiments. We show that the processing time is a small part of the overall time to derive or evolve a circuit and that major improvements in processor speed alone will have only a minimal impact on improving the scalability of intrinsic EHW. The third issue we consider is the system-level design of intrinsic EHW experiments. We review what other researchers have done to break the scalability barrier and contend that the type of reconfigurable platform and the evolutionary algorithm are tied together and impose limits on each other.

Hereford, James↗
NASA NTRS2002

Evolvable, reconfigurable hardware for future space systems

This paper overviews Evolvable Hardware (EHW) technology, examining its potential for enhancing survivability and flexibility of future space systems. EHW refers to selfconfiguration of electronic hardware by evolutionary/genetic search mechanisms. Evolvable Hardware can maintain existing functionality in the presence of faults and degradations due to aging, temperature and radiation. It can also configure itself for new functionality when required for mission changes or encountered opportunities. The paper illustrates hardware evolution in silicon using a JPL-designed programmable device reconfigurable at transistor level as the platform and a genetic algorithm running on a DSP as the reconfiguration mechanism. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The experiments demonstrate functional recovery from faults as well as from degradation at extreme temperatures indicating the possibility of expanding the operational range of extreme electronics through evolved circuit solutions.

Evolvable Hardware EHW↗
NASA NTRS1998

Ladder-structured photonic variable delay device

An ladder-structured variable delay device for providing variable true time delay to multiple optical beams simultaneously. The device comprises multiple basic units stacked on top of each other resembling a ladder. Each basic unit comprises a polarization sensitive corner reflector formed by two polarization beamsplitters and a polarization rotator array placed parallel to the hypotenuse of the corner reflector. Controlling an array element of the polarization rotator array causes an optical beam passing through the array element to either go up to a basic unit above it or reflect back towards output. The beams going higher on the ladder experience longer optical path delay. Finally, the ladder-structured variable device can be cascaded with another multi-channel delay device to form a new device which combines the advantages of the two individual devices. This programmable optic device has the properties of high packing density, low loss, easy fabrication, and virtually infinite bandwidth. In addition, the delay is reversible so that the same delay device can be used for both antenna transmitting and receiving.

Yao, X. Steve↗
NASA NTRS2005

Photonic variable delay devices based on optical birefringence

Optical variable delay devices for providing variable true time delay to multiple optical beams simultaneously. A ladder-structured variable delay device comprises multiple basic building blocks stacked on top of each other resembling a ladder. Each basic building block has two polarization beamsplitters and a polarization rotator array arranged to form a trihedron; Controlling an array element of the polarization rotator array causes a beam passing through the array element either going up to a basic building block above it or reflect back towards a block below it. The beams going higher on the ladder experience longer optical path delay. An index-switched optical variable delay device comprises of many birefringent crystal segments connected with one another, with a polarization rotator array sandwiched between any two adjacent crystal segments. An array element in the polarization rotator array controls the polarization state of a beam passing through the element, causing the beam experience different refractive indices or path delays in the following crystal segment. By independently control each element in each polarization rotator array, variable optical path delays of each beam can be achieved. Finally, an index-switched variable delay device and a ladder-structured variable device are cascaded to form a new device which combines the advantages of the two individual devices. This programmable optic device has the properties of high packing density, low loss, easy fabrication, and virtually infinite bandwidth. The device is inherently two dimensional and has a packing density exceeding 25 lines/cm2. The delay resolution of the device is on the order of a femtosecond (one micron in space) and the total delay exceeds 10 nanosecond. In addition, the delay is reversible so that the same delay device can be used for both antenna transmitting and receiving.

Yao, X. Steve↗
NASA NTRS2012

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Suarez, George↗
NASA NTRS2023

Toward Accurate Thermal Modeling of Phase Change Material Based Photonic Devices

Reconfigurable or programmable photonic devices are rapidly growing and have become an integral part of many optical systems. The ability to selectively modulate electromagnetic waves through electrical stimuli is crucial in the advancement of a variety of applications from data communication and computing devices to environmental science and space explorations. Chalcogenide-based phase change materials (PCMs) are one of the most promising material candidates for reconfigurable photonics due to their large optical contrast between their different solid-state structural phases. Although significant efforts have been devoted to accurate simulation of PCM-based devices, in this paper, we highlight three important aspects which have often evaded prior models yet having significant impacts on the thermal and phase transition behavior of these devices: the enthalpy of fusion, the heat capacity change upon glass transition, as well as the thermal conductivity of liquid-phase PCMs. We further investigated the important topic of switching energy scaling in PCM devices, which also helps explain why the three above-mentioned effects have long been overlooked in electronic PCM memories but only become important in photonics. Our findings offer insight to facilitate accurate modeling of PCM-based photonic devices and can inform the development of more efficient reconfigurable optics.

Phase change materials↗
NASA NTRS1976

Hardware additions to microprocessor architecture aid software development

An address trap (breakpoint) mechanism and last-in-first-out (LIFO) address stack are suggested as two additions to the basic microprocessor architecture whose functions are solely to aid the programmer. These devices provide the programmer with the ability to specify address breakpoints and to trace program execution back through N instructions, where N is the depth of the stack. Both devices, plus interface logic and buffering, have been designed for an INTEL 8080-based system using approximately 25 integrated-circuit packages.

Sievers, M. W.↗
DOE OSTI2021

Localized strain profile in surface electrode array for programmable composite multiferroic devices

In this work, we investigate localized in-plane strains on the microscale, induced by arrays of biased surface electrodes patterned on piezoelectrics. Particular focus is given to the influence that adjacent electrode pairs have on one another to study the impact of densely packed electrode arrays. We present a series of X-ray microdiffraction studies to reveal the spatially resolved micrometer-scale strain distribution. The strain maps with micrometer-scale resolution highlight how the local strain profile in square regions up to 250 x 250 lm 2 in size is affected by the surface electrodes that are patterned on ferroelectric single-crystal [Pb(Mg 1/3 Nb 2/3 )O 3 ] x -[PbTiO 3 ] 1-x . The experimental measurements and simulation results show the influence of electrode pair distance, positioning of the electrode pair, including the angle of placement, and neighboring electrode pair arrangements on the strength and direction of the regional strain. Our findings are relevant to the development of microarchitected strain-mediated multiferroic devices. The electrode arrays could provide array-addressable localized strain control for applications including straintronic memory, probabilistic computing platforms, microwave devices, and magnetic-activated cell sorting platforms.

42 ENGINEERING↗
NASA NTRS1991

Sign-And-Magnitude Up/Down Counter

Magnitude-and-sign counter includes conventional up/down counter for magnitude part and special additional circuitry for sign part. Negative numbers indicated more directly. Counter implemented by programming erasable programmable logic device (EPLD) or programmable logic array (PLA). Used in place of conventional up/down counter to provide sign and magnitude values directly to other circuits.

Cole, Steven W.↗