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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Ab Initio Quantum Information Processor Design with Single-Molecule Magnets: A Multiscale Modeling Approach (Final Report)

This final report summarizes the team's efforts to develop a multiscale modeling approach that ranges from different levels of ab-initio quantum chemistry simulations to effective models and time-dependent external control, and to use this approach to systematically design quantum information processors with TbPc 2 single-molecule magnets. The impact of the work is two-fold: (i) New quantum chemistry simulation techniques capable of treating complex, multiscale problems such as the TbPc 2 molecule were developed, and (ii) the prospects for building quantum processors based on single-molecule magnets coupled by superconducting transmission line resonators were analyzed. The outcomes of this project revealed that current technology is at the cusp of being able to realize the main components of such a processor, and they highlighted the need to achieve stronger molecule-resonator interactions to enhance the viability of this approach. The multiscale modeling techniques developed during this project are general and transferable to other molecules and will thus have a broad impact on the field of quantum chemistry. Methods for controlling and simulating many coupled qubits developed here will also impact other quantum information technologies.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2023

Sample-efficient verification of continuously-parameterized quantum gates for small quantum processors

Most near-term quantum information processing devices will not be capable of implementing quantum error correction and the associated logical quantum gate set. Instead, quantum circuits will be implemented directly using the physical native gate set of the device. These native gates often have a parameterization (e.g., rotation angles) which provide the ability to perform a continuous range of operations. Verification of the correct operation of these gates across the allowable range of parameters is important for gaining confidence in the reliability of these devices. In this work, we demonstrate a procedure for sample-efficient verification of continuously-parameterized quantum gates for small quantum processors of up to approximately 10 qubits. This procedure involves generating random sequences of randomly-parameterized layers of gates chosen from the native gate set of the device, and then stochastically compiling an approximate inverse to this sequence such that executing the full sequence on the device should leave the system near its initial state. We show that fidelity estimates made via this technique have a lower variance than fidelity estimates made via cross-entropy benchmarking. This provides an experimentally-relevant advantage in sample efficiency when estimating the fidelity loss to some desired precision. We describe the experimental realization of this technique using continuously-parameterized quantum gate sets on a trapped-ion quantum processor from Sandia QSCOUT and a superconducting quantum processor from IBM Q, and we demonstrate the sample efficiency advantage of this technique both numerically and experimentally.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2020

Understanding the Impact of Memory Access Patterns in Intel Processors

Because of increasing complexity in the memory hierarchy, predicting the performance of a given application in a given processor is becoming more difficult. The problem is worsened by the fact that the hardware needed to deal with more complex memory traffic also affects energy consumption. Moreover, in a heterogeneous system with shared main memory, the memory traffic between the last level cache (LLC) and the memory creates contention between other processors and accelerator devices. For these reasons, it is important to investigate and understand the impact of different memory access patterns on the memory system. This study investigates the interplay between Intel processors' memory hierarchy and different memory access patterns in applications. The authors explore sequential streaming and strided memory access patterns with the objective of predicting LLC-dynamic random access memory (DRAM) traffic for a given application in given Intel architectures. Moreover, the impact of prefetching is also investigated in this study. Experiments with different Intel micro-architectures uncover mechanisms to predict LLC-DRAM traffic that can yield up to 99% accuracy for sequential streaming access patterns and up to 95% accuracy for strided access patterns.

Alaul haque monil, Mohammad↗
DOE OSTI2021

Techniques in performance and efficiency improvements of processors in a cooling system

Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for Thermal Design Power (TDP) rebalancing among thermally-coupled processors and non-thermally-coupled processors, providing computing efficiency or homogeneity with respect to, including but not limited to, thermal requirements, power consumption, and processor operations. The TDP rebalancing may include implementing management circuitry and configuration control circuitry. Other embodiments may be described and claimed.

Keceli, Fuat↗
DOE OSTI2022

Controlling prediction functional blocks used by a branch predictor in a processor

An electronic device includes a processor, a branch predictor in the processor, and a predictor controller in the processor. The branch predictor includes multiple prediction functional blocks, each prediction functional block configured for generating predictions for control transfer instructions (CTIs) in program code based on respective prediction information, the branch predictor configured to select, from among predictions generated by the prediction functional blocks for each CTI, a selected prediction to be used for that CTI. The predictor controller keeps a record of prediction functional blocks from which the branch predictor previously selected predictions for CTIs. The predictor controller uses information from the record for controlling which prediction functional blocks are used by the branch predictor for generating predictions for CTIs.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2026

Architectural scaling tradeoffs in modular 3D bosonic quantum processors

We propose a modular three-dimensional bosonic quantum processor built from repeatable coupled-cavity modules linked by configurable interconnect networks. Using hardware-motivated graph-theoretic measures, we compare nearest-neighbor, hub-based, and hybrid architectures in terms of interconnect count, communication distance, resource concentration, and implementation complexity. Rather than identifying a universally optimal topology, our analysis shows how these architectures redistribute the costs of scaling, including wiring and port requirements, nonlocal communication distance, exposure to shared resources, routing bottlenecks, and scheduling overhead. Case studies of a \(3\times3\) processor and a larger hierarchical architecture further distinguish finite-size performance from asymptotic scaling. The resulting framework provides a systematic basis for evaluating modular three-dimensional bosonic processors and for identifying the device-level parameters required for quantitative hardware design.

Zhu, Shaojiang [Fermilab] (ORCID:0000000293180092)↗
DOE OSTI2024

Modeling information flow in a computer processor with a multi-stage queuing model

In this paper, we introduce a nonlinear stochastic model to describe the propagation of information inside a computer processor. In this model, a computational task is divided into stages, and information can flow from one stage to another. The model is formulated as a spatially-extended, continuous-time Markov chain where space represents different stages. This model is equivalent to a spatially-extended version of the M/M/s queue. The main modeling feature is the throttling function which describes the processor slowdown when the amount of information falls below a certain threshold. We derive the stationary distribution for this stochastic model and develop a closure for a deterministic ODE system that approximates the evolution of the mean and variance of the stochastic model. In conclusion, we demonstrate the validity of the closure with numerical simulations.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Broadband unidirectional visible imaging using wafer-scale nano-fabrication of multi-layer diffractive optical processors

We present a broadband and polarization-insensitive unidirectional imager that operates at the visible part of the spectrum, where image formation occurs in one direction, while in the opposite direction, it is blocked. This approach is enabled by deep learning-driven diffractive optical design with wafer-scale nano-fabrication using high-purity fused silica to ensure optical transparency and thermal stability. Our design achieves unidirectional imaging across three visible wavelengths (covering red, green, and blue parts of the spectrum), and we experimentally validated this broadband unidirectional imager by creating high-fidelity images in the forward direction and generating weak, distorted output patterns in the backward direction, in alignment with our numerical simulations. This work demonstrates wafer-scale production of diffractive optical processors, featuring 16 levels of nanoscale phase features distributed across two axially aligned diffractive layers for visible unidirectional imaging. This approach facilitates mass-scale production of ~0.5 billion nanoscale phase features per wafer, supporting high-throughput manufacturing of hundreds to thousands of multi-layer diffractive processors suitable for large apertures and parallel processing of multiple tasks. Beyond broadband unidirectional imaging in the visible spectrum, this study establishes a pathway for artificial-intelligence-enabled diffractive optics with versatile applications, signaling a new era in optical device functionality with industrial-level, massively scalable fabrication.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Universal linear intensity transformations using spatially incoherent diffractive processors

Abstract Under spatially coherent light, a diffractive optical network composed of structured surfaces can be designed to perform any arbitrary complex-valued linear transformation between its input and output fields-of-view (FOVs) if the total number ( N ) of optimizable phase-only diffractive features is ≥~2 N i N o , where N i and N o refer to the number of useful pixels at the input and the output FOVs, respectively. Here we report the design of a spatially incoherent diffractive optical processor that can approximate any arbitrary linear transformation in time-averaged intensity between its input and output FOVs. Under spatially incoherent monochromatic light, the spatially varying intensity point spread function ( H ) of a diffractive network, corresponding to a given, arbitrarily-selected linear intensity transformation, can be written as H ( m , n ; m ′, n ′) = | h ( m , n ; m ′, n ′)| 2 , where h is the spatially coherent point spread function of the same diffractive network, and ( m , n ) and ( m ′, n ′) define the coordinates of the output and input FOVs, respectively. Using numerical simulations and deep learning, supervised through examples of input-output profiles, we demonstrate that a spatially incoherent diffractive network can be trained to all-optically perform any arbitrary linear intensity transformation between its input and output if N ≥ ~2 N i N o . We also report the design of spatially incoherent diffractive networks for linear processing of intensity information at multiple illumination wavelengths, operating simultaneously. Finally, we numerically demonstrate a diffractive network design that performs all-optical classification of handwritten digits under spatially incoherent illumination, achieving a test accuracy of >95%. Spatially incoherent diffractive networks will be broadly useful for designing all-optical visual processors that can work under natural light.

36 MATERIALS SCIENCE↗
DOE OSTI2024

All-optical image denoising using a diffractive visual processor

Abstract Image denoising, one of the essential inverse problems, targets to remove noise/artifacts from input images. In general, digital image denoising algorithms, executed on computers, present latency due to several iterations implemented in, e.g., graphics processing units (GPUs). While deep learning-enabled methods can operate non-iteratively, they also introduce latency and impose a significant computational burden, leading to increased power consumption. Here, we introduce an analog diffractive image denoiser to all-optically and non-iteratively clean various forms of noise and artifacts from input images – implemented at the speed of light propagation within a thin diffractive visual processor that axially spans <250 × λ, where λ is the wavelength of light. This all-optical image denoiser comprises passive transmissive layers optimized using deep learning to physically scatter the optical modes that represent various noise features, causing them to miss the output image Field-of-View (FoV) while retaining the object features of interest. Our results show that these diffractive denoisers can efficiently remove salt and pepper noise and image rendering-related spatial artifacts from input phase or intensity images while achieving an output power efficiency of ~30–40%. We experimentally demonstrated the effectiveness of this analog denoiser architecture using a 3D-printed diffractive visual processor operating at the terahertz spectrum. Owing to their speed, power-efficiency, and minimal computational overhead, all-optical diffractive denoisers can be transformative for various image display and projection systems, including, e.g., holographic displays.

36 MATERIALS SCIENCE↗
DOE OSTI2026

Realization of fermionic Laughlin state on a quantum processor

Strongly correlated topological phases of matter are central to modern condensed matter physics and quantum information technology but often challenging to probe and control in material systems. The experimental difficulty of accessing these phases has motivated the use of engineered quantum platforms for simulation and manipulation of exotic topological states. Among these, the Laughlin state stands as a cornerstone for topological matter, embodying fractionalization, anyonic excitations, and incompressibility. Although its bosonic analogs have been realized on programmable quantum simulators, a genuine fermionic Laughlin state has yet to be demonstrated on a quantum processor. Here, we realize the ν = 1/3 fermionic Laughlin state on IonQ’s trapped-ion quantum computer using an efficient and scalable Hamiltonian variational ansatz with 369 two-qubit gates on a 16-qubit circuit. Employing symmetry-verification error mitigation, we extract key observables that characterize the Laughlin state, including correlation hole, bulk-edge correspondence, and topological entanglement entropy, with strong agreement to exact diagonalization benchmarks. This work demonstrates an end-to-end workflow to simulate material-intrinsic topological orders and provides a starting point to explore its dynamics and excitations on digital quantum processors.

Shen, Lingnan [Univ. of Washington, Seattle, WA (U↗
DOE OSTI2024

Extending the computational reach of a superconducting qutrit processor

Quantum computing with qudits is an emerging approach that exploits a larger, more connected computational space, providing advantages for many applications, including quantum simulation and quantum error correction. Nonetheless, qudits are typically afflicted by more complex errors and suffer greater noise sensitivity which renders their scaling difficult. In this work, we introduce techniques to tailor arbitrary qudit Markovian noise to stochastic Weyl–Heisenberg channels and mitigate noise that commutes with our Clifford and universal two-qudit gate in generic qudit circuits. We experimentally demonstrate these methods on a superconducting transmon qutrit processor, and benchmark their effectiveness for multipartite qutrit entanglement and random circuit sampling, obtaining up to 3× improvement in our results. To the best of our knowledge, this constitutes the first-ever error mitigation experiment performed on qutrits. Our work shows that despite the intrinsic complexity of manipulating higher-dimensional quantum systems, noise tailoring and error mitigation can significantly extend the computational reach of today’s qudit processors.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2022

A quantum processor based on coherent transport of entangled atom arrays

The ability to engineer parallel, programmable operations between desired qubits within a quantum processor is key for building scalable quantum information systems. In most state-of-the-art approaches, qubits interact locally, constrained by the connectivity associated with their fixed spatial layout. Here we demonstrate a quantum processor with dynamic, non-local connectivity, in which entangled qubits are coherently transported in a highly parallel manner across two spatial dimensions, between layers of single- and two-qubit operations. Our approach makes use of neutral atom arrays trapped and transported by optical tweezers; hyperfine states are used for robust quantum information storage, and excitation into Rydberg states is used for entanglement generation. We use this architecture to realize programmable generation of entangled graph states, such as cluster states and a seven-qubit Steane code state. Furthermore, we shuttle entangled ancilla arrays to realize a surface code state with thirteen data and six ancillary qubits and a toric code state on a torus with sixteen data and eight ancillary qubits. Finally, we use this architecture to realize a hybrid analogue–digital evolution and use it for measuring entanglement entropy in quantum simulations, experimentally observing non-monotonic entanglement dynamics associated with quantum many-body scars. Realizing a long-standing goal, these results provide a route towards scalable quantum processing and enable applications ranging from simulation to metrology.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Measurement-induced entanglement and teleportation on a noisy quantum processor

Measurement has a special role in quantum theory: by collapsing the wavefunction, it can enable phenomena such as teleportation and thereby alter the ‘arrow of time’ that constrains unitary evolution. When integrated in many-body dynamics, measurements can lead to emergent patterns of quantum information in space–time that go beyond the established paradigms for characterizing phases, either in or out of equilibrium. For present-day noisy intermediate-scale quantum (NISQ) processors, the experimental realization of such physics can be problematic because of hardware limitations and the stochastic nature of quantum measurement. Here we address these experimental challenges and study measurement-induced quantum information phases on up to 70 superconducting qubits. By leveraging the interchangeability of space and time, we use a duality mapping to avoid mid-circuit measurement and access different manifestations of the underlying phases, from entanglement scaling to measurement-induced teleportation. We obtain finite-sized signatures of a phase transition with a decoding protocol that correlates the experimental measurement with classical simulation data. The phases display remarkably different sensitivity to noise, and we use this disparity to turn an inherent hardware limitation into a useful diagnostic. Our work demonstrates an approach to realizing measurement-induced physics at scales that are at the limits of current NISQ processors.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2023

Conceptual study of a two-layer silicon pixel detector to tag the passage of muons from cosmic sources through quantum processors

Abstract Recent studies in quantum computing have shown that quantum error correction with large numbers of physical qubits are limited by ionizing radiation from high-energy particles. Depending on the physical setup of the quantum processor, the contribution of muons from cosmic sources can constitute a significant fraction of these interactions. As most of these muons are difficult to stop, we perform a conceptual study of a two-layer silicon pixel detector to tag their hits on a solid-state quantum processor instead. With a typical dilution refrigerator geometry model, we find that efficiencies greater than 50% are most likely to be achieved if at least one of the layers is operated at the deep-cryogenic (<1 K) flanges of the refrigerator. Following this finding, we further propose a novel research program that could allow the development of silicon pixel detectors that are fast enough to provide input to quantum error correction algorithms, can operate at deep-cryogenic temperatures, and have very low power consumption.

Instruments & Instrumentation↗
DOE OSTI2020

Probing quantum processor performance with pyGSTi

PyGSTi is a Python software package for assessing and characterizing the performance of quantum computing processors. It can be used as a standalone application, or as a library, to perform a wide variety of quantum characterization, verification, and validation (QCVV) protocols on as-built quantum processors. In this work, we outline pyGSTi's structure, and what it can do, using multiple examples. We cover its main characterization protocols with end-to-end implementations. These include gate set tomography, randomized benchmarking on one or many qubits, and several specialized techniques. We also discuss and demonstrate how power users can customize pyGSTi and leverage its components to create specialized QCVV protocols and solve user-specific problems.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

Simulating noise on a quantum processor: interactions between a qubit and resonant two-level system bath

Material defects fundamentally limit the coherence times of superconducting qubits, and manufacturing completely defect-free devices is not yet possible. Therefore, understanding the interactions between defects and a qubit in a real quantum processor design is essential. We build a model that incorporates the standard tunneling model, the electric field distributions in the qubit, and open quantum system dynamics, and draws from the current understanding of two-level system (TLS) theory. Specifically, we start with one million TLSs distributed on the surface of a qubit and pick the 200 systems that are most strongly coupled to the qubit. We then perform a full Lindbladian simulation that explicitly includes the coherent coupling between the qubit and the TLS bath to model the time dependent density matrix of resonant TLS defects and the qubit. We find that the 200 most strongly coupled TLSs can accurately describe the qubit energy relaxation time. This work confirms that resonant TLSs located in areas where the electric field is strong can significantly affect the qubit relaxation time, even if they are located far from the Josephson junction (JJ). Similarly, a strongly-coupled resonant TLS located in the JJ does not guarantee a reduced qubit relaxation time if a more strongly coupled TLS is far from the JJ. In addition to the coupling strengths between TLSs and the qubit, the model predicts that the geometry of the device and the TLS relaxation time play a significant role in qubit dynamics. Our work can provide guidance for future quantum processor designs with improved qubit coherence times.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2026

A cryogenic muon tagging system based on kinetic inductance detectors for superconducting quantum processors

Ionizing radiation has emerged as a potential limiting factor for superconducting quantum processors, inducing quasiparticle bursts and correlated errors that challenge fault-tolerant operation. Atmospheric muons are particularly problematic due to their high energy and penetration power, making passive shielding ineffective. Therefore, monitoring the real-time muon flux is crucial to guide the development of alternative error-correction or mitigation strategies. We present the design, simulation, and first operation of a cryogenic muon-tagging system based on kinetic inductance detectors (KIDs), developed as a stand-alone cryogenic particle-tagging module for superconducting quantum processors. The system consists of two KIDs arranged in a vertical stack and operated at ∼20 mK. Monte Carlo simulations based on Geant4 guided the prototype design and provided reference expectations for muon-tagging efficiency and accidental coincidences due to ambient γ-rays. We observed a muon-induced coincidence rate among the top and bottom detectors of (192 ± 9) $\times\,10^{-3}$ events s$^{−1}$, in excellent agreement with the Monte Carlo prediction. The prototype achieves a muon-tagging efficiency of about 90% with negligible dead time. These results demonstrate the feasibility of operating a muon-tagging system at millikelvin temperatures and represent a key step toward the integration of cryogenic veto systems with multi-qubit chips to mitigate muon-induced errors.

Mariani, Ambra [INFN, Rome] (ORCID:000000028184857↗