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Neuromorphic computing architecture with dynamically accessible contexts

Various technologies pertaining to allocating computing resources of a neuromorphic computing system are described herein. Subgraphs of a neural algorithm graph to be executed by the neuromorphic computing system are identified. The subgraphs are each executed by a group of neuron circuits serially. Output data generated by execution of the subgraphs are provided to the same or a second group of neuron circuits at a same time or with associated timing data indicative of a time at which the output data was generated. The same or second group of neuron circuits performs one or more processing operations based upon the output data.

Aimone, James Bradley↗

The neurobench framework for benchmarking neuromorphic computing algorithms and systems

Neuromorphic computing shows promise for advancing computing efficiency and capabilities of AI applications using brain-inspired principles. However, the neuromorphic research field currently lacks standardized benchmarks, making it difficult to accurately measure technological advancements, compare performance with conventional methods, and identify promising future research directions. This article presents NeuroBench, a benchmark framework for neuromorphic algorithms and systems, which is collaboratively designed from an open community of researchers across industry and academia. NeuroBench introduces a common set of tools and systematic methodology for inclusive benchmark measurement, delivering an objective reference framework for quantifying neuromorphic approaches in both hardware-independent and hardware-dependent settings. For latest project updates, visit the project website (neurobench.ai).

Yik, Jason [Harvard Univ., Cambridge, MA (United S↗

Low Size, Weight, and Power Neuromorphic Computing to Improve Combustion Engine Efficiency

Neuromorphic computing offers one path forward for AI at the edge. However, accessing and effectively utilizing a neuromorphic hardware platform is non-trivial. In this work, we present a complete pipeline for neuromorphic computing at the edge, including a small, inexpensive, low-power, FPGA-based neuromorphic hardware platform, a training algorithm for designing spiking neural networks for neuromorphic hardware, and a software framework for connecting those components. We demonstrate this pipeline on a real-world application, engine control for a spark-ignition internal combustion engine. We illustrate how we connect engine simulations with neuromorphic hardware simulations and training software to produce hardware-compatible spiking neural networks that perform engine control to improve fuel efficiency. We present initial results on the performance of these spiking neural networks and illustrate that they outperform open-loop engine control. We also give size, weight, and power estimates for a deployed solution of this type.

Schuman, Catherine↗

Quantum materials for energy-efficient neuromorphic computing: Opportunities and challenges

Neuromorphic computing approaches become increasingly important as we address future needs for efficiently processing massive amounts of data. The unique attributes of quantum materials can help address these needs by enabling new energy-efficient device concepts that implement neuromorphic ideas at the hardware level. In particular, strong correlations give rise to highly non-linear responses, such as conductive phase transitions that can be harnessed for short- and long-term plasticity. Similarly, magnetization dynamics are strongly non-linear and can be utilized for data classification. This Perspective discusses select examples of these approaches and provides an outlook on the current opportunities and challenges for assembling quantum-material-based devices for neuromorphic functionalities into larger emergent complex network systems.

36 MATERIALS SCIENCE↗

Maximized lateral inhibition in paired magnetic domain wall racetracks for neuromorphic computing

Lateral inhibition is an important functionality in neuromorphic computing, modeled after the biological neuron behavior that a firing neuron deactivates its neighbors belonging to the same layer and prevents them from firing. In most neuromorphic hardware platforms lateral inhibition is implemented by external circuitry, thereby decreasing the energy efficiency and increasing the area overhead of such systems. Recently, the domain wall—magnetic tunnel junction (DW-MTJ) artificial neuron is demonstrated in modeling to be intrinsically inhibitory. Without peripheral circuitry, lateral inhibition in DW-MTJ neurons results from magnetostatic interaction between neighboring neuron cells. However, the lateral inhibition mechanism in DW-MTJ neurons has not been studied thoroughly, leading to weak inhibition only in very closely-spaced devices. This work approaches these problems by modeling current- and field- driven DW motion in a pair of adjacent DW-MTJ neurons. We maximize the magnitude of lateral inhibition by tuning the magnetic interaction between the neurons. The results are explained by current-driven DW velocity characteristics in response to an external magnetic field and quantified by an analytical model. Dependence of lateral inhibition strength on device parameters is also studied. Finally, lateral inhibition behavior in an array of 1000 DW-MTJ neurons is demonstrated. Our results provide a guideline for the optimization of lateral inhibition implementation in DW-MTJ neurons. Finally, with strong lateral inhibition achieved, a path towards competitive learning algorithms such as the winner-take-all are made possible on such neuromorphic devices.

77 NANOSCIENCE AND NANOTECHNOLOGY↗

An Interface–Type Memristive Device for Artificial Synapse and Neuromorphic Computing

Interface-type (IT) metal/oxide Schottky memristive devices have attracted considerable attention over filament-type (FT) devices for neuromorphic computing because of their uniform, filament-free, and analog resistive switching (RS) characteristics. The most recent IT devices are based on oxygen ions and vacancies movement to alter interfacial Schottky barrier parameters and thereby control RS properties. However, the reliability and stability of these devices have been significantly affected by the undesired diffusion of ionic species. Herein, a reliable interface-dominated memristive device is demonstrated using a simple Au/Nb-doped SrTiO 3 (Nb:STO) Schottky structure. The Au/Nb:STO Schottky barrier modulation by charge trapping and detrapping is responsible for the analog resistive switching characteristics. Because of its interface-controlled RS, the proposed device shows low device-to-device, cell-to-cell, and cycle-to-cycle variability while maintaining high repeatability and stability during endurance and retention tests. Furthermore, the Au/Nb:STO IT memristive device exhibits versatile synaptic functions with an excellent uniformity, programmability, and reliability. A simulated artificial neural network with Au/Nb:STO synapses achieves a high recognition accuracy of 94.72% for large digit recognition from MNIST database. These results suggest that IT resistive switching can be potentially used for artificial synapses to build next-generation neuromorphic computing.

36 MATERIALS SCIENCE↗

Real-Time Evolution and Deployment of Neuromorphic Computing at The Edge

Extremely low power neuromorphic systems are well-suited for deployment to the edge for many applications. In many use cases of neuromorphic computing for control, a spiking neural network is trained off-line using a simulation and then deployed to a neuromorphic system at the edge, where it will operate without ongoing training or learning. However, it may be desirable to continue training or learning at the edge to refine or adapt to the real-world system. In this work, we propose an approach for performing real-time evolutionary optimization for spiking neural networks for neuromorphic deployment at the edge. In particular, we propose a combination of simulation and real-world evaluations, along with feedback from the real-world environment, to train spiking neural networks for continuous deployment to the edge. We show that the real-time evolution at the edge approach achieves comparable performance to an evolution approach that requires constant evaluation in the realworld environment.

Schuman, Catherine↗

Multi-level, forming and filament free, bulk switching trilayer RRAM for neuromorphic computing at the edge

CMOS-RRAM integration holds great promise for low energy and high throughput neuromorphic computing. However, most RRAM technologies relying on filamentary switching suffer from variations and noise, leading to computational accuracy loss, increased energy consumption, and overhead by expensive program and verify schemes. We developed a filament-free, bulk switching RRAM technology to address these challenges. We systematically engineered a trilayer metal-oxide stack and investigated the switching characteristics of RRAM with varying thicknesses and oxygen vacancy distributions to achieve reliable bulk switching without any filament formation. We demonstrated bulk switching at megaohm regime with high current nonlinearity, up to 100 levels without compliance current. We developed a neuromorphic compute-in-memory platform and showcased edge computing by implementing a spiking neural network for an autonomous navigation/racing task. Our work addresses challenges posed by existing RRAM technologies and paves the way for neuromorphic computing at the edge under strict size, weight, and power constraints.

97 MATHEMATICS AND COMPUTING↗

The organic redox transistor for neuromorphic computing

Inspired by the in-memory computing architectures of biological systems, neuromorphic computing using crossbar arrays of artificial synapses based on non-volatile memory (NVM) devices with variable conductances has emerged as a new paradigm to enable massively parallel and ultra-low power computing hardware for data centric applications. Although inference has been demonstrated successfully using crossbars based on a variety of NMV technologies, efficient learning and scaling to large arrays (>10 6 elements) remains a challenge due to the synaptic elements' non-ideal electrical characteristics which degrades ANN accuracy. A further challenge is that in the conductive state memristors draw large currents >μA resulting in significant voltage drops in the interconnect wires and increased probability of failure in scaled arrays. We suggest the organic polymer redox transistor (RT) is an alternate approach that could solve many of these challenges, enabling both inference and parallel outer product updates, as recently demonstrated by Fuller et al. An RT consists of redox-active channel and gate electrodes in contact with a liquid or solid electrolyte. lon insertion through the electrolyte controls the channel electronic conductivity, while electron transfer through an external circuit maintains overall charge neutrality. Unlike a rechargeable battery, in the RT the voltage built-up across the electrolyte is kept to a minimum (typically <100 mV) by using the same material for the gate and channel. Elimination of the voltage offset simplifies integration of the RT into programmable arrays by enabling the use of various selectors. RTs based on inorganic and organic materials have been recently demonstrated with conductance tuning occurring at potentials of just a few mV and hundreds to thousands of linearly and symmetrically programmable conductance states, enabling near ideal accuracy in neural network simulations. Introduced in the 1980's, redox transistors with metallic gate electrodes and organic channel materials, also known as organic electrochemical transistors (OECTs), have been explored for a variety of applications such as chem- and bio-sensing, neural interfaces, and low cost printed circuits. A typical channel material for OECTs is the conducting polymer poly(3,4-ethylenedioxythiophene) doped with poly(styrene sulfonate) (PEDOT:PSS). PEDOT is a p-type semiconducting polymer with mobile positively charged polarons that hop chain-to-chain.

Talin, Albert Alec↗

Leveraging dendritic complexity for neuromorphic computing

Abstract Beyond-von Neumann computing approaches are necessary to sustain the growth of microelectronics and the increasing appetite for artificial intelligence/machine learning algorithms. Neuromorphic computing is an emerging paradigm that takes inspiration from the brain to provide a path forward to improve the computational efficiency and computational density of next-generation computing architectures. In nature, we observe brains performing complex computations with a much smaller energy footprint than conventional computing approaches. Current neuromorphic systems are focused primarily on scalability, namely, increasing the number of computational units (neurons) and connections between units (synapses). However, for brain-like cognition and efficiency in next-generation computing hardware, we need increased complexity in function, as well as improved connection density for scalability. Here, we present our work that aims to incorporate dendrites for ‘compute-on-wire’ in neuromorphic architectures to increase the computational complexity (e.g. number of programmable parameters, nonlinear dynamics) as well as computational efficiency (energy/compute) of artificial neural networks (ANNs). We do this by showcasing neuromorphic dendrite elements that can be leveraged for various applications. We will present examples of neuroscience-inspired direction-selective circuits and an ANN with active dendrites leveraging shunting inhibition. We also demonstrate the benefits of using dendrites in deep neural networks. To conclude, we discuss how we can utilize emerging hardware devices in these systems and design next-generation neuromorphic architectures with dendrites.

Cardwell, Suma G. (ORCID:0000000226575545)↗

Workshop on Manufacturing and Integration Challenges for Analog and Neuromorphic Computing

The U.S. Department of Energy’s (DOE’s) Advanced Manufacturing Office (AMO) held its third virtual workshop on Semiconductor R&D for Energy Efficiency on August 11-13, 2021. This public workshop – titled “Manufacturing and Integration Challenges for Analog and Neuromorphic Computing” – brought together more than 180 leading scientific and technical experts to identify challenges and opportunities to improve manufacturing capabilities for analog and neuromorphic computing architectures to significantly increase energy efficiency of microelectronic devices. The workshop featured perspectives of researchers from national laboratories, universities, government agencies, and industry with expertise in novel and emerging devices, processes, and metrology and characterization. This workshop is intended to inform an AMO research, development, demonstration, and deployment (RDD&D) plan to significantly reduce semiconductor energy use by 2030. It was co-sponsored by the Semiconductor Research Corporation (SRC) and the DOE Office of Science’s Advanced Scientific Computing Research (ASCR).

97 MATHEMATICS AND COMPUTING↗

An optoelectronic heterostructure for neuromorphic computing: CdS/V 3 O 5

Nonvolatile resistive switching is one of the key phenomena for emerging applications in optoelectronics and neuromorphic computing. In most of the cases, an electric field is applied to a two terminal dielectric material device and leads to the formation of a low resistance filament due to ion migration. However, the stochastic nature of the ion migration can be an impediment for the device robustness and controllability, with uncontrolled variations of high and low resistance states or threshold voltages. Here, we report an optically induced resistive switching based on a CdS/V 3 O 5 heterostructure which can overcome this issue. V 3 O 5 is known to have a second order insulator to metal transition around T c ≈ 415 K, with an electrically induced threshold switching at room temperature. Upon illumination, the direct transfer of the photoinduced carriers from the CdS into V 3 O 5 produces a nonvolatile resistive switching at room temperature. The initial high resistance can be recovered by reaching the high temperature metallic phase, i.e., temperatures above T c . Interestingly, this resistive switching becomes volatile around the T c . In conclusion, by locally manipulating the volatile and nonvolatile resistive switching using electric field and light, this system is a promising platform for hardware based neuromorphic computing implementations.

97 MATHEMATICS AND COMPUTING↗

Evaluation of fluxon synapse device based on superconducting loops for energy efficient neuromorphic computing

With Moore’s law nearing its end due to the physical scaling limitations of CMOS technology, alternative computing approaches have gained considerable attention as ways to improve computing performance. Here, we evaluate performance prospects of a new approach based on disordered superconducting loops with Josephson-junctions for energy efficient neuromorphic computing. Synaptic weights can be stored as internal trapped fluxon states of three superconducting loops connected with multiple Josephson-junctions (JJ) and modulated by input signals applied in the form of discrete fluxons (quantized flux) in a controlled manner. The stable trapped fluxon state directs the incoming flux through different pathways with the flow statistics representing different synaptic weights. We explore implementation of matrix–vector-multiplication (MVM) operations using arrays of these fluxon synapse devices. We investigate the energy efficiency of online-learning of MNIST dataset. Our results suggest that the fluxon synapse array can provide ~100× reduction in energy consumption compared to other state-of-the-art synaptic devices. This work presents a proof-of-concept that will pave the way for development of high-speed and highly energy efficient neuromorphic computing systems based on superconducting materials.

42 ENGINEERING↗

Redox transistors based on TiO 2 for analogue neuromorphic computing

The ability to train deep neural networks on large data sets have made significant impacts onto artificial intelligence, but consume significant amounts of energy due to the need to move information from memory to logic units. In-memory "neuromorphic" computing presents an alternative framework that processes information directly on memory elements. In-memory computing has been limited by the poor performance of the analogue information storage element, often phase-change memory or memristors. To solve this problem, we developed two types of "redox transistors" using TiO 2 (anatase) which stores analogue information states through the electrochemical concentration of dopants in the crystal. The first type of redox transistor uses lithium as the electrochemical dopant ion, and its key advantage is low operating voltage. The second uses oxygen vacancies as the dopant, which is CMOS compatible and can retain state even when scaled to nanosized dimensions. Both devices offer significant advantages in terms of predictable analogue switching over conventional filamentary-based devices, and provide a significant advance in developing materials and devices for neuromorphic computing.

36 MATERIALS SCIENCE↗

Easy-plane spin Hall nano-oscillators as spiking neurons for neuromorphic computing

Here we show analytically using a macrospin approximation that easy-plane spin Hall nano-oscillators excited by a spin current polarized perpendicularly to the easy plane have phase dynamics analogous to that of Josephson junctions. Similarly to Josephson junctions, they can reproduce the spiking behavior of biological neurons that is appropriate for neuromorphic computing. To take advantage of typical spin-orbit torques, we use a nanoconstriction geometry, in which the magnetostatic interaction and magnetocrystalline anisotropy are tuned to create an easy plane that includes the interface normal direction. We perform micromagnetic simulations of such oscillators realized in this geometry and show that the easy-plane spiking dynamics is preserved in this experimentally feasible architecture. Finally we simulate two elementary neural network blocks that implement operations essential for neuromorphic computing. First, we show that output spikes energies from two neurons can be summed and injected into a following layer neuron and second, we demonstrate that outputs can be multiplied by synaptic weights implemented by locally modifying the anisotropy.

36 MATERIALS SCIENCE↗

Computational Complexity of Neuromorphic Algorithms

Neuromorphic computing has several characteristics that make it an extremely compelling computing paradigm for post Moore computation. Some of these characteristics include intrinsic parallelism, inherent scalability, collocated processing and memory, and event-driven computation. While these characteristics impart energy efficiency to neuromorphic systems, they do come with their own set of challenges. One of the biggest challenges in neuromorphic computing is to establish the theoretical underpinnings of the computational complexity of neuromorphic algorithms. In this paper, we take the first steps towards defining the space and time complexity of neuromorphic algorithms. Specifically, we describe a model of neuromorphic computation and state the assumptions that govern the computational complexity of neuromorphic algorithms. Next, we present a theoretical framework to define the computational complexity of a neuromorphic algorithm. We explicitly define what space and time complexities mean in the context of neuromorphic algorithms based on our model of neuromorphic computation. Finally, we leverage our approach and define the computational complexities of six neuromorphic algorithms: constant function, successor function, predecessor function, projection function, neuromorphic sorting algorithm and neighborhood subgraph extraction algorithm.

Date, Prasanna↗

Comparing quantum annealing and spiking neuromorphic computing for sampling binary sparse coding QUBO problems

We consider the problem of computing a sparse binary representation of an image. Given an image and an overcomplete, non-orthonormal basis, we aim to find a sparse binary vector indicating the minimal set of basis vectors that when added together best reconstruct the given input. We formulate this problem with an L 2 loss on the reconstruction error, and an L 0 loss on the binary vector enforcing sparsity. First, we solve the sparse representation QUBOs by solving them both on a D-Wave quantum annealer with Pegasus chip connectivity, as well as on the Intel Loihi 2 spiking neuromorphic processor using a stochastic Non-equilibrium Boltzmann Machine (NEBM). Second, using Quantum Evolution Monte Carlo with Reverse Annealing and iterated warm starting on Loihi 2 to evolve the solution quality from the respective machines. We demonstrate that both quantum annealing and neuromorphic computing are suitable for solving binary sparse coding QUBOs.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

Harnessing the Second-Order Metal−Insulator Transition for Neuromorphic Computing

Vanadium oxides are widely studied phase change materials for brain-inspired computing architectures. Systems like VO 2 and V 2 O 3 exhibit first-order metal−insulator transitions (MITs) with hysteresis and percolative switching, increasing stochasticity and device variability. Here, we focus on the less explored Magnéli phase V 4 O 7 , which undergoes a continuous, non-hysteretic, second-order MIT. This surprisingly enables highly reproducible volatile resistive switching in spiking-neuron-type devices. We synthesize V 4 O 7 films, characterize their structural and transport properties, and demonstrate voltage and current-driven threshold switching with electrothermal feedback. In a Pearson–Anson oscillator, V 4 O 7 devices produce stable, tunable spiking across 20–200 kHz, with consistent operation among multiple devices. We introduce a numerical analog leaky-integrate-and-fire (aLIF) model that captures waveform shapes and their dependence on load resistance, temperature, and voltage. Furthermore, these findings suggest that second-order MIT materials like V 4 O 7 are promising for deterministic, scalable spiking neuron arrays for neuromorphic computing.

V4O7↗