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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sources NASA NTRS DOE OSTI

DOE OSTI2025

Securing 3D NAND Without Density Loss via In-Situ Encryption Using a Single Transistor XOR Cell

In this article, we push lightweight XOR-based in-situ encryption to extreme density by proposing a singletransistor XOR memory cell and applying it to 3D NAND, enabling secure data storage without density loss. Using a ferroelectric field-effect transistor (FeFET) as an example technology, we demonstrate that: i) a single-transistor memory can realize the XOR function by exploiting the ability to charge the source and drain separately and control current flow direction, eliminating the need for conventional encrypted cells that rely on complementary devices; ii) with a XOR-based cipher, encryption and decryption can be mapped to in-situ array operations, where ciphertext is stored as the threshold voltage (VTH) states of FeFETs in a NAND string, and decryption is achieved through read operations using key-dependent complementary source/drain bias; iii) the proposed technique is scalable to multi-level cell (MLC) storage by encrypting and decrypting data bit by bit; iv) using an integrated NAND FeFET array, we experimentally demonstrate encryption and decryption operations for both single-level cell (SLC) and MLC storage; v) systemlevel benchmarking shows that the proposed technique achieves 48× and 278× improvements in encryption and decryption throughput, respectively, compared to AES.

36 MATERIALS SCIENCE↗

DOE OSTI2024

Variation Tolerant and Energy-Efficient Charge Domain Compute-in-Memory Array with Binary and Multi-Level Cell Ferroelectric FET

Here, in this work, we present a variation-tolerant and energy-efficient charge-domain Ferroelectric FET (FeFET) based Compute-in-Memory (CiM) array design that is compatible with both binary and multi-level cell memory sensing. We demonstrate that: 1) by exploiting FeFET as a nonvolatile switch, its high ON/OFF ratio in the subthreshold region can suppress the error introduced by the inaccurate ON state conductance, thus realizing robust CiM operations, unlike the current-domain CiM design where the computation results is highly sensitive to the device conductance variation; 2) by leveraging a dense dynamic random access memory (DRAM)-like 1FeFET1C cell structure, the proposed design benefits from the existing high density DRAM establishment while also significantly relaxing the capacitor retention and transistor leakage requirement; 3) the charge-domain CiM supports both binary FeFET with minimum overhead and MLC FeFET with tolerable latency for MLC state sensing, whose efficacy is validated experimentally on both cell-level and array-level; 4) the proposed CiM shows much better device variation resilience than conventional current-domain CiM, and also improves inference accuracy. Macro-level evaluation results demonstrate significantly higher energy efficiency and area efficiency compared to prior CiM works.

Duan, Jiahui [University of Notre Dame, IN (United↗

DOE OSTI2025

On-chip frequency-bin quantum photonics

Abstract Frequency-bin encoding furnishes a compelling pathway for quantum information processing systems compatible with established lightwave infrastructures based on fiber-optic transmission and wavelength-division multiplexing. Yet although significant progress has been realized in proof-of-principle tabletop demonstrations, ranging from arbitrary single-qubit gates to controllable multiphoton interference, challenges in scaling frequency-bin processors to larger systems remain. In this Perspective, we highlight recent advances at the intersection of frequency-bin encoding and integrated photonics that are fundamentally transforming the outlook for scalable frequency-based quantum information. Focusing specifically on results on sources, state manipulation, and hyperentanglement, we envision a possible future in which on-chip frequency-bin circuits fulfill critical roles in quantum information processing, particularly in communications and networking.

electro-optic modulators↗

DOE OSTI2025

Vertical 2T-nC FeRAM Demonstration: BEOL Read Transistor for 4F 2 Memory Strings and Two-Terminal Selector Design for Polarization Disturb Mitigation

In this work, we demonstrate a vertical 2T-nC FeRAM with a back-end-of-line (BEOL) read transistor (T R ) for 4F 2 string and propose a selector design to mitigate polarization disturb in passive capacitor crossbar arrays. Key contributions include: 1) successful integration and operation composed of a Si MOSFET write transistor (T W ), 3-layer cylindrical ferroelectric capacitors, and Si-doped In 2 O 3 BEOL T R , demonstrating the feasibility of 4F 2 2T−nC string; 2) introducing nonlinearity into the capacitor stack to suppress ferroelectric voltage drop under inhibition biases while maintaining sufficient write voltage, reducing disturbance; 3)modeling and experimental validation of inserting a metalsemiconductor (a-Si)-metal (MSM) selector into the capacitor in mitigating the disturb, particularly achieving 9x reduction of disturb after 10 6 cycles in the V W /2 scheme.

42 ENGINEERING↗