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At least 37 records · Page 2

Testability enhancement in digital system design

A new way of employing hardware redundancy to reduce the number of tests for fault detection in both combinational and synchronous sequential circuits is investigated. An approach is presented for utilizing systematic redundancy to simplify design work. Models for PLM (programmable logic module) and CMM (controllable memory module) are depicted. Systematic design and detection procedures are described. Using these procedures, an easily testable circuit (for stuck faults) can be designed. In contrast to the earlier results on fault detection in logic circuit, two tests are needed to detect any stuck faults of combinational logic circuit. Four tests are necessary and sufficient to detect any stuck faults of elementary logic gates and the malfunction of flip-flops of synchronous sequential circuit using Delay flip-flops or trigger flip-flops.

Chuang, C. S.↗

LED instrument approach instruction display

A display employing light emitting diodes (LED's) was developed to demonstrate the feasibility of such displays for presenting landing and navigation information to reduce the workload of general aviation pilots during IFR flight. The display consists of a paper tape reader, digital memory, control electronics, digital latches, and LED alphanumeric displays. A presentable digital countdown clock-timer is included as part of the system to provide a convenient means of monitoring time intervals for precise flight navigation. The system is a limited capability prototype assembled to test pilot reaction to such a device under simulated IFR operation. Pilot opinion indicates that the display is helpful in reducing the IFR pilots workload when used with a runway approach plate. However, the development of a compact, low power second generation display was recommended which could present several instructions simultaneously and provide information update capability. A microprocessor-based display could fulfill these requirements.

Meredith, B. D.↗

Large-scale turbulence simulation on the Navier-Stokes Computer

Analytical techniques for turbulent air or water flow over vehicles and for the development of active control methods are described, with a focus on simulations being implemented on the Navier-Stokes Computer (NSC) at Princeton University. Consideration is given to the general NSC architecture (the central control, memory, and processing units; the switching network; and the prototype NSC), the algorithm for large-scale MHD turbulence (Orszag and Tang, 1979), and the pipeline configurations. Extensive diagrams and flow charts are provided.

Hayder, M. E.↗

How to handle 6GBytes a night and not get swamped

The Macho Project has undertaken a 5 year effort to search for dark matter in the halo of the Galaxy by scanning the Magellanic Clouds for micro-lensing events. Each evening's raw image data will be reduced in real-time into the observed stars' photometric measurements. The actual search for micro-lensing events will be a post-processing operation. The theoretical prediction of the rate of such events necessitates the collection of a large number of repeated exposures. The project designed camera subsystem delivers 64 Mbytes per exposure with exposures typically occurring every 500 seconds. An ideal evening's observing will provide 6 Gbytes of raw image data and 40 Mbytes of reduced photometric measurements. Recognizing the difficulty of digging out from a snowballing cascade of raw data, the project requires the real-time reduction of each evening's data. The software team's implementation strategy centered on this non-negotiable mandate. Accepting the reality that 2 full time people needed to implement the core real-time control and data management system within 6 months, off-the-shelf vendor components were explored to provide quick solutions to the classic needs for file management, data management, and process control. Where vendor solutions were lacking, state-of-the-art models were used for hand tailored subsystems. In particular, petri nets manage process control, memory mapped bulletin boards provide interprocess communication between the multi-tasked processes, and C++ class libraries provide memory mapped, disk resident databases. The differences between the implementation strategy and the final implementation reality are presented. The necessity of validating vendor product claims are explored. Both the successful and hindsight decisions enabling the collection and processing of the nightly data barrage are reviewed.

Allsman, R.↗

Information Switching Processor (ISP) contention analysis and control

In designing a satellite system with on-board processing, the selection of a switching architecture is often critical. The on-board switching function can be implemented by circuit switching or packet switching. Destination-directed packet switching has several attractive features, such as self-routing without on-board switch reconfiguration, no switch control memory requirement, efficient bandwidth utilization for packet switched traffic, and accommodation of circuit switched traffic. Destination-directed packet switching, however, has two potential concerns: (1) contention and (2) congestion. And this report specifically deals with the first problem. It includes a description and analysis of various self-routing switch structures, the nature of contention problems, and contention and resolution techniques.

Inukai, Thomas↗

Towards a Qualification Data Set: Expanded SEE Data on the P2020 Processor

Earlier P2020 SEE data are compared and expanded to a recent die revision, significantly increasing samples tested by protons by five devices, and by heavy ions by five devices. Earlier tested SEE types are found to be fairly similar in register, L1 cache, L2 cache, and CPU crashes. New test methods give SEE performance for the flash memory controller, watchdog circuit, and a built-in Ethernet port on the P2020 processor. Results from heavy ion and proton tests are presented, with data separated over a large number of specific error types and test programs.

Vartanian, Sargeh↗

Conserving power in computer memories

Power control system for electronic memories saves energy by switching off power to portions of memories that are not in use. Although power-off period lasts only a few microseconds or milliseconds, it amounts to sizable part of overall read/write cycle timer; large energy savings can be realized.

Source record↗

Additive Manufacturing and Experimental Characterization of Nickel-Titanium Shape-Memory Alloy Wick Structures and Heat Pipes for Spacecraft Thermal Control

Shape memory alloys (SMA), such as those based on nickel-titanium (NiTi), are increasingly being applied as multifunctional spacecraft components. For thermal management applications, NiTi flow tubing hinges and self-deploying loop heat pipes have been demonstrated. Emerging additive manufacturing (AM) processes are enabling more complex SMA devices than can be formed from conventional plain wire, tubing, and sheet stock materials. This paper presents our progress toward applying powder bed fusion AM to producing porous NiTi wicks and NiTi-H2O heat pipes, which could be embedded in thermally deploying radiators for spacecraft thermal management. AM near-equiatomic NiTi (55.1 wt% Ni) porous wick specimens were produced with a range of deposition parameters. Transient acetone rate-of-rise experiments were performed to estimate wick permeability (K) and average pore radius (r_pore) values and identify parameter sets with high capillary performance. Surface treatments were evaluated to achieve hydrophilic wick structures. Evaluated treatments included chemical oxide growth with H2O2, oxide and sodium titanate growth with NaOH solution, and ultrasonic cleaning with specialty detergents that can remove hydrocarbon contaminants. The most durable hydrophilic surface conditions were obtained with the NaOH treatment. High performing wick deposition parameters were used to produce a full AM NiTi heat pipe, which was treated with NaOH solution to activate the wick. This heat pipe was operated on a test stand in the inverted configuration (upper evaporator and lower condenser), and demonstrated stable nearly isothermal operation for 150 hrs.

Thermal management↗

Additive Manufacturing and Experimental Characterization of Nickel-Titanium Shape-Memory Alloy Wick Structures and Heat Pipes for Spacecraft Thermal Control

Shape memory alloys (SMA), such as those based on nickel-titanium (NiTi), are increasingly being applied as multifunctional spacecraft components. For thermal management applications, NiTi flow tubing hinges and self-deploying loop heat pipes have been demonstrated. Emerging additive manufacturing (AM) processes are enabling more complex SMA devices than can be formed from conventional plain wire, tubing, and sheet stock materials. This paper presents our progress toward applying powder bed fusion AM to producing porous NiTi wicks and NiTi-H2O heat pipes, which could be embedded in thermally deploying radiators for spacecraft thermal management. AM near-equiatomic NiTi (55.1 wt% Ni) porous wick specimens were produced with a range of deposition parameters. Transient acetone rate-of-rise experiments were performed to estimate wick permeability (K) and average pore radius (r_pore) values and identify parameter sets with high capillary performance. Surface treatments were evaluated to achieve hydrophilic wick structures. Evaluated treatments included chemical oxide growth with H2O2, oxide and sodium titanate growth with NaOH solution, and ultrasonic cleaning with specialty detergents that can remove hydrocarbon contaminants. The most durable hydrophilic surface conditions were obtained with the NaOH treatment. High performing wick deposition parameters were used to produce a full AM NiTi heat pipe, which was treated with NaOH solution to activate the wick. This heat pipe was operated on a test stand in the inverted configuration (upper evaporator and lower condenser), and demonstrated stable nearly isothermal operation for 150 hrs.

Thermal management↗

Command and Control Software Development Memory Management

This internship was initially meant to cover the implementation of unit test automation for a NASA ground control project. As is often the case with large development projects, the scope and breadth of the internship changed. Instead, the internship focused on finding and correcting memory leaks and errors as reported by a COTS software product meant to track such issues. Memory leaks come in many different flavors and some of them are more benign than others. On the extreme end a program might be dynamically allocating memory and not correctly deallocating it when it is no longer in use. This is called a direct memory leak and in the worst case can use all the available memory and crash the program. If the leaks are small they may simply slow the program down which, in a safety critical system (a system for which a failure or design error can cause a risk to human life), is still unacceptable. The ground control system is managed in smaller sub-teams, referred to as CSCIs. The CSCI that this internship focused on is responsible for monitoring the health and status of the system. This team's software had several methods/modules that were leaking significant amounts of memory. Since most of the code in this system is safety-critical, correcting memory leaks is a necessity.

Programmin↗

An experimental distributed microprocessor implementation with a shared memory communications and control medium

The distributed processing concept is defined in terms of control primitives, variables, and structures and their use in performing a decomposed discrete Fourier transform (DET) application function. The design assumes interprocessor communications to be anonymous. In this scheme, all processors can access an entire common database by employing control primitives. Access to selected areas within the common database is random, enforced by a hardware lock, and determined by task and subtask pointers. This enables the number of processors to be varied in the configuration without any modifications to the control structure. Decompositional elements of the DFT application function in terms of tasks and subtasks are also described. The experimental hardware configuration consists of IMSAI 8080 chassis which are independent, 8 bit microcomputer units. These chassis are linked together to form a multiple processing system by means of a shared memory facility. This facility consists of hardware which provides a bus structure to enable up to six microcomputers to be interconnected. It provides polling and arbitration logic so that only one processor has access to shared memory at any one time.

Mejzak, R. S.↗

Systems, methods, and products for graphically illustrating and controlling a droplet actuator

Systems for controlling a droplet microactuator are provided. According to one embodiment, a system is provided and includes a controller, a droplet microactuator electronically coupled to the controller, and a display device displaying a user interface electronically coupled to the controller, wherein the system is programmed and configured to permit a user to effect a droplet manipulation by interacting with the user interface. According to another embodiment, a system is provided and includes a processor, a display device electronically coupled to the processor, and software loaded and/or stored in a storage device electronically coupled to the controller, a memory device electronically coupled to the controller, and/or the controller and programmed to display an interactive map of a droplet microactuator. According to yet another embodiment, a system is provided and includes a controller, a droplet microactuator electronically coupled to the controller, a display device displaying a user interface electronically coupled to the controller, and software for executing a protocol loaded and/or stored in a storage device electronically coupled to the controller, a memory device electronically coupled to the controller, and/or the controller.

Paik, Philip Y.↗

Information storage at the molecular level - The design of a molecular shift register memory

The control of electron transfer rates is discussed and a molecular shift register memory at the molecular level is described. The memory elements are made up of molecules which can exist in either an oxidized or reduced state and the bits can be shifted between the cells with photoinduced electron transfer reactions. The device integrates designed molecules onto a VLSI substrate. A control structure to modify the flow of information along a shift register is indicated schematically.

Beratan, David N.↗

Shape-Memory-Alloy Actuator For Flight Controls

Report proposes use of shape-memory-alloy actuators, instead of hydraulic actuators, for aerodynamic flight-control surfaces. Actuator made of shape-memory alloy converts thermal energy into mechanical work by changing shape as it makes transitions between martensitic and austenitic crystalline phase states of alloy. Because both hot exhaust gases and cryogenic propellant liquids available aboard launch rockets, shape-memory-alloy actuators exceptionally suited for use aboard such rockets.

Barret, Chris↗

Army/NASA small turboshaft engine digital controls research program

The emphasis of a program to conduct digital controls research for small turboshaft engines is on engine test evaluation of advanced control logic using a flexible microprocessor based digital control system designed specifically for research on advanced control logic. Control software is stored in programmable memory. New control algorithms may be stored in a floppy disk and loaded directly into memory. This feature facilitates comparative evaluation of different advanced control modes. The central processor in the digital control is an Intel 8086 16 bit microprocessor. Control software is programmed in assembly language. Software checkout is accomplished prior to engine test by connecting the digital control to a real time hybrid computer simulation of the engine. The engine currently installed in the facility has a hydromechanical control modified to allow electrohydraulic fuel metering and VG actuation by the digital control. Simulation results are presented which show that the modern control reduces the transient rotor speed droop caused by unanticipated load changes such as cyclic pitch or wind gust transients.

Sellers, J. F.↗

Control of Finite-State, Finite Memory Stochastic Systems

A generalized problem of stochastic control is discussed in which multiple controllers with different data bases are present. The vehicle for the investigation is the finite state, finite memory (FSFM) stochastic control problem. Optimality conditions are obtained by deriving an equivalent deterministic optimal control problem. A FSFM minimum principle is obtained via the equivalent deterministic problem. The minimum principle suggests the development of a numerical optimization algorithm, the min-H algorithm. The relationship between the sufficiency of the minimum principle and the informational properties of the problem are investigated. A problem of hypothesis testing with 1-bit memory is investigated to illustrate the application of control theoretic techniques to information processing problems.

Sandell, Nils R.↗

Distributed memory approaches for robotic neural controllers

The suitability is explored of two varieties of distributed memory neutral networks as trainable controllers for a simulated robotics task. The task requires that two cameras observe an arbitrary target point in space. Coordinates of the target on the camera image planes are passed to a neural controller which must learn to solve the inverse kinematics of a manipulator with one revolute and two prismatic joints. Two new network designs are evaluated. The first, radial basis sparse distributed memory (RBSDM), approximates functional mappings as sums of multivariate gaussians centered around previously learned patterns. The second network types involved variations of Adaptive Vector Quantizers or Self Organizing Maps. In these networks, random N dimensional points are given local connectivities. They are then exposed to training patterns and readjust their locations based on a nearest neighbor rule. Both approaches are tested based on their ability to interpolate manipulator joint coordinates for simulated arm movement while simultaneously performing stereo fusion of the camera data. Comparisons are made with classical k-nearest neighbor pattern recognition techniques.

Jorgensen, Charles C.↗