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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Predictive Models and Novel Accelerated Tests for the Reliability of Cell Metallization in Photovoltaic Modules (Final Report)

Studies of metallization corrosion m photovoltaics have mainly been limited to comparisons of modules placed in accelerated chambers to fielded modules [1]. Damp Heat accelerated tests and phenomenological equations [2] are used to assess metallization corrosion without understanding the effect of UV light and temperature and humidity cycles on encapsulant adhesion degradation. The roles of encapsulant in-and out-diffusions of moisture and encapsulant impurities are important. Furthermore, few photovoltaic metallization corrosion studies included the role of bias and leakage currents, which are crucial in the electrochemical reaction of metallization. Leakage currents can highly accelerate the corrosion mechanism and are important to include in the studies of corrosion. In our research plan, we will address the following gaps in the PV community's understanding of metallization corrosion: (1) metallization corrosion with bias, humidity, and impurities in the encapsulant or metallization; (2) humidity diffusion through fresh and degraded encapsulants; and (3) comparison of model predictions with outdoor field modules and SunPower's extensive data for its back-contact and front-contact fleets [2] along with NREL's store of >20 year old modules. Our goal is to build models and accelerated tests to predict long term degradation of metallization corrosion of photovoltaic modules in the field. Our studies will include metals used in c-Si solar cells (Cu, Ag, and Al) and commonly used encapsulants (EV A (ethylene vinyl acetate), TPO (thermoplastic olefin), and silicone).

14 SOLAR ENERGY↗
DOE OSTI2022

Temperature-dependent charge barrier height of amorphous germanium contact detector

The exploration of germanium (Ge) detectors with amorphous Ge (a-Ge) contacts has drawn attention to the searches for rare-event physics such as dark matter and neutrinoless double-beta decay. The charge barrier height (CBH) of the a-Ge contacts deposited on the detector surface is crucial to suppress the leakage current of the detector in order to achieve a low-energy detection threshold and high-energy resolution. The temperature-dependent CBH of a-Ge contacts for three Ge detectors is analyzed to study the bulk leakage current (BLC) characteristics. The detectors were fabricated at the University of South Dakota using homegrown crystals. The CBH is determined from the BLC when the detectors are operated in the reverse bias mode with a guard-ring structure, which separates the BLC from the surface leakage current (SLC). Here the results show that CBH is temperature dependent. The direct relation of the CBH variation to temperature is related to the barrier inhomogeneities created on the interface of a-Ge and crystalline Ge. The inhomogeneities that occur at the interface were analyzed using the Gaussian distribution model for three detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

Origin of reduced efficiency in GaN-based micro-LEDs studied by scanning near-field optical microscopy

The quantum efficiency of micro-light emitting diodes (micro-LEDs) is lower than that of large area LEDs. This efficiency reduction is typically attributed to the nonradiative Shockley–Read–Hall recombination at the surface defects and current leakage through the sidewall region without a clear distinction between these effects. In this work, we attempt to find out which of these phenomena is most critical for the reduced efficiency of micro-LEDs. This has been done by mapping electroluminescence (EL) and photoluminescence (PL) and measuring PL dynamics in blue GaN micro-LEDs fabricated by dry etching. It has been found that in the as-etched device, the EL intensity is much lower than in devices with KOH etching and atomic layer deposition of SiO 2 . This effect is especially pronounced close to the sidewalls. On the other hand, PL decay times are similar in as-etched and passivated devices, both in their center and at the sidewalls. This allows concluding that the main mechanism of the reduced efficiency of micro-LEDs fabricated by dry etching is the current leakage in the sidewall region and not the nonradiative recombination. The KOH etching has been found to be the most efficient means to eliminate the current leakage.

36 MATERIALS SCIENCE↗
DOE OSTI2022

Schottky contacts to N-polar GaN with SiN interlayer for elevated temperature operation

In this Letter, we unveil the high-temperature limits of N-polar GaN Schottky contacts enhanced by a low-pressure chemical vapor deposited (LPCVD) SiN interlayer. Compared to conventional Schottky diodes, the insertion of a 5 nm SiN lossy dielectric interlayer in-between Ni and N-polar GaN increases the turn-on voltage (V ON ) from 0.4 to 0.9 V and the barrier height ($\phi_B$) from 0.4 to 0.8 eV. This modification also reduces the leakage current at zero bias significantly: at room temperature, the leakage current in the conventional Schottky diode is >103 larger than that observed in the device with the SiN interlayer, while at 200 °C, this ratio increases to 105. Thus, the rectification ratio (ION/IOFF) at ±1.5 V reduces to less than one at 250 °C for the conventional Schottky diode, whereas for SiN-coated diodes, rectification continues until 500 °C. The I–V characteristics of the diode with an SiN interlayer can be recovered after exposure to 400 °C or lower. Contact degradation occurs at 500 °C, although devices are not destroyed yet. Here, we report N-polar GaN Schottky contact operation up to 500 °C using an LPCVD SiN interlayer.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2024

Setups for eliminating static charge of the ATLAS18 strip sensors

Abstract Construction of the new all-silicon Inner Tracker (ITk), developed by the ATLAS collaboration to beable to track charged particles produced at the High-Luminosity LHC, started in 2020 and is expected tocontinue till 2028. The ITk detector will include 18,000 highly segmented and radiation hard n+-in-psilicon strip sensors (ATLAS18), which are being manufactured by Hamamatsu Photonics. Mechanical and electrical characteristics of produced sensors are measured upon their delivery at several institutes participating in a complex Quality Control (QC) program. The QC tests performed on each individual sensor check the overall integrity and quality of the sensor.During the QC testing of ATLAS18 strip sensors, an increased number of sensors thatfailed the electrical tests was observed. In particular, IV measurements indicated an early breakdown,while large areas containing several tens or hundreds of neighbouring strips with low interstrip isolationwere identified by the Full strip tests, and leakage current instabilities were measured in a long-term leakage current stability setup. Moreover, a high surface electrostatic charge reaching a level of several hundreds of volts per inch was measured on a large number of sensors and on the plastic sheets, whichmechanically protect these sensors in their paper envelopes. Accumulated data indicates a clearcorrelation between observed electrical failures and the sensor charge-up.To mitigate the above-described issues, the QC testing sites significantly modified the sensor handlingprocedures and introduced sensor recovery techniques based on irradiation of the sensor surface with UVlight or application of intensive flows of ionized gas. In this presentation, we will describe the setupsimplemented by the QC testing sites to treat silicon strip sensors affected by static charge andevaluate the effectiveness of these setups in terms of improvement of the sensor performance.

Instruments & Instrumentation↗
DOE OSTI2021

Initial tests of large format sensors for the ATLAS ITk strip tracker

For the construction of the Inner Tracker (ITk) as part of the phase-II upgrade programme of the ATLAS detector for the High-Luminosity (HL) LHC, batches of Long Strip (LS) and Short Strip (SS) n + -in-p type micro-strip sensors have been produced by Hamamatsu Photonics and Infineon. The full size sensors measure approximately 98 × 98 mm 2 and are designed and engineered for tolerance against the 9.7 × 10 14 1 MeV n eq /cm 2 fluence expected at the HL-LHC, including a safety factor of 1.5. Each sensor has 2 or 4 columns of 1280 individual channels arranged at 75.5 μ m horizontal pitch. To ensure the sensors comply with their specifications, a Quality Control (QC) procedure has been implemented, comprising measurements on every individual sensor as well as on a sample basis. Every sensor is subjected to an initial visual inspection, after which the full surface of the sensor is captured with very high resolution by an automated camera setup. Non-contact metrology is performed to obtain the sensor surface profile. Electrical measurements establishing the reverse bias leakage current and depletion voltage are then conducted automatically. Sample sensors from every batch are subjected to 40 h of leakage stability checks in controlled atmosphere, and tests on every channel measuring leakage current, coupling capacitance and bias resistance are done. The recorded results are uploaded to a production database following data quality checks. In this paper, QC test validation data and the compiled results for the first batches of production grade sensors are presented. The QC protocol was validated, and the first production sensors were confirmed to be within specification. The results are compared to those from the previous generation of prototype sensors.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗
DOE OSTI2022

Electric current paths in a Si:P delta-doped device imaged by nitrogen-vacancy diamond magnetic microscopy

The recently-developed ability to control phosphorous-doping of silicon at an atomic level using scanning tunneling microscopy, a technique known as atomic precision advanced manufacturing (APAM), has allowed us to tailor electronic devices with atomic precision, and thus has emerged as a way to explore new possibilities in Si electronics. In these applications, critical questions include where current flow is actually occurring in or near APAM structures as well as whether leakage currents are present. In general, detection and mapping of current flow in APAM structures are valuable diagnostic tools to obtain reliable devices in digital-enhanced applications. In this report, we used nitrogen-vacancy (NV) centers in diamond for wide-field magnetic imaging (with a few-mm field of view and micron-scale resolution) of magnetic fields from surface currents flowing in an APAM test device made of a P delta-doped layer on a Si substrate, a standard APAM witness material. We integrated a diamond having a surface NV ensemble with the device (patterned in two parallel mm-sized ribbons), then mapped the magnetic field from the DC current injected in the APAM device in a home-built NV wide-field microscope. The 2D magnetic field maps were used to reconstruct the surface current densities, allowing us to obtain information on current paths, device failures such as choke points where current flow is impeded, and current leakages outside the APAM-defined P-doped regions. Analysis on the current density reconstructed map showed a projected sensitivity of ~0.03 A m -1 , corresponding to a smallest-detectable current in the 200 μm wide APAM ribbon of ~6 μA. These results demonstrate the failure analysis capability of NV wide-field magnetometry for APAM materials, opening the possibility to investigate other cutting-edge microelectronic devices.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2021

Low-Temperature Annealing of CdZnTeSe under Bias

We performed a gradual low-temperature annealing up to 360 K on a CdZnTeSe radiation detector equipped with gold and indium electrodes under bias at both polarities. We observed significant changes in the detector’s resistance and space-charge accumulation. This could potentially lead to the control and improvement of the electronic properties of the detector because the changes are accompanied with the reduction in the bulk dark current and surface leakage current. In this article, we present the results of a detailed study of the internal electric field and conductivity changes in CdZnTeSe detector for various annealing steps under bias taking into account different polarities during annealing and subsequent characterization. We observed that low-temperature annealing results in an increase in the barrier height at the contacts that, in general, reduces the dark current and decreases the positive space charge present in the sample compared to the pre-annealed condition.

47 OTHER INSTRUMENTATION↗
DOE OSTI2023

Oxygen vacancy contributions to the electrical stress response and endurance of ferroelectric hafnium zirconium oxide thin films

Despite its scalability and CMOS process compatibility, the limited endurance and sub-optimal stress response of ferroelectric Zr-substituted hafnia [(Hf,Zr)O 2 ] have been one of the key impediments toward its integration into practical device and technology applications. Here, using electrical measurements complemented by photoluminescence spectroscopy, we investigate the underlying mechanisms behind this behavior in 10 nm thick W/Hf 0.5 Zr 0.5 O 2 /W capacitors. Analyzing the evolution of leakage current with stress cycles and the spectroscopic response of the stress-induced leakage current, we attribute the behavior to defect levels, which lie at 0.6 eV from the conduction band edge of the ferroelectric. Photoluminescence spectroscopy, in turn, further corroborates the defect level's position within the bandgap while enabling its attribution to the presence of oxygen vacancies. Furthermore, this work helps to identify oxygen vacancies as the key factor responsible for the degraded endurance and stress response in (Hf,Zr)O 2 and subsequently motivates the exploration of methods to reduce the oxygen vacancy concentrations without destabilizing the ferroelectric orthorhombic phase.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

Ultrathin ferroic HfO 2 –ZrO 2 superlattice gate stack for advanced transistors

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage. This led to a fundamental change in the gate stack in 2008, the incorporation of high-dielectric-constant HfO 2 , which remains the material of choice to date. Here we report HfO 2 –ZrO 2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric–antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal–oxide–semiconductor capacitors is equivalent to an effective SiO 2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO 2 -based high-dielectric-constant gate stacks without scavenging the interfacial SiO 2 , which has adverse effects on the electron transport and gate leakage current. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO 2 –ZrO 2 multilayers, stabilized with competing ferroelectric–antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO 2 -based high-dielectric-constant materials.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Gallium Oxide Heterojunction Diodes for 400 °C High‐Temperature Applications

β ‐Ga 2 O 3 ‐based semiconductor devices are expected to have significantly improved high‐power and high‐temperature performance due to its ultrawide bandgap of close to 5 eV. However, the high‐temperature operation of these ultrawide‐bandgap devices is usually limited by the relatively low 1–2 eV built‐in potential at the Schottky barrier with most high‐work‐function metals. Herein, heterojunction p ‐NiO/n‐ β ‐Ga 2 O 3 diodes fabrication and optimization for high‐temperature device applications are reported, demonstrating a current rectification ratio ( I ON / I OFF ) of more than 10 6 at 410 °C. The NiO heterojunction diode can achieve higher turn‐on ( V ON ) voltage and lower reverse leakage current compared to the Ni‐based Schottky diode fabricated on the same single‐crystal β ‐Ga 2 O 3 substrate, despite charge transport dominated by interfacial recombination. Electrical characterization and device modeling show that these advantages are due to a higher built‐in potential and additional band offset. These results suggest that heterojunction p–n diodes based on β ‐Ga 2 O 3 can significantly improve high‐temperature electronic device and sensor performance.

Sohel, Shahadat H.↗
DOE OSTI2022

Review of Potential–Induced Degradation in Bifacial Photovoltaic Modules

Bifacial modules are increasingly deployed in the field and are expected to represent half of the market share within 10 years. Their rear structure differs from monofacial modules to allow additional light absorption. However, it brings new reliability challenges to address. In particular, the risk of potential-induced degradation (PID) is increased as both module sides are impacted. Different PID processes have been identified in the literature: shunting type (PID-s), polarization type (PID-p), Na penetration type, and corrosion type (PID-c). Their occurrence depends on the photovoltaic system configuration as well as the module's materials. Apart from PID-s, PID processes are not well understood and extensive research is needed to elucidate the PID scenario and underlying mechanisms. Herein, current knowledge about PID processes and their impact on the main bifacial modules in the market are gathered with the aim to guide future research. Bifacial module technologies and leakage current paths leading to PID are described. Indoor and outdoor PID testing methods are detailed. For each bifacial module technology, the PID processes are investigated with their indicators, mechanism and recovery process. Furthermore, PID-impacting factors and limitation solutions are finally reported and a state of the art on PID modeling is presented.

14 SOLAR ENERGY↗
DOE OSTI2025

Thermally induced PtOx interfacial layer enhances stability of Pt/β-Ga2O3 vertical Schottky diodes

This study investigates the long-term stability of Pt/β-Ga2O3 field-plated Schottky barrier diodes at high temperatures, with extended thermal cycling and soaking stress. The device characteristics reveal a strong dependence on operating temperature, leading to an ON/OFF current ratio of ∼10× at ±3 V and 600 °C. Extensive thermal cycling (25 cycles over 100 h) between room temperature and 350 °C shows that leakage currents stabilize after the initial ten cycles. This stabilization is likely due to the formation of a thin PtOx layer at the Pt/β-Ga2O3 interface, as confirmed by high-resolution scanning transmission electron microscopy. Further exposure to a constant 350 °C environment for 10 h reveals a slight increase in the leakage current from 10−7 to 10−6 A at −5 V and degradation of the forward current, due to potential thermodynamic instability of the Ohmic contacts. This study provides insights into the changes in the Pt/β-Ga2O3 diode performance with thermal stress, offering a basis for predicting the device’s operational reliability at high temperatures for sensing and power applications.

08 HYDROGEN↗
DOE OSTI2024

Investigating the Effects of Individual Neutron-Induced Defects in Bipolar Junction Transistors

Here, this study investigates neutron-induced displacement damage in Bipolar Junction Transistors (BJTs) using TCAD models informed by Deep-Level-Transient-Spectroscopy (DLTS) data. These models are calibrated and validated against experimental measurements performed at various neutron fluences. Both npn and pnp transistor configurations are studied to analyze the effects of individual traps on carrier recombination and base leakage currents. In npn transistors, deep traps (0.42 eV from the conduction band) dominate at low voltages, while shallow traps (0.17 eV from the conduction band) become prominent at higher voltages. Conversely, pnp transistors have base leakage current predominantly due to deep-level traps. The study observes a notable trend in trap density versus fluence, characterized by a linear relationship on a log-log scale. These insights into defect evolution under radiation conditions are crucial for optimizing semiconductor device reliability and performance in radiation-prone environments.

42 ENGINEERING↗
DOE OSTI2026

Silicon pinhole strip defects and their impact on ATLAS Inner Tracker HV current measurement

In preparation for the High-Luminsity LHC (HL-LHC) [1], the ATLAS detector will undergo major detector upgrades, including the replacement of the current Inner Detector with the new all-silicon Inner Tracker (ITk) [2]. The ITk consists of a pixel detector close to the beamline surrounded by a large-area strip detector. During detector production, the electrical properties of silicon sensors and readout electronics must be characterized through a series of quality control (QC) and quality assurance tests. These tests ensure any defect is captured at the earliest possible stage. One such defect, callled a pinhole, occurs when the strip implant and the metal readout electrode are shorted through the intermediary dielectric layer. Notably, the introduction of pinholes during module assembly and pinhole effects on completed modules, especially on leakage current measurement circuitry, have never been studied. In this paper, we investigate the effect of such connections on the sensor leakage current measurements of completed modules and introduce new ways to locate pinholed strips. Here, with minor modifications to testing procedures, such defects are shown not to impede module testing or performance.

FOS: Physical sciences↗
DOE OSTI2024

Comprehensive evaluation of commercially scalable atomic-layer-deposited alumina coating impact on full cell battery performance across varied test conditions

Atomic Layer Deposition (ALD) has emerged as a strategic enhancement method for lithium-ion battery (LIB) materials offering potential benefits and durability benefits for industrial battery production. However, the translation from laboratory achievements to commercial-scale applications has been limited. Here, this study aims to bridge this gap by comprehensively evaluating the effects of commercially scalable Al 2 O 3 ALD coatings using full pouch cell performance as a means to assess the ALD impact. We utilized large-scale slot-die coating techniques to ensure consistent electrode quality and tested four configurations of pouch cells to analyze the individual effects of ALD coating on anode and cathode electroactive materials. Our extensive testing matrix included long-term cycling, fast discharge, fast charge, leakage current, and high voltage tests. While at lower C-rates (<~1C), the influence of Al 2 O 3 coatings on cell performance is not significant. Fast charging conditions reveal that the anode ALD coating significantly enhances performance via a passivating effect, while on the cathode, it is detrimental, potentially due to increased resistance of the thin interfacial layer formed during the ALD processing. Leakage current and high-voltage tests show that the application of ALD coatings on either anode or cathode effectively minimizes side reactions at the electrode-electrolyte interface. Additionally, ALD coatings significantly mitigate concentrated and localized lithium plating on the anodes. These insights provide a valuable understanding of the potential of ALD technologies in LIB manufacturing to tailor cell performance, paving the way for safer, more efficient, and cost-effective battery solutions.

25 ENERGY STORAGE↗
DOE OSTI2022

Thermal stability of antiferroelectric-like Al:HfO 2 thin films with TiN or Pt electrodes

HfO 2 -based antiferroelectric-like thin films are increasingly being considered for commercial devices. However, even with initial promise, the temperature sensitivity of electrical properties such as loss tangent and leakage current remains unreported. 50 nm thick, 4 at. % Al-doped HfO 2 thin films were synthesized via atomic layer deposition with both top and bottom electrodes being TiN or Pt. A study of their capacitance vs temperature showed that the Pt/Al:HfO 2 /Pt had a relative dielectric permittivity of 23.30 ± 0.06 at room temperature with a temperature coefficient of capacitance (TCC) of 78 ± 86 ppm/°C, while the TiN/Al:HfO 2 /TiN had a relative dielectric permittivity of 32.28 ± 0.14 at room temperature with a TCC of 322 ± 41 ppm/°C. The capacitance of both devices varied less than 6% over 1 to 1000 kHz from –125 to 125 °C. Both capacitors maintained loss tangents under 0.03 and leakage current densities of 10 –9 –10 –7 A/cm 2 between –125 and 125 °C. The TiN/Al:HfO 2 /TiN capacitor maintained an energy storage density (ESD) of 18.17 ± 0.79 J/cm 3 at an efficiency of 51.79% ± 2.75% over the –125 to 125 °C range. The Pt/Al:HfO 2 /Pt capacitor also maintained a stable ESD of 9.83 ± 0.26 J/cm 3 with an efficiency of 62.87% ± 3.00% over the same temperature range. Finally, such low losses in both capacitors along with their thermal stability make antiferroelectric-like, Al-doped HfO 2 thin films a promising material for temperature-stable microelectronics.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Evaluation of HPK n + - p planar pixel sensors for the CMS Phase-2 upgrade

To cope with the challenging environment of the planned high luminosity upgrade of the Large Hadron Collider (HL-LHC), scheduled to start operation in 2029, CMS will replace its entire tracking system. The requirements for the tracker are largely determined by the long operation time of 10 years with an instantaneous peak luminosity of up to 7.5 × 10 34 cm –2 s –1 in the ultimate performance scenario. Depending on the radial distance from the interaction point, the silicon sensors will receive a particle fluence corresponding to a non-ionizing energy loss of up to $\Phi_{\text {eq}}$ = 3.5 × 10 16 cm –2 . Here this paper focuses on planar pixel sensor design and qualification up to a fluence of $\Phi_{\text {eq}}$ = 1.4 × 10 16 cm –2 . For the development of appropriate planar pixel sensors an R&D program was initiated, which includes $n^+ -p$ sensors on 150 mm (6”) wafers with an active thickness of 150 μm with pixel sizes of 100 × 25 μm 2 and 50 × 50 μm 2 manufactured by Hamamatsu. Single chip modules with ROC4Sens and RD53A readout chips were made. Irradiation with protons and neutrons, as well was an extensive test beam campaign at DESY were carried out. This paper presents the investigation of various assemblies mainly with ROC4Sens readout chips. It demonstrates that multiple designs fulfill the requirements in terms of breakdown voltage, leakage current and efficiency. The single point resolution for 50 × 50 μm 2 pixels is measured as 4.0 μm for non-irradiated samples, and 6.3 μm after irradiation to $\Phi_{\text {eq}}$ = 7.2 × 10 15 cm –2 .

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗