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At least 37 records · Page 2

Parallel Processing with Digital Signal Processing Hardware and Software

The assembling and testing of a parallel processing system is described which will allow a user to move a Digital Signal Processing (DSP) application from the design stage to the execution/analysis stage through the use of several software tools and hardware devices. The system will be used to demonstrate the feasibility of the Algorithm To Architecture Mapping Model (ATAMM) dataflow paradigm for static multiprocessor solutions of DSP applications. The individual components comprising the system are described followed by the installation procedure, research topics, and initial program development.

Swenson, Cory V.↗

Hardware And Software For Development Of Robot Arms

System of modular, reusable hardware and software assembled for use in developing remotely controlled robotic arms. Includes (1) central computer and peripheral equipment at control and monitoring station and (2) remote mechanical platform that supports robotic arm. Central computer controls motor drives of robotic arm, but optically, platform holds on-board computer for autonomous operation. Consists mostly of commercial hardware and software. Simulated results of commands viewed in three dimensions.

Usikov, Daniel↗

PNNL OS3300 Alpha/Beta Monitoring System Software and Hardware Operations Manual (Rev.2)

The Pacific Northwest National Laboratory (PNNL) OS3300 Alpha/Beta Monitoring System Software and Hardware Operations Manual describes how to operate the software and hardware on a personal computer in conjunction with the Berthold Technologies LB150D continuous air monitor. Included are operational details for the software functions and information about how to read and use the dropdown menus and how to understand readings and calculations.

54 ENVIRONMENTAL SCIENCES↗

Digital echocardiography 2002: now is the time

The ability to acquire echocardiographic images digitally, store and transfer these data using the DICOM standard, and routinely analyze examinations exists today and allows the implementation of a digital echocardiography laboratory. The purpose of this review article is to outline the critical components of a digital echocardiography laboratory, discuss general strategies for implementation, and put forth some of the pitfalls that we have encountered in our own implementation. The major components of the digital laboratory include (1) digital echocardiography machines with network output, (2) a switched high-speed network, (3) a high throughput server with abundant local storage, (4) a reliable low-cost archive, (5) software to manage information, and (6) support mechanisms for software and hardware. Implementation strategies can vary from a complete vendor solution providing all components (hardware, software, support), to a strategy similar to our own where standard computer and networking hardware are used with specialized software for management of image and measurement information.

Review↗

PNNL OS3700 Tritium Monitoring System Software and Hardware Operations Manual (Rev.2)

The Pacific Northwest National Laboratory (PNNL) OS3700 Tritium Monitoring System Software and Hardware Operations Manual describes how to install and operate the software and hardware on a personal computer operating in conjunction with the Berthold Technologies LB110 flow-through proportional counter detector system. Included are operational details for the software functions, how to read and use the dropdown menus, how to understand readings and calculations, and how to access the database tables.

54 ENVIRONMENTAL SCIENCES↗

Hardware and software reliability estimation using simulations

The simulation technique is used to explore the validation of both hardware and software. It was concluded that simulation is a viable means for validating both hardware and software and associating a reliability number with each. This is useful in determining the overall probability of system failure of an embedded processor unit, and improving both the code and the hardware where necessary to meet reliability requirements. The methodologies were proved using some simple programs, and simple hardware models.

Swern, Frederic L.↗

Distributed execution of recovery blocks - An approach for uniform treatment of hardware and software faults in real-time applications

The concept of distributed execution of recovery blocks is examined as an approach for uniform treatment of hardware and software faults. A useful characteristic of the approach is the relatively small time cost it requires. The approach is thus suitable for incorporation into real-time computer systems. A specific formulation of the approach that is aimed at minimizing the recovery time is presented, called the distributed recovery block (DRB) scheme. The DRB scheme is capable of effecting forward recovery while handling both hardware and software faults in a uniform manner. An approach to incorporating the capability for multiprocessing scheme is also discussed. Two experiments aimed at testing the execution efficiency of the scheme in real-time applications have been conducted on two different multimicrocomputer networks. The results clearly indicate the feasibility of achieving tolerance of hardware and software faults in a broad range of real-time computer systems by use of the schemes for distributed execution of recovery blocks.

Kim, K. H.↗

Hardware-assisted software clock synchronization for homogeneous distributed systems

A clock synchronization scheme that strikes a balance between hardware and software solutions is proposed. The proposed is a software algorithm that uses minimal additional hardware to achieve reasonably tight synchronization. Unlike other software solutions, the guaranteed worst-case skews can be made insensitive to the maximum variation of message transit delay in the system. The scheme is particularly suitable for large partially connected distributed systems with topologies that support simple point-to-point broadcast algorithms. Examples of such topologies include the hypercube and the mesh interconnection structures.

Ramanathan, P.↗

Hierarchical Simulation to Assess Hardware and Software Dependability

This thesis presents a method for conducting hierarchical simulations to assess system hardware and software dependability. The method is intended to model embedded microprocessor systems. A key contribution of the thesis is the idea of using fault dictionaries to propagate fault effects upward from the level of abstraction where a fault model is assumed to the system level where the ultimate impact of the fault is observed. A second important contribution is the analysis of the software behavior under faults as well as the hardware behavior. The simulation method is demonstrated and validated in four case studies analyzing Myrinet, a commercial, high-speed networking system. One key result from the case studies shows that the simulation method predicts the same fault impact 87.5% of the time as is obtained by similar fault injections into a real Myrinet system. Reasons for the remaining discrepancy are examined in the thesis. A second key result shows the reduction in the number of simulations needed due to the fault dictionary method. In one case study, 500 faults were injected at the chip level, but only 255 propagated to the system level. Of these 255 faults, 110 shared identical fault dictionary entries at the system level and so did not need to be resimulated. The necessary number of system-level simulations was therefore reduced from 500 to 145. Finally, the case studies show how the simulation method can be used to improve the dependability of the target system. The simulation analysis was used to add recovery to the target software for the most common fault propagation mechanisms that would cause the software to hang. After the modification, the number of hangs was reduced by 60% for fault injections into the real system.

Ries, Gregory Lawrence↗

Packaging HEP Heterogeneous Mini-apps for Portable Benchmarking and Facility Evaluation on Modern HPCs

High Energy Physics (HEP) experiments are making increasing use of GPUs and GPU dominated High Performance Computer facilities. Both the software and hardware of these systems are rapidly evolving, creating challenges for experiments to make informed decisions as to where they wish to devote resources. In its first phase, the High Energy Physics Center for Computational Excellence (HEP-CCE) produced portable versions of a number of heterogeneous HEP mini-apps, such as p2r, FastCaloSim, Patatrack and the WireCell Toolkit, that exercise a broad range of GPU characteristics, enabling cross platform and facility benchmarking and evaluation. However, these miniapps still require a significant amount of manual intervention to deploy on a new facility. We present our work in developing turn-key deployments of these mini-apps, where by means of containerization and automated configuration and build techniques such as Spack, we are able to quickly test new hardware, software, environments and entire facilities with minimal user intervention, and then track performance metrics over time.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

Packaging HEP Heterogeneous Mini-apps for Portable Benchmarking and Facility Evaluation on Modern HPCs

High Energy Physics (HEP) experiments are making increasing use of GPUs and GPU dominated High Performance Computer facilities. Both the software and hardware of these systems are rapidly evolving, creating challenges for experiments to make informed decisions as to where they wish to devote resources. In its first phase, the High Energy Physics Center for Computational Excellence (HEP-CCE) produced portable versions of a number of heterogeneous HEP mini-apps, such as \ptor, FastCaloSim, Patatrack and the WireCell Toolkit, that exercise a broad range of GPU characteristics, enabling cross platform and facility benchmarking and evaluation. However, these mini-apps still require a significant amount of manual intervention to deploy on a new facility. We present our work in developing turn-key deployments of these mini-apps, where by means of containerization and automated configuration and build techniques such as Spack, we are able to quickly test new hardware, software, environments and entire facilities with minimal user intervention, and then track performance metrics over time.

Atif, Mohammad [Brookhaven] (ORCID:000000026889770↗

A new systems engineering approach to streamlined science and mission operations for the Far Ultraviolet Spectroscopic Explorer (FUSE)

The Mission Operations and Data Systems Directorate (MO&DSD, Code 500), the Space Sciences Directorate (Code 600), and the Flight Projects Directorate (Code 400) have developed a new approach to combine the science and mission operations for the FUSE mission. FUSE, the last of the Delta-class Explorer missions, will obtain high resolution far ultraviolet spectra (910 - 1220 A) of stellar and extragalactic sources to study the evolution of galaxies and conditions in the early universe. FUSE will be launched in 2000 into a 24-hour highly eccentric orbit. Science operations will be conducted in real time for 16-18 hours per day, in a manner similar to the operations performed today for the International Ultraviolet Explorer. In a radical departure from previous missions, the operations concept combines spacecraft and science operations and data processing functions in a single facility to be housed in the Laboratory for Astronomy and Solar Physics (Code 680). A small missions operations team will provide the spacecraft control, telescope operations and data handling functions in a facility designated as the Science and Mission Operations Center (SMOC). This approach will utilize the Transportable Payload Operations Control Center (TPOCC) architecture for both spacecraft and instrument commanding. Other concepts of integrated operations being developed by the Code 500 Renaissance Project will also be employed for the FUSE SMOC. The primary objective of this approach is to reduce development and mission operations costs. The operations concept, integration of mission and science operations, and extensive use of existing hardware and software tools will decrease both development and operations costs extensively. This paper describes the FUSE operations concept, discusses the systems engineering approach used for its development, and the software, hardware and management tools that will make its implementation feasible.

Butler, Madeline J.↗

System for Centering a Turbofan in a Nacelle During Tests

A feedback position-control system has been developed for maintaining the concentricity of a turbofan with respect to a nacelle during acoustic and flow tests in a wind tunnel. The system is needed for the following reasons: Thermal and thrust loads can displace the fan relative to the nacelle; In the particular test apparatus (see Figure 1), denoted as a rotor-only nacelle (RAN), the struts, vanes, and other stator components of a turbofan engine that ordinarily maintain the required concentricity in the face of thermal and thrust loads are not present; and The struts and stator components are not present because it is necessary to provide a flow path that is acoustically clean in the sense that the measured noise can be attributed to the fan alone. The system is depicted schematically in Figure 2. The nacelle is supported by two struts attached to a two-axis traverse table located outside the wind-tunnel wall. Two servomotors acting through 100:1 gearboxes drive the table along the Y and Z axes, which are perpendicular to the axis of rotation. The Y and Z components of the deviation from concentricity are measured by four laser displacement sensors mounted on the nacelle and aimed at reflective targets on the center body, which is part of the fan assembly. The outputs of the laser displacement sensors are digitized and processed through a personal computer programmed with control software. The control output of the computer commands the servomotors to move the table as needed to restore concentricity. Numerous software and hardware travel limits and alarms are provided to maximize safety. A highly ablative rub strip in the nacelle minimizes the probability of damage in the event that a deviation from concentricity exceeds the radial clearance [<0.004 in. (<0.1 mm)] between the inner surface of the nacelle and the tips of the fan blades. To be able to prevent an excursion in excess of the tip clearance, the system must be accurate enough to control X and Y displacements to within 0.001 in. (.0.025 mm). One characteristic essential to such accuracy is sufficient rigidity in the mechanical components of the system to prevent excitation of vibrations in the strut/ nacelle subsystem. The need for such a high degree of accuracy prompted a comprehensive analysis of sources of measurement and control errors, followed by rigorous design efforts to minimize these errors. As a result, the design of the system incorporates numerous improvements in hardware, software, and operational procedures.

Cunningham, Cameron C.↗

Configurable Hardware And Software For Multiple Related Uses

Control Monitor Unit (CMU) is system of configurable hardware and software undergoing development for use in controlling and monitoring complex systems of equipment. Provides comprehensive array of capabilities for such functions as processing equipment-test data for calibration and diagnosis, controlling operation of equipment in real time, simulating operation of equipment, and processing large streams of scientific-measurement data. Automates many of ground operations involved in preparing and testing spacecraft prior to launch. Also useful in variety of similar applications; for example, testing aircraft, ships, power plants, and automated production lines.

Uhrlaub, David R.↗

Integrated Hardware and Software for No-Loss Computing

When an algorithm is distributed across multiple threads executing on many distinct processors, a loss of one of those threads or processors can potentially result in the total loss of all the incremental results up to that point. When implementation is massively hardware distributed, then the probability of a hardware failure during the course of a long execution is potentially high. Traditionally, this problem has been addressed by establishing checkpoints where the current state of some or part of the execution is saved. Then in the event of a failure, this state information can be used to recompute that point in the execution and resume the computation from that point. A serious problem arises when one distributes a problem across multiple threads and physical processors is that one increases the likelihood of the algorithm failing due to no fault of the scientist but as a result of hardware faults coupled with operating system problems. With good reason, scientists expect their computing tools to serve them and not the other way around. What is novel here is a unique combination of hardware and software that reformulates an application into monolithic structure that can be monitored in real-time and dynamically reconfigured in the event of a failure. This unique reformulation of hardware and software will provide advanced aeronautical technologies to meet the challenges of next-generation systems in aviation, for civilian and scientific purposes, in our atmosphere and in atmospheres of other worlds. In particular, with respect to NASA s manned flight to Mars, this technology addresses the critical requirements for improving safety and increasing reliability of manned spacecraft.

James, Mark↗

Hardware and software fault tolerance - A unified architectural approach

The loss of hardware fault tolerance which often arises when design diversity is used to improve the fault tolerance of computer software is considered analytically, and a unified design approach is proposed to avoid the problem. The fundamental theory of fault-tolerant (FT) architectures is reviewed; the current status of design-diversity software development is surveyed; and the FT-processor/attached-processor (FTP/AP) architecture developed by Lala et al. (1986) is described in detail and illustrated with diagrams. FTP/AP is shown to permit efficient implementation of N-version FT software while still tolerating random hardware failures with very high coverage; the reliability is found to be significantly higher than that of conventional majority-vote N-version software.

Lala, Jaynarayan H.↗

Study of a unified hardware and software fault-tolerant architecture

A unified architectural concept, called the Fault Tolerant Processor Attached Processor (FTP-AP), that can tolerate hardware as well as software faults is proposed for applications requiring ultrareliable computation capability. An emulation of the FTP-AP architecture, consisting of a breadboard Motorola 68010-based quadruply redundant Fault Tolerant Processor, four VAX 750s as attached processors, and four versions of a transport aircraft yaw damper control law, is used as a testbed in the AIRLAB to examine a number of critical issues. Solutions of several basic problems associated with N-Version software are proposed and implemented on the testbed. This includes a confidence voter to resolve coincident errors in N-Version software. A reliability model of N-Version software that is based upon the recent understanding of software failure mechanisms is also developed. The basic FTP-AP architectural concept appears suitable for hosting N-Version application software while at the same time tolerating hardware failures. Architectural enhancements for greater efficiency, software reliability modeling, and N-Version issues that merit further research are identified.

Lala, Jaynarayan↗