Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “gating”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1975

Investigation of field induced trapping on floating gates

The development of a technology for building electrically alterable read only memories (EAROMs) or reprogrammable read only memories (RPROMs) using a single level metal gate p channel MOS process with all conventional processing steps is outlined. Nonvolatile storage of data is achieved by the use of charged floating gate electrodes. The floating gates are charged by avalanche injection of hot electrodes through gate oxide, and discharged by avalanche injection of hot holes through gate oxide. Three extra diffusion and patterning steps are all that is required to convert a standard p channel MOS process into a nonvolatile memory process. For identification, this nonvolatile memory technology was given the descriptive acronym DIFMOS which stands for Dual Injector, Floating gate MOS.

Gosney, W. M.↗
NASA NTRS1994

Plasma Deposited SiO2 for Planar Self-Aligned Gate Metal-Insulator-Semiconductor Field Effect Transistors on Semi-Insulating InP

Metal-insulator-semiconductor (MIS) field effect transistors were fabricated on InP substrates using a planar self-aligned gate process. A 700-1000 A gate insulator of Si02 doped with phosphorus was deposited by a direct plasma enhanced chemical vapor deposition at 400 mTorr, 275 C, 5 W, and power density of 8.5 MW/sq cm. High frequency capacitance-voltage measurements were taken on MIS capacitors which have been subjected to a 700 C anneal and an interface state density of lxl0(exp 11)/eV/cq cm was found. Current-voltage measurements of the capacitors show a breakdown voltage of 107 V/cm and a insulator resistivity of 10(exp 14) omega cm. Transistors were fabricated on semi-insulating InP using a standard planar self-aligned gate process in which the gate insulator was subjected to an ion implantation activation anneal of 700 C. MIS field effect transistors gave a maximum extrinsic transconductance of 23 mS/mm for a gate length of 3 microns. The drain current drift saturated at 87.5% of the initial current, while reaching to within 1% of the saturated value after only 1x10(exp 3). This is the first reported viable planar InP self-aligned gate transistor process reported to date.

Tabory, Charles N.↗
NASA NTRS2003

The human respiratory gate

Respiratory activity phasically alters membrane potentials of preganglionic vagal and sympathetic motoneurones and continuously modulates their responsiveness to stimulatory inputs. The most obvious manifestation of this 'respiratory gating' is respiratory sinus arrhythmia, the rhythmic fluctuations of electrocardiographic R-R intervals observed in healthy resting humans. Phasic autonomic motoneurone firing, reflecting the throughput of the system, depends importantly on the intensity of stimulatory inputs, such that when levels of stimulation are low (as with high arterial pressure and sympathetic activity, or low arterial pressure and vagal activity), respiratory fluctuations of sympathetic or vagal firing are also low. The respiratory gate has a finite capacity, and high levels of stimulation override the ability of respiration to gate autonomic responsiveness. Autonomic throughput also depends importantly on other factors, including especially, the frequency of breathing, the rate at which the gate opens and closes. Respiratory sinus arrhythmia is small at rapid, and large at slow breathing rates. The strong correlation between systolic pressure and R-R intervals at respiratory frequencies reflects the influence of respiration on these two measures, rather than arterial baroreflex physiology. A wide range of evidence suggests that respiratory activity gates the timing of autonomic motoneurone firing, but does not influence its tonic level. I propose that the most enduring significance of respiratory gating is its use as a precisely controlled experimental tool to tease out and better understand otherwise inaccessible human autonomic neurophysiological mechanisms.

Review↗
NASA NTRS2005

Modeling of a Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate

Considerable research has been performed by several organizations in the use of the Metal- Ferroelectric-Semiconductor Field-Effect Transistors (MFSFET) in memory circuits. However, research has been limited in expanding the use of the MFSFET to other electronic circuits. This research project investigates the modeling of a NAND gate constructed from MFSFETs. The NAND gate is one of the fundamental building blocks of digital electronic circuits. The first step in forming a NAND gate is to develop an inverter circuit. The inverter circuit was modeled similar to a standard CMOS inverter. A n-channel MFSFET with positive polarization was used for the n-channel transistor, and a n-channel MFSFET with negative polarization was used for the p-channel transistor. The MFSFETs were simulated by using a previously developed current model which utilized a partitioned ferroelectric layer. The inverter voltage transfer curve was obtained over a standard input of zero to five volts. Then a 2-input NAND gate was modeled similar to the inverter circuit. Voltage transfer curves were obtained for the NAND gate for various configurations of input voltages. The resultant data shows that it is feasible to construct a NAND gate with MFSFET transistors.

Phillips, Thomas A.↗
NASA NTRS2006

Metal-Ferroelectric-Semiconductor Field-Effect Transistor NAND Gate Switching Time Analysis

Previous research investigated the modeling of a N Wga te constructed of Metal-Ferroelectric- Semiconductor Field-Effect Transistors (MFSFETs) to obtain voltage transfer curves. The NAND gate was modeled using n-channel MFSFETs with positive polarization for the standard CMOS n-channel transistors and n-channel MFSFETs with negative polarization for the standard CMOS p-channel transistors. This paper investigates the MFSFET NAND gate switching time propagation delay, which is one of the other important parameters required to characterize the performance of a logic gate. Initially, the switching time of an inverter circuit was analyzed. The low-to-high and high-to-low propagation time delays were calculated. During the low-to-high transition, the negatively polarized transistor pulls up the output voltage, and during the high-to-low transition, the positively polarized transistor pulls down the output voltage. The MFSFETs were simulated by using a previously developed model which utilized a partitioned ferroelectric layer. Then the switching time of a 2-input NAND gate was analyzed similarly to the inverter gate. Extension of this technique to more complicated logic gates using MFSFETs will be studied.

Phillips, Thomas A.↗
NASA NTRS2008

Radiation-Insensitive Inverse Majority Gates

To help satisfy a need for high-density logic circuits insensitive to radiation, it has been proposed to realize inverse majority gates as microscopic vacuum electronic devices. In comparison with solid-state electronic devices ordinarily used in logic circuits, vacuum electronic devices are inherently much less adversely affected by radiation and extreme temperatures. The proposed development would involve state-of-the-art micromachining and recent advances in the fabrication of carbon-nanotube-based field emitters. A representative three-input inverse majority gate would be a monolithic, integrated structure that would include three gate electrodes, six bundles of carbon nanotubes (serving as electron emitters) at suitable positions between the gate electrodes, and an overhanging anode. The bundles of carbon nanotubes would be grown on degenerately doped silicon substrates that would be parts of the monolithic structure. The gate electrodes would be fabricated as parts of the monolithic structure by means of a double-silicon-on-insulator process developed at NASA's Jet Propulsion Laboratory. The tops of the bundles of carbon nanotubes would lie below the plane of the tops of the gate electrodes. The particular choice of shapes, dimensions, and relative positions of the electrodes and bundles of carbon nanotubes would provide for both field emission of electrons from the bundles of carbon nanotubes and control of the electron current to obtain the inverse majority function, which is described in the paper.

Manohara, Harish↗
NASA NTRS2011

Frame-Transfer Gating Raman Spectroscopy for Time-Resolved Multiscalar Combustion Diagnostics

Accurate experimental measurement of spatially and temporally resolved variations in chemical composition (species concentrations) and temperature in turbulent flames is vital for characterizing the complex phenomena occurring in most practical combustion systems. These diagnostic measurements are called multiscalar because they are capable of acquiring multiple scalar quantities simultaneously. Multiscalar diagnostics also play a critical role in the area of computational code validation. In order to improve the design of combustion devices, computational codes for modeling turbulent combustion are often used to speed up and optimize the development process. The experimental validation of these codes is a critical step in accepting their predictions for engine performance in the absence of cost-prohibitive testing. One of the most critical aspects of setting up a time-resolved stimulated Raman scattering (SRS) diagnostic system is the temporal optical gating scheme. A short optical gate is necessary in order for weak SRS signals to be detected with a good signal- to-noise ratio (SNR) in the presence of strong background optical emissions. This time-synchronized optical gating is a classical problem even to other spectroscopic techniques such as laser-induced fluorescence (LIF) or laser-induced breakdown spectroscopy (LIBS). Traditionally, experimenters have had basically two options for gating: (1) an electronic means of gating using an image intensifier before the charge-coupled-device (CCD), or (2) a mechanical optical shutter (a rotary chopper/mechanical shutter combination). A new diagnostic technology has been developed at the NASA Glenn Research Center that utilizes a frame-transfer CCD sensor, in conjunction with a pulsed laser and multiplex optical fiber collection, to realize time-resolved Raman spectroscopy of turbulent flames that is free from optical background noise (interference). The technology permits not only shorter temporal optical gating (down to <1 s, in principle), but also higher optical throughput, thus resulting in a substantial increase in measurement SNR.

Nguyen, Quang-Viet↗
NASA NTRS2016

An Integrated Gate Turnaround Management Concept Leveraging Big Data/Analytics for NAS Performance Improvements

The Integrated Gate Turnaround Management (IGTM) concept was developed to improve the gate turnaround performance at the airport by leveraging relevant historical data to support optimization of airport gate operations, which include: taxi to the gate, gate services, push back, taxi to the runway, and takeoff, based on available resources, constraints, and uncertainties. By analyzing events of gate operations, primary performance dependent attributes of these events were identified for the historical data analysis such that performance models can be developed based on uncertainties to support descriptive, predictive, and prescriptive functions. A system architecture was developed to examine system requirements in support of such a concept. An IGTM prototype was developed to demonstrate the concept using a distributed network and collaborative decision tools for stakeholders to meet on time pushback performance under uncertainties.

Big Data and Net-enabled ATM↗
NASA NTRS2017

System and Method for Scan Range Gating

A system for scanning light to define a range gated signal includes a pulsed coherent light source that directs light into the atmosphere, a light gathering instrument that receives the light modified by atmospheric backscatter and transfers the light onto an image plane, a scanner that scans collimated light from the image plane to form a range gated signal from the light modified by atmospheric backscatter, a control circuit that coordinates timing of a scan rate of the scanner and a pulse rate of the pulsed coherent light source so that the range gated signal is formed according to a desired range gate, an optical device onto which an image of the range gated signal is scanned, and an interferometer to which the image of the range gated signal is directed by the optical device. The interferometer is configured to modify the image according to a desired analysis.

Zuk, David M.↗
NASA NTRS2017

Modeling and Simulating Airport Surface Operations with Gate Conflicts

The Surface Operations Simulator and Scheduler (SOSS) is a fast-time simulation platform used to develop and test future surface scheduling concepts such as NASAs Air Traffic Demonstration 2 of time-based surface metering at Charlotte Douglas International Airport (CLT). Challenges associated with CLT surface operations have driven much of SOSS development. Recently, SOSS functionality for modeling hardstand operations was developed to address gate conflicts, which occur when an arrival and departure wish to occupy the same gate at the same time. Because surface metering concepts such as ATD2 have the potential to increase gates conflicts as departure are held at their gates, it is important to study the interaction between surface metering and gate conflict management. Several approaches to managing gate conflicts with and without the use of hardstands were simulated and their effects on surface operations and scheduler performance compared.

Zelinski, Shannon↗
NASA NTRS2017

Modeling and Simulating Airport Surface Operations with Gate Conflicts

The Surface Operations Simulator and Scheduler (SOSS) is a fast-time simulation platform used to develop and test future surface scheduling concepts such as NASA's Air Traffic Demonstration 2 of time-based surface metering at Charlotte Douglass International Airport (CLT). Challenges associated with CLT surface operations have driven much of SOSS development. Recently, SOSS functionality for modeling harsdstand operations was developed to address gate conflicts, which occur when an arrival and departure wish to occupy the same gate at the same time. Because surface metering concepts such as ATD2 have the potential to increase gates conflicts as departures are held at their gates, it is important to study the interaction between surface metering and gate conflict management. Several approaches to managing gate conflicts with and without the use of hardstands were simulated and their effects on surface operations and scheduler performance compared.

Zelinski, Shannon↗
NASA NTRS2021

A Nanoscale Vacuum Field Emission Gated Diode with an Umbrella Cathode

A nanoscale field emission vacuum channel gated diode structure is proposed and a tungsten cathode with an umbrella-like geometry and sharp vertical edge is fabricated. The edge of the suspended cathode becomes the field emission surface. Unlike in the traditional transistor with the gate typically located between the source and the drain, the bottom silicon plate becomes the gate here and the anode terminal is located between the umbrella cathode and the gate. The fabricated devices show excellent diode characteristics and the gated diode structure is attractive for extremely low gate leakage.

Vacuum field emission diode↗
NASA NTRS2001

The gating mechanism of the large mechanosensitive channel MscL

The mechanosensitive channel of large conductance, MscL, is a ubiquitous membrane-embedded valve involved in turgor regulation in bacteria. The crystal structure of MscL from Mycobacterium tuberculosis provides a starting point for analysing molecular mechanisms of tension-dependent channel gating. Here we develop structural models in which a cytoplasmic gate is formed by a bundle of five amino-terminal helices (S1), previously unresolved in the crystal structure. When membrane tension is applied, the transmembrane barrel expands and pulls the gate apart through the S1-M1 linker. We tested these models by substituting cysteines for residues predicted to be near each other only in either the closed or open conformation. Our results demonstrate that S1 segments form the bundle when the channel is closed, and crosslinking between S1 segments prevents opening. S1 segments interact with M2 when the channel is open, and crosslinking of S1 to M2 impedes channel closing. Gating is affected by the length of the S1-M1 linker in a manner consistent with the model, revealing critical spatial relationships between the domains that transmit force from the lipid bilayer to the channel gate.

Non-NASA Center↗
NASA NTRS1984

GaAs dual-gate FET for operation up to K-band

A high-frequency equivalent-circuit model of a GaAs dual-gate FET and analytical expressions for the input/output impedances, transconductance, unilateral gain, and stability factor are presented. It is found that the gain of a dual-gate FET is higher than of a single-gate FET at low frequency but decreases faster as frequency increases because of the capacitive shunting effect of the second gate. A dual-gate power FET suitable for variable-gain-amplifier applications up to K-band has been developed. At 10 GHz, a 1.2-mm-gatewidth device has achieved an output power of 1.1 W with 10.5-dB gain and 31-percent power-added efficiency. At 20 GHz, the same device delivered an output power of 340 mW with 5.3-dB gain. At K-band, a dynamic-gain control range of up to 45 dB was obtained with an insertion phase change of no more than + or 2 degrees for the first 10 dB of gain control.

Kim, B.↗
NASA NTRS1993

Characteristics of 0.8- and 0.2-microns gate length In(x)Ga(1-x) As/In(0.52)Al(0.48)As/InP (0.53 less than or equal to x less than or equal to 0.70) modulation-doped field-effect transistors at cryogenic temperatures

The performance characteristics of InP-based In(x)Ga(1-x)As/In(0.52)Al(0.48)As (0.53 is less than or equal to x is less than or equal to 0.70) pseudomorphic modulation-doped field-effect transistors (MODFET's) as a function of strain in the channel, gate, length, and temperature were investigated analytically and experimentally. The strain in the channel was varied by varying the In composition x. The temperature was varied in the range of 40-300 K and the devices have gate lengths L(sub g) of 0.8 and 0.2 microns. Analysis of the device was done using a one-dimensional self consistent solution of the Poisson and Schroedinger equations in the channel, a two-dimensional Poisson solver to obtain the channel electric field, and a Monte Carlo simulation to estimate the carrier transit times in the channel. An increase in the value of the cutoff frequency is predicted for an increase in In composition, a decrease in temperature, and a decrease in gate length. The improvements seen with decreasing temperature, decreasing gate length, and increased In composition were smaller than those predicted by analysis. The experimental results on pseudomorphic InGaAs/InAlAs MODFET's showed that there is a 15-30 percent improvement in cutoff frequency in both the 0.8- and 0.2-micron gate length devices when the temperature is lowered from 300 to 40 K.

Lai, Richard↗
NASA NTRS2003

Design of a Ferroelectric Programmable Logic Gate Array

A programmable logic gate array has been designed utilizing ferroelectric field effect transistors. The design has only a small number of gates, but this could be scaled up to a more useful size. Using FFET's in a logic array gives several advantages. First, it allows real-time programmability to the array to give high speed reconfiguration. It also allows the array to be configured nearly an unlimited number of times, unlike a FLASH FPGA. Finally, the Ferroelectric Programmable Logic Gate Array (FPLGA) can be implemented using a smaller number of transistors because of the inherent logic characteristics of an FFET. The device was only designed and modeled using Spice models of the circuit, including the FFET. The actual device was not produced. The design consists of a small array of NAND and NOR logic gates. Other gates could easily be produced. They are linked by FFET's that control the logic flow. Timing and logic tables have been produced showing the array can produce a variety of logic combinations at a real time usable speed. This device could be a prototype for a device that could be put into imbedded systems that need the high speed of hardware implementation of logic and the complexity to need to change the logic algorithm. Because of the non-volatile nature of the FFET, it would also be useful in situations that needed to program a logic array once and use it repeatedly after the power has been shut off.

MacLeod, Todd C.↗
NASA NTRS2006

Dual Input AND Gate Fabricated From a Single Channel Poly (3-Hexylthiophene) Thin Film Field Effect Transistor

A regio-regular poly (3-hexylthiophene) (RRP3HT) thin film transistor having a split-gate architecture has been fabricated on a doped silicon/silicon nitride substrate and characterized. This device demonstrates AND logic functionality. The device functionality was controlled by applying either 0 or -10 V to each of the gate electrodes. When -10 V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The p-type carrier charge mobility was about 5x10(exp -4) per square centimeter per V-sec. The low mobility is attributed to the sharp contours of the RRP3HT film due to substrate non-planarity. A significant advantage of this architecture is that AND logic devices with multiple inputs can be fabricated using a single RRP3HT channel with multiple gates.

Pinto, N. J.↗
NASA NTRS2009

Measurement and Analysis of a Ferroelectric Field-Effect Transistor NAND Gate

Previous research investigated expanding the use of Ferroelectric Field-Effect Transistors (FFET) to other electronic devices beyond memory circuits. Ferroelectric based transistors possess unique characteris tics that give them interesting and useful properties in digital logic circuits. The NAND gate was chosen for investigation as it is one of the fundamental building blocks of digital electronic circuits. In t his paper, NAND gate circuits were constructed utilizing individual F FETs. N-channel FFETs with positive polarization were used for the standard CMOS NAND gate n-channel transistors and n-channel FFETs with n egative polarization were used for the standard CMOS NAND gate p-chan nel transistors. The voltage transfer curves were obtained for the NA ND gate. Comparisons were made between the actual device data and the previous modeled data. These results are compared to standard MOS logic circuits. The circuits analyzed are not intended to be fully opera tional circuits that would interface with existing logic circuits, bu t as a research tool to look into the possibility of using ferroelectric transistors in future logic circuits. Possible applications for th ese devices are presented, and their potential benefits and drawbacks are discussed.

Phillips, Thomas A.↗