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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

Coding for reliable satellite communications

This research project was set up to study various kinds of coding techniques for error control in satellite and space communications for NASA Goddard Space Flight Center. During the project period, researchers investigated the following areas: (1) decoding of Reed-Solomon codes in terms of dual basis; (2) concatenated and cascaded error control coding schemes for satellite and space communications; (3) use of hybrid coding schemes (error correction and detection incorporated with retransmission) to improve system reliability and throughput in satellite communications; (4) good codes for simultaneous error correction and error detection, and (5) error control techniques for ring and star networks.

Gaarder, N. T.↗
NASA NTRSDate not supplied

NOR Flash Memory Scrubbing Application for Boot File Preservation of NASA’s Descent and Landing Computer (DLC)

Progress on NASA’s Safe and Precise Landing Integrated Capabilities Evolution (SPLICE) project continues, specifically with this development of the Descent and Landing Computer (DLC). One of the DLC’s primary contributions as a SPLICE technology is its implementation of algorithms and operation of sensors to autonomously guide a spacecraft in performing more precise and safer landings on celestial bodies such as the Moon and Mars [1]. The second iteration of the DLC is known as the Engineering Test Unit (ETU) and one of its desired functionalities is the ability to preserve the fidelity of the system’s boot file through the use of memory scrubbing [2]. The ETU has two primary boards, one for housing a Multi-Processor System on a Chip (MPSoC) and the other for housing a Xilinx Kintex Ultrascale FPGA*. To emulate a memory scrubbing function implemented on the ETU’s FPGA board, the design and testing of a software application was performed on a Xilinx KCU105 FPGA evaluation board. The memory scrubbing application had to meet certain key criteria such as (1) properly utilize with the flash memory’s Serial Peripheral Interface (SPI) to read, write, and erase flash memory properly, (2) be able to detect arbitrarily large or small amounts of bit-errors, (3) be able to correct all detected errors, and (4) perform memory scrubbing indefinitely and autonomously. A prototype implementation was constructed and tested, demonstrating successful detection and correction of bit errors in multiple configurations. In the form of burst errors or singular bit flips, and in amounts of errors ranging from one to fifteen (per 256 Bytes), the application was successful in preserving memory fidelity.

Flash memory↗
DOE OSTI2024

Error field detection and correction studies towards ITER operation

In magnetic fusion devices, error field (EF) sources, spurious magnetic field perturbations, need to be identified and corrected for safe and stable (disruption-free) tokamak operation. Within Work Package Tokamak Exploitation RT04, a series of studies have been carried out to test the portability of the novel non-disruptive method, designed and tested in DIII-D (Paz-Soldan et al 2022 Nucl. Fusion62 126007), and to perform an assessment of model-based EF control strategies towards their applicability in ITER. In this paper, the lessons learned, the physical mechanism behind the magnetic island healing, which relies on enhanced viscous torque that acts against the static electro-magnetic torque, and the main control achievements are reported, together with the first design of the asynchronous EF correction current/density controller for ITER.

70 PLASMA PHYSICS AND FUSION TECHNOLOGY↗
NASA NTRS1991

Self-Testing Static Random-Access Memory

Proposed static random-access memory for computer features improved error-detecting and -correcting capabilities. New self-testing scheme provides for detection and correction of errors at any time during normal operation - even while data being written into memory. Faults in equipment causing errors in output data detected by repeatedly testing every memory cell to determine whether it can still store both "one" and "zero", without destroying data stored in memory.

Chau, Savio↗
NASA NTRS1983

On the probability of undetected error for the maximum distance separable codes

The performance of maximum-distance-separable codes with symbols from GF(1) when they are used for pure error detection or for simultaneous error correction and detection is investigated. These codes are good for symbol error detection. Their probability of undetected error is upper bounded by q to the -r and decreases monotonically as the symbol error probability epsilon decreases from (q-1)/q to 0, where r is the number of parity-check symbols of a code.

Kasami, T.↗
NASA NTRS1984

On the probability of undetected error for the maximum distance separable codes

The performance of maximum-distance-separable codes with symbols from GF(1) when they are used for pure error detection or for simultaneous error correction and detection is investigated. These codes are good for symbol error detection. Their probability of undetected error is upper bounded by q to the -r and decreases monotonically as the symbol error probability epsilon decreases from (q-1)/q to 0, where r is the number of parity-check symbols of a code.

Kasami, T.↗
NASA NTRS1985

A median filter approach for correcting errors in a vector field

Techniques are presented for detecting and correcting errors in a vector field. These methods employ median filters which are frequently used in image processing to enhance edges and remove noise. A detailed example is given for wind field maps produced by a spaceborne scatterometer. The error detection and replacement algorithm was tested with simulation data from the NASA Scatterometer (NSCAT) project.

Schultz, H.↗
NASA NTRS2006

System and method for forward error correction

A system and method are provided for transferring a packet across a data link. The packet may include a stream of data symbols which is delimited by one or more framing symbols. Corruptions of the framing symbol which result in valid data symbols may be mapped to invalid symbols. If it is desired to transfer one of the valid data symbols that has been mapped to an invalid symbol, the data symbol may be replaced with an unused symbol. At the receiving end, these unused symbols are replaced with the corresponding valid data symbols. The data stream of the packet may be encoded with forward error correction information to detect and correct errors in the data stream.

Cole, Robert M.↗
NASA NTRS2007

System and method for transferring data on a data link

A system and method are provided for transferring a packet across a data link. The packet may include a stream of data symbols which is delimited by one or more framing symbols. Corruptions of the framing symbol which result in valid data symbols may be mapped to invalid symbols. If it is desired to transfer one of the valid data symbols that has been mapped to an invalid symbol, the data symbol may be replaced with an unused symbol. At the receiving end, these unused symbols are replaced with the corresponding valid data symbols. The data stream of the packet may be encoded with forward error correction information to detect and correct errors in the data stream.

Cole, Robert M.↗
NASA NTRS1989

Orbital maneuvering vehicle teleoperation and video data compression

The Orbital Maneuvering Vehicle (OMV) and concepts of teleoperation and video data compression as applied to OMV design and operation are described. The OMV provides spacecraft delivery, retrieval, reboost, deboost and viewing services, with ground-control or Space Station operation, through autonomous navigation and pilot controlled maneuvers. Communications systems are comprised of S-band RF command, telemetry, and compressed video data links through the TDRSS and GSTDN networks. The control console video monitors display a monochrome image at an update rate of five frames per second. Depending upon the mode of operation selected by the pilot, the video resolution is either 255 x 244 pixels, or 510 x 244 pixels. Since practically all video image redundancy is removed by the compression process, the video reconstruction is particularly sensitive to data transmission bit errors. Concatenated Reed-Solomon and convolution coding are used with helical data interleaving for error detection and correction, and an error-containment process minimizes the propagation of error effects throughout the video image. Video sub-frame replacement is used, in the case of a non-correctable error or error burst, to minimize the visual impact to the pilot.

Jones, Steve↗
NASA NTRS1988

Burst-Locked Oscillator Avoids Side Lock

Counting circuit corrects errors when side lock occurs. Digital error-detection-and-correction circuit in color-television oscillator circuit provides synchronization when color-burst frequency drifts outside normal tolerance. Digital side-lock-prevention circuit used in television color-burst phase-lock-loop oscillator provides greater tolerance of off-frequency signals than crystal-controlled oscillators.

Dischert, Robert A.↗
DOE OSTI2022

Multi-area parameter error identification for large power systems

Power grid model parameters may contain errors due to various reasons. Detecting and correcting parameter errors typically requires significant computational effort due to the size and complexity of the parameter database. While the normalized Lagrange multiplier (NLM) method can effectively detect, identify and correct parameter errors, its computational burden could rapidly grow with increasing system size. This paper addresses this issue by proposing a multi-area parameter error identification method. Each area has its own outlier detection tool for detecting the incorrect parameters and measurements within the area. On the other hand, due to the reduced redundancy at area boundaries, parameter errors on branches incident to boundary buses may not be detected. Such errors are subsequently detected by a coordination level estimator completing the system-wide parameter detection procedure. In conclusion, performance of the developed method is demonstrated using the IEEE 118-bus and 2000-bus Texas synthetic systems.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1992

Matrix error correction for digital data

A technique for digital data error detection and correction is disclosed which adds alignment and checksum bytes to three sides of a matrix (24) of digital data to be protected. This technique is particularly used for the recording and storage (16,18) of digital data on video tape medium (14). The digital data is treated as a matrix block (24). Checksum and alignment bytes are added (20) to the digital data before tape storage and stripped (22) therefrom after successful alignment checks and data validation. In particular, the first column may be used to provide alignment bytes of a predetermined value for each row. The last column provides row checksum bytes for the data in each row. The last row provides column check sum bytes for each column, excluding the column of alignment bytes. The data location at the intersection of the row of column checksum bytes and the column of row checksum bytes may be used as a checksum byte for either the row or column checksum bytes.

Dotson, Ronald S.↗
DOE OSTI2026

Leveraging Qubit Loss Detection in Fault-Tolerant Quantum Algorithms

Qubit loss errors constitute a dominant source of noise in many quantum hardware systems, particularly in neutral-atom quantum computers. We develop a theoretical framework to effectively detect and correct loss errors in logical algorithms and leverage such loss information in decoding. Considering general quantum error correction codes and logical circuits, we introduce a delayed-erasure decoder for experimentally motivated error models which leverages information from delayed loss detection to accurately correct loss errors, even when the precise moment of the error is unknown. Using this decoder, we identify strategies for detecting and correcting loss errors based on the logical circuit structure. For deep circuits prior to logical measurement, we explore methods to integrate loss detection into syndrome extraction with minimal overhead, identifying optimal strategies depending on the qubit loss fraction in the noise and hardware capabilities. In contrast, we find that many key algorithmic subroutines involve frequent gate teleportation, shortening the circuit depth before logical measurement and naturally replacing qubits with no additional experimental overhead. We simulate this setting using a toy model algorithm for small-angle synthesis and find a significant performance improvement as the loss fraction increases. These results provide a path forward for advancing large-scale fault-tolerant quantum computation in systems with loss error detection.

atoms↗
NASA NTRS1990

Analysis and design of algorithm-based fault-tolerant systems

An important consideration in the design of high performance multiprocessor systems is to ensure the correctness of the results computed in the presence of transient and intermittent failures. Concurrent error detection and correction have been applied to such systems in order to achieve reliability. Algorithm Based Fault Tolerance (ABFT) was suggested as a cost-effective concurrent error detection scheme. The research was motivated by the complexity involved in the analysis and design of ABFT systems. To that end, a matrix-based model was developed and, based on that, algorithms for both the design and analysis of ABFT systems are formulated. These algorithms are less complex than the existing ones. In order to reduce the complexity further, a hierarchical approach is developed for the analysis of large systems.

Nair, V. S. Sukumaran↗
NASA NTRS1981

Erasure decoding in burst-error channels

A proven means of communicating reliably in a burst-error channel is the code interleaving scheme. Code symbols from a number of component codes are interleaved before being sent through the channel. This method effectively distributes the error detection and correction burden among the component codes and makes errors occurring in a codeword from each component code more or less independent. Erasure decoding techniques allow further refinement on the code interleaving concept. Their application leads to improved overall code performance when the symbol depth of the lead code is shallow compared to the average error-burst length of the channel. Theoretical formulations derived for predicting the performance of separate decoding and erasure decoding schemes are valuable in providing reasonably good estimates on redundancy requirements of the component codes.

Leung, K. S.↗