SEARCH · Engineering Papers

Results for “digital logic”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 37 records · Page 2

All sources NASA NTRS DOE OSTI

DOE OSTI2023

A Data-Driven Passive Islanding Detection Scheme

This paper proposes a novel statistical parameters based data driven approach for passive islanding detection. The proposed scheme relies in the voltage data, measured at the point of common coupling, and is comprised of three stages. The Stage-1 quickly detects what is termed as coarse islanding, Stage-2 computes the decaying DC detector (DDCD), and 3) finally, the digital relay logic (DRL) is devised in Stage-3. The proposed scheme is tested as per the IEEE-1547, UL 1741 and IEC-62116 standards. Various tests are investigated on the modified IEEE-13 bus system, modeled in PSCAD/EMTDC, under stringent test scenarios such as power mismatch, induction motor starting effect, capacitor bank switching and various level of loads changes, considered for both single and multiple DG systems. The test results reveal that the proposed scheme can detect islanding in less than 2 cycles, and results in nearly zero non detection zone (NDZ). Also, the scheme can very well be used for single-phase microgrids too as it relies only on the single phase voltage information.

anti-islanding protection↗

DOE OSTI2024

Petahertz electronics

Petahertz, or lightwave, electronics uses tailored optical waveforms to control charge carriers in an electronic circuit at petahertz frequencies. This may enable faster processing than conventional pulsed electronics, which cannot be scaled beyond gigahertz frequencies. In recent years, petahertz-scale currents driven by optical fields have been measured in solid-state systems and nanoscale structures, with several proof-of-principle demonstrations of sub-optical-cycle current generation and optical-field-resolved waveform detection at the sub-femtosecond to few-femtosecond scale. Recent work has taken the first steps towards digital and quantum operation by exploring optical-field-driven logic and memory functionality. Here, in this Review, we discuss the progress towards sub-cycle field-driven current injection, highlighting key theoretical concepts, experimental milestones, and questions remaining as we push towards realizing petahertz electronics for ultrafast optical waveform analysis, digital logic, communications, and quantum computation.

Heide, Christian↗

DOE OSTI2023

A nanocryotron memory and logic family

The development of superconducting electronics based on nanocryotrons has been limited so far to few device circuits, in part due to the lack of standard and robust logic cells. Here, we introduce and experimentally demonstrate designs for a set of nanocryotron-based building blocks that can be configured and combined to implement memory and logic functions. The devices were fabricated by patterning a single superconducting layer of niobium nitride and measured in liquid helium on a wide range of operating points. The tests show 10 - 4 bit error rates with above ± 20 % margins up to 50 MHz and the possibility of operating under the effect of an out-of-plane 36 mT magnetic field, with ± 30 % margins at 10 MHz. Additionally, we designed and measured an equivalent delay-flip-flop made of two memory cells to show the possibility of combining multiple building blocks to make larger circuits. These blocks may constitute a solid foundation for the development of nanocryotron logic circuits and finite-state machines with potential applications in the integrated processing and control of superconducting nanowire single-photon detectors.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2024

The CMOS Pseudo-Thyristor: a zero-static current discriminator circuit

We report a very low power discriminator circuit for pixelized detectors, called the Pseudo-Thyristor is described in this document. It is a positive feedback topology using regular PMOS and NMOS field-effect transistors (FET's) with zero static current. When a small charge is injected into the circuit, it flips rapidly due to the positive feedback and outputs a logic transition for further digitization. Simulation shows that in a 65 nm process, it is possible to achieve a detecting threshold below 5 fC while maintain the average power consumption below 10 micro-Watts when the hit occupancy is <10% for 40 MHz operation.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2024

An Advanced Synchronized Time Digital Grid Twin Testbed for Relay Misoperation Analysis of Electrical Fault Type Detection Algorithms

Distributed energy resources and the number of relays are expected to rise in modern electrical grids; consequently, relay misoperations are also expected to grow. Relays can detect electrical fault types using an internal algorithm and can display the result using light indicators on the front of the relay. However, some relays’ internal algorithms for predicting types of electrical faults could be improved. This study assesses a relay’s external and internal algorithms with an Advanced Synchronized Time Digital Grid Twin (ASTDGT) testbed with paired relays. A misoperation relay analysis focused on measuring the accuracy of using the boundary admittance (the external algorithm) versus the set-default (the internal algorithm) relay method to determine the electrical fault types was performed. In this study, the internal and external relay algorithms were assessed with a synchronized time digital grid twin testbed using a real-time simulator. This testbed evaluated two sets of logic at the same time with the digital grid twin and paired relays in the loop. Different types of electrical faults were simulated, and the relays’ recorded events and electrical fault light indicator states were collected from the human–machine interfaces. This ASTDGT testbed with paired relays successfully evaluated the relay algorithm misoperations. The boundary admittance method had an accuracy of 100% for line-to-line, line-to-ground, and line-to-line ground faults.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2022

Radiation-Hardened GaN HEMT and Cell Design, Modeling, and Fabrication for Nuclear Instrumentation Applications

Recent advances in nuclear power generation technologies show great promise for efficient, safe generation of carbon-free power in the near future. Consequently, many new generation reactor designs are being pursued by government and industry groups, including both fission- and fusion-based technologies. Radiation- and temperature-tolerant sensor technology continues to advance, yet development of the electronics/instrumentation technologies suitable for these environments have fallen behind. Industry has adequately addressed harsh environment electronics needs for low earth orbit satellites, but the much more extreme conditions associated with electronics placed near or in a reactor core remain unaddressed. This project investigates the use of gallium nitride (GaN) circuit technology to address the unique needs for sensor interface electronics and communications in reactor environments. This report provides a summary of the first year’s project activities related to developing and optimizing devices and circuits for this GaN high electronic mobility transistor (HEMT) process. Activities reported include multiple analog and digital circuit designs simulated using custom Verilog-A models generated from measured GaN devices fabricated in the target process. Digital circuit designs included fundamental logic circuits such as an inverter, NAND, NOR, AND and OR gates, as well as a 5-stage ring oscillator. Each design was simulated using an open-source SPICE simulator, and an integrated circuit layout was produced of each design for use in future fabrication. Analog circuit designs focused on the fundamental building blocks to be used to construct sensor interface and communications circuits. These included current mirrors, matched differential pairs, and a Gilbert cell mixer design, each with an associated integrated circuit layout. Layout tools used for these designs included two open-source packages—KLayout and Magic—which were customized for specific use with the OSU GaN process layers. Design rules and preliminary device extraction capabilities were built for the Magic tool to enable device extraction and subsequent netlist generation for SPICE simulation. Finally, future research directions for year two are summarized. When the year-two directions are implemented, the project will be in position to advance the state of the art in electronics for near- or in-reactor sensor interfacing and communications.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2023

A Schottky Tune Meter for the Fermilab Mu2E Delivery Ring

The Mu2E experiment will measure the ratio of the rate of the neutrinoless, coherent conversion of muons into electrons as a measure of Charged Lepton Flavor Violation. As part of the Mu2E experiment, a proton storage ring, called the Delivery Ring, will utilize resonant extraction to slow-spill protons to the experiment. To regulate and optimize the Delivery Ring resonant extraction process, a fast tune measurement scheme will be required. This Mu2E tune meter will measure the average tune and the tune spectrum, in multiple time slices, through the entire resonant extraction cycle of nominally 43 msec. The Mu2E tune meter system utilizes vertical and horizontal 21.4 MHz Schottky detector resonant pickups, taken from the decommissioned Tevatron, high-gain amplifiers and digital down-conversion FPGA logic for its signal processing. This paper will present the design of this Schottky tune meter as well as tune measurements from the Mu2E delivery ring.

43 PARTICLE ACCELERATORS↗

DOE OSTI2025

Introduction: Neuromorphic Materials

The explosive growth in data collection and the need to process it efficiently, as well as the desire to automate increasingly complex tasks in transportation, medical care, manufacturing, security and many other fields have motivated a growing interest in neuromorphic computing. Unlike the binary, transistorbased ON/OFF logic gates and separate logic and memory functionalities employed in digital computing, neuromorphic computing is inspired by animal brains that use interconnected synapses and neurons to perform processing, storage and transmission of information at the same location, while only consuming ~20 W or less of power. Motivated by the brain’s efficiency, adaptability, self-learning and resiliency qualities, neuromorphic computing can be broadly defined as an approach to processing and storing information using hardware and algorithms inspired by models of biological neural systems. Present research in neuromorphic computing encompasses approaches that vary significantly in their degree of neuro-inspiration, from systems that only incorporate features such as asynchronous, event-driven operation or use crossbar arrays of non-volatile memory (NVM) elements to accelerate deep neural networks (DNNs), to designs that embrace the extreme parallelism, sparsity, reconfigurability, adaptability, complexity and stochasticity observed in nervous systems. The term ‘neuromorphic’ computing is often credited to Carver Mead, who in the 1980s investigated Si-based analog electronics to replicate functions of the animal retina. Earlier important advances in this field include the work of Frank Rosenblatt, who proposed the concept of the perceptron, Bernard Widrow, who used this concept to build one of the first analog neural networks, the Adaline and many other researchers (see ref. 6 for an historical perspective on neuromorphic computing). With the recent increase in the use of artificial intelligence and large language models, and rising concerns over the associated energy costs, interest in neuromorphic hardware has expanded rapidly. According to some estimates, driven largely by the drastic growth in the training use of artificial intelligence (AI) models using the current computing architectures, the energy cost of computing is projected to reach the energy supply worldwide by 2045. Furthermore, while this is not a realistic outcome, it means that, if more efficient computing technologies are not developed -- soon -- the world will soon become one where demand for energy and market constraints limit the continued increase of societal access to AI and cloud services from data centers. Data centers used for training and use of these models consume hundreds of terawatt hours of electricity, already past 4% of the US electricity demand.

Circuits↗

DOE OSTI2024

The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results

Exploiting the “sparse” nature of the information in XPCS (X-ray Photon Correlation Spectroscopy) and XSVS (Speckle Visibility Spectroscopy) experiments, we present the SparkPix-S, a 3-sides buttable Application Specific Integrated Circuit (ASIC) based on a sparsified readout strategy for large-format hybrid detectors. The SparkPix-S architecture, based on the successful ePix family, will be composed as follows: a front-end 2-D matrix of 384×352 square pixels with 50 µm pitch is arranged to match the dimensions of a PIN Si-sensor matrix; charge readout, signal shaping and amplitude discrimination is performed at pixel-level, by means of a low-power (<18 µW) analog processor, which, in case of an event, negotiates access to an analog bus placed every other column; on the chip periphery (balcony), the information on each bus is digitized by an array of successive approximation analog-to-digital converters (SAR-ADCs) running at 10 Msps; on the digital back-end the global logic will generate the output data stream using low-voltage differential signalling (LVDS). A first prototype of the SparkPix-S, with a reduced matrix size of 96×96 pixels, is currently under production on a 130 nm CMOS technology. Simulated performance results show an equivalent noise charge <60 el. r.m.s. at 1 MHz repetition rate, with a maximum input energy of 60 keV and capability to discriminate charge signals with equivalent energy as low as 900 eV.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2021

OPERATING EXPERIENCE AND ITS RELATIONSHIP TO EMBEDDED DIGITAL DEVICES IN SAFETY SYSTEMS

Interest in embedded digital devices (EDDs) for monitoring and providing control of components is increasing and the added functionality digital brings such as diagnostics, displays, control functions is welcomed in both the nuclear and other industries. As a result, pure analog-based components continue to disappear from the industrial I&C marketplace. Equipment with EDDs, also known by related terms such as smart devices, intelligent devices, and digital devices of limited functionality, can include sensors, breakers, priority logic modules, time delay relays, pumps, valve actuators, motor control centers, and uninterruptible power supplies. Not only is equipment consisting of analog and older digital technology being replaced with commercial grade products containing EDDs, but EDDs can also be retrofitted to work with existing components. EDDs may be installed physically within a component, such as in a relay. There are also external devices that some would not consider an EDD, but that operate in almost all technical ways identically to one internal to a component such as in a valve controller. In fact, the digital portions may be located hundreds of feet from the actual component.Due to the potential of being used in an identical manner and without alteration from their application in other industries, operating experience (OpE) for EDDs may be much more applicable than in the case of other more system level devices. Clear separation and independence of functionality provided with EDDs may also allow greater applicability of existing OpE from industry for changes that can be shown not to affect its safety function. However, OpE also demonstrates issues with different conditions between other industries and nuclear power plants, such as issues with undeclared changes or undeclared digital devices and the new failure modes they may introduce, issues with the reporting of OpE in industry, and a lack of transparency into OpE for EDDs.Understanding and addressing these issues will be key in the future use of EDDs in nuclear power plants, but failure rate data is difficult to obtain for EDDs, and lessons learned from the use of EDDs are difficult to collect and identify.Key words: embedded digital device, smart device, operating experience, failure modes

Muhlheim, Michael↗

DOE OSTI2022

Event driven readout architecture with non-priority arbitration for radiation detectors

A novel event driven readout architecture, EDWARD (Event Driven with Access and 8 Reset Decoder) architecture, for highly granular pixel detectors is presented. It incorporates, inter alia, an asynchronous arbitration tree based on Seitz' arbiters, removing the need for an imposed prioritization scheme. It also provides protection against glitches during readout. The system allows not only reading pixel activities, but also retrieving additional data, both analog and digital, from the pixels. A novel in-channel logic allows the entire readout process to be split into consecutive phases for additional flexibility. All operations are controlled by only one edge of the clock signal, seen as an acknowledge token, so there is no dead time between readouts.

47 OTHER INSTRUMENTATION↗

DOE OSTI2025

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗

DOE OSTI2023

Performance and Commissioning of the BigBite Timing Hodoscope for Nucleon Form Factor Measurements at Jefferson Lab

The BigBite Timing Hodoscope detector is the primary subject of this thesis. The Super BigBite Spectrometer is a Jefferson Lab Hall A Collaboration project that has and will continue to measure nucleon electromagnetic form factors. This spectrometer includes the Timing Hodoscope which provides high resolution particle timing data for scattered electrons in the electron arm of BigBite. The Timing Hodoscope utilizes 90, 25 × 25 × 600 mm3 scintillator bars stacked on top of each other to form a single detector plane, and these bars are connected to 180 photo-multiplier tubes via light guides. Particles collide with the scintillating material creating a shower of optical photons and these particle events in the bars are collected to generate signals that are readout by the data acquisition (DAQ) electronics. NINO ASIC amplifier-discriminator cards output signals from the photo-multiplier tubes into analogue and logic signals, which are sent to analogue-to-digital (ADC) and time-to-digital (TDC) converter data acquisition readout modules. This data is then used for analysis of the detector. The focus of this thesis is the construction, commissioning, calibration, and performance of the BigBite Timing Hodoscope before and during the first of five nucleon electromagnetic form factor experiments at Jefferson Lab Hall A. Before the neutron magnetic form factor, G n M, experiment, cosmic ray data was collected during commissioning to confirm proper operation of the Timing Hodoscope electronics by observing the ADC and TDC data. Commissioning studies for charge normalization, gain matching, and other ADC and TDC detector data variables were performed before moving the detector into Hall A. Following installation in Hall A, several calibration studies were implemented to fine-tune the detector in preparation for use in the experiment. The calibration studies included analysis of timing cuts, TDC alignment, the time-walk effect, time difference offsets, and scintillator velocity corrections. Once the Timing Hodoscope was well-calibrated, data-taking during the experiment commenced and the beam-on-target data was used to characterize the Timing Hodoscope performance during the G n M experiment run-time. The performance analysis included studies observing energy deposit, cluster size, rates, accidentals, pile-up, tracking efficiency, position resolution, and time resolution. After application of physics cuts to ensure a data set comprised of particle tracks corresponding to elastic electrons, which is the main data of interest for measurement of G n M, the Timing Hodoscope is shown on average across all kinematic settings to have a >98% tracking efficiency, a position resolution of 4-6 cm in the non-dispersive plane and 1.5-2 cm in the dispersive plane, and a time resolution of 500-750 ps. These performance results are compared to a GEANT4 based performance simulation of the BigBite Timing Hodoscope for reference, showing to what degree the measured performance values match those taken from the simulation.

Marinaro, Ralph↗

DOE OSTI2024

Calibration of the analog beam-signal hardware for the credited engineered beam power limit system at the Proton Power Upgrade Project at the Spallation Neutron Source

A programmable signal processor-based credited safety control that calculates pulsed beam power based on beam kinetic energy and charge was designed as part of the Proton Power Upgrade (PPU) project at the Spallation Neutron Source (SNS). The system must reliably shut off the beam if the average power exceeds 2.145 MW averaging over 60 seconds. System calibration requires pedigree in measurements, calibration setup, and calculations. This paper discusses the calibration of the analog beam signal components up to and including the Analog Digital Convertors (ADCs) for implementation into the Safety Programmable Logic Controllers (PLCs) and Field Programmable Gate Arrays (FPGAs).

Bobrek, Miljko↗

DOE OSTI2025

A Digital Three Level Space Vector Modulator for High Frequency Vector Sequence Generation

This letter proposes a digital high-speed three-level space vector pulse width modulator (3L-SVPWM). A conventional 3L-SVPWM is typically computation-based, involving a sequential execution of sub-tasks on a digital signal processor (DSP) based controller. The resulting high computation time of 5.4 μs limits the implementation of additional control blocks for switching frequencies greater than 100 kHz. This is overcome by transforming sub-tasks into digital blocks with 1-0 decisions and simpler arithmetic operations. The sub-task blocks are executed concurrently on a programmable logic device (PLD). Hence, a fast 3L-SVPWM execution in 140 ns is achieved. The proposed digital 3L-SVPWM enables high switching frequency operation of wide bandgap (WBG) device-based 3 L inverters to generate high fundamental frequency waveforms. A finite state machine is an integral part of the proposed implementation with the ability to generate any vector sequence, maximizing the usage of redundant vector states in 3L-SVPWM. Here, the proposed digital 3L-SVPWM operation is demonstrated with a GaN-based 3 L active neutral point clamped (3L-ANPC) inverter. Experimental results are presented at 250 kHz switching frequency to generate vector sequences for center-aligned SVPWM (CA-SVPWM) and common mode voltage reduced SVPWM (CMVR-SVPWM). The results also showcase a high fundamental frequency generation capability of 10 kHz.

active neutral point clamped inverter↗

DOE OSTI2021

UEMtomaton: A Source-Available Platform to Aid in Start-up of Ultrafast Electron Microscopy Labs

The steady rise in the number of ultrafast electron microscopy (UEM) labs, in addition to the opacity and lack of detailed descriptions of current approaches that would enable point-by-point construction, has created an opportunity for sharing common methods and instrumentation for (for example) automating data acquisition to assist in efficient lab start-up and to learn about common and robust protocols. In the spirit of open sharing of methods, we provide here a description of an entry-level method and user interface (UI) for automating UEM experiments, and we provide access to the source code and scripts (source-available) for ease of implementation or as a starting reference point for those entering or seeking to enter the field (https://github.com/CEMSFlannigan/UEMtomaton/releases/tag/v1.0). Core instrumentation and physical connections in the UEM lab at Minnesota are described. Interface communication schemes consisting of duo server-client pairs between critical components – the optical delay stage and the UEM digital camera – are presented, with emphasis placed on describing the logic and communications sequence designed to conduct automated series acquisitions. An application designed and programmed with C++/CLI as Windows Forms in Microsoft Visual Studio – dubbed UEMtomaton – is also presented. Key to the UI layout is centralization of the automation tasks and establishment of communication within the software rather than by interfacing with each individual workstation. It is our hope that this note provides useful insight for current and future UEM researchers, particularly with respect to generalizability and portability of the approach to emerging labs. Here, we note that while this basic, entry-level approach is certainly not the most sophisticated or comprehensive of those currently in use, we feel there is nevertheless value in clearly communicating a proven straightforward method to hopefully lower the barrier to entry into the field.

47 OTHER INSTRUMENTATION↗

DOE OSTI2025

Rapid Inference of Logic Gate Neural Networks for Anomaly Detection in High Energy Physics

The increasing data rates and complexity of detectors at the Large Hadron Collider (LHC) necessitate fast and efficient machine learning models, particularly for rapid selection of what data to store, known as triggering. Building on recent work in differentiable logic gates, we present a public implementation of a Convolutional Differentiable Logic Gate Neural Network (CLGN). We apply this to detecting anomalies at the Level-1 Trigger at CMS using public data from the CICADA project. We demonstrate that the CLGN achieves physics performance on par with or superior to conventional quantized neural networks. We also synthesize an LGN for a Field-Programmable Gate Array (FPGA) and show highly promising FPGA characteristics, notably zero Digital Signal Processor (DSP) resource usage. This work highlights the potential of logic gate networks for high-speed, on-detector inference in High Energy Physics and beyond.

FOS: Physical sciences↗

DOE OSTI2025

Reconfigurable neuromorphic components and algorithms for next-generation artificial intelligence

Digital transistor-based general-purpose hardware (e.g., central processing units) is the dominant solution to support both traditional computing (logic, arithmetic, etc.) as well as modern artificial intelligence. State-of-the-art research has shown feasibility of post-digital physics-based neuromorphic hardware, which is hypothesized to support artificial intelligence algorithms with orders-of-magnitude improved time/energy efficiencies. But such research has not been widely deployed mainly because of such novel hardware’s extreme application-specificity, and the dominance of low-cost general-purpose (but inefficient) digital hardware. To make use of the novel algorithms and the superlative performance of physics-based hardware, we need to identify scientific principles that can enable generality in physics-based hardware. This work resulted in two important broad outcomes – first, we demonstrate fully reconfigurable neuromorphic components, and second, we demonstrate a viable artificial intelligence learning algorithm that can exploit the functioning of neuromorphic hardware. We demonstrate up to five orders of magnitude improvement in energy efficiency compared to the best general-purpose digital hardware.

97 MATHEMATICS AND COMPUTING↗