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DOE OSTI2022

Radiation-Hardened GaN HEMT and Cell Design, Modeling, and Fabrication for Nuclear Instrumentation Applications

Recent advances in nuclear power generation technologies show great promise for efficient, safe generation of carbon-free power in the near future. Consequently, many new generation reactor designs are being pursued by government and industry groups, including both fission- and fusion-based technologies. Radiation- and temperature-tolerant sensor technology continues to advance, yet development of the electronics/instrumentation technologies suitable for these environments have fallen behind. Industry has adequately addressed harsh environment electronics needs for low earth orbit satellites, but the much more extreme conditions associated with electronics placed near or in a reactor core remain unaddressed. This project investigates the use of gallium nitride (GaN) circuit technology to address the unique needs for sensor interface electronics and communications in reactor environments. This report provides a summary of the first year’s project activities related to developing and optimizing devices and circuits for this GaN high electronic mobility transistor (HEMT) process. Activities reported include multiple analog and digital circuit designs simulated using custom Verilog-A models generated from measured GaN devices fabricated in the target process. Digital circuit designs included fundamental logic circuits such as an inverter, NAND, NOR, AND and OR gates, as well as a 5-stage ring oscillator. Each design was simulated using an open-source SPICE simulator, and an integrated circuit layout was produced of each design for use in future fabrication. Analog circuit designs focused on the fundamental building blocks to be used to construct sensor interface and communications circuits. These included current mirrors, matched differential pairs, and a Gilbert cell mixer design, each with an associated integrated circuit layout. Layout tools used for these designs included two open-source packages—KLayout and Magic—which were customized for specific use with the OSU GaN process layers. Design rules and preliminary device extraction capabilities were built for the Magic tool to enable device extraction and subsequent netlist generation for SPICE simulation. Finally, future research directions for year two are summarized. When the year-two directions are implemented, the project will be in position to advance the state of the art in electronics for near- or in-reactor sensor interfacing and communications.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2025

Status of the Mu2e calorimeter readout electronics

The Mu2e experiment [1] at Fermilab will search for the neutrino-less coherent conversion of a muon into an electron in the field of a nucleus. Mu2e detectors comprise a straw tracker, an electromagnetic calorimeter and a veto for cosmic rays. The calorimeter employs 1348 Cesium Iodide crystals readout by silicon photomultipliers and fast front-end and digitization electronics. The front-end electronics consists of two discrete readout circuits (AMP-HV) for each crystal. These provide the amplification, shaping stage and linear regulation of the SiPM bias voltage and monitoring. The SiPM and front-end control electronics is implemented in a battery of mezzanine boards each equipped with an ARM processor that controls a group of 20 Amp-HV circuits distributing the low voltage and the high-voltage. The electronic is hosted in crates located on the external surface of calorimeter disks. The crates also host the waveform digitizer board (DIRAC) that performs digitization of the front end signals and transmit the digitized data to the Mu2e DAQ. Calorimeter electronic is hosted inside the cryostat and must sustain very high radiation and magnetic field so it was necessary to fully qualify it. The system design and quality assurance procedures will be reviewed.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗

DOE OSTI2026

Low power on-chip data transmission for wafer-scale monolithic active pixel sensors

Here, this paper details the implementation of the digital pulse shaping subsystem within the Backbone Transmission Line Encoding (BTLE) driver, a low-power, long-distance on-chip data transmission solution designed in a 65 nm CMOS process. Digital pulse shaping is critical for minimizing inter-symbol interference (ISI) caused by bandwidth limitations of on-chip interconnects, especially in wafer-scale monolithic active pixel sensors (MAPS). A duobinary encoder coupled with a parallelized polyphase finite impulse response (FIR) filter is used for efficient shaping of the transmitted signal spectrum. This reconfigurable architecture achieves reliable 160 Mb/s data transfer over a 10 cm on-chip link, as validated by simulations demonstrating low power consumption (FoM 37.3 fJ/bit/mm of transmission line length) and effective ISI mitigation.

47 OTHER INSTRUMENTATION↗

DOE OSTI2021

Simplified feedback control system for scanning tunneling microscopy

A Scanning Tunneling Microscope (STM) is one of the most important scanning probe tools available to study and manipulate matter at the nanoscale. In a STM, a tip is scanned on top of a surface with a separation of a few Å. Often, the tunneling current between the tip and the sample is maintained constant by modifying the distance between the tip apex and the surface through a feedback mechanism acting on a piezoelectric transducer. This produces very detailed images of the electronic properties of the surface. The feedback mechanism is nearly always made using a digital processing circuit separate from the user computer. Here, we discuss another approach using a computer and data acquisition through the universal serial bus port. We find that it allows successful ultralow noise studies of surfaces at cryogenic temperatures. We show results on different compounds including a type II Weyl semimetal (WTe2), a quasi-two-dimensional dichalcogenide superconductor (2H–NbSe2), a magnetic Weyl semimetal (Co3Sn2S2), and an iron pnictide superconductor (FeSe).

Martín-Vega, Francisco (ORCID:0000000333177833)↗

DOE OSTI2023

Contact-Less Integrity Verification of Microelectronics Using Near-Field EM Analysis

Modern microelectronics life-cycle and supply chain ecosystem bring multiple untrusted entities, which can compromise their integrity. A major integrity issue of microelectronics stems from piracy of intellectual properties (IP) and counterfeiting, which causes significant revenue loss to the semiconductor manufacturers. Further, these components often lead to compromised functionality, reliability, security, and safety of an electronic system. This paper presents secure information transmission and probing methods for verifying the integrity of digital integrated circuit (ICs) based on their electromagnetic (EM) near-field emissions and thereby protecting systems against counterfeit components. The proposed method has been tested on both high-level instructions executed by microprocessors or Systems-on-Chip (serving as examples of software), and also logic circuits within FPGA fabrics and ASICs (serving as examples of hardware). The authentication information required by each digital system is generated using a pseudo-random number generator circuit and securely transmitted via near-field magnetic emissions. The authorized party can probe these emissions using a near-field probe, process the acquired signals to improve the signal-to-noise ratio (SNR), and then recover the secure information through matched filtering. Experimental results from commercial SoCs are used to demonstrate the proposed technique. Methods for reducing EM interference during integrity verification of both FPGAs and ASICs are also described.

47 OTHER INSTRUMENTATION↗

DOE OSTI2023

On-Chip Batteries as Distributed Energy Sources in Heterogeneous 2.5D/3D Integrated Circuits

Energy efficiency in digital systems faces challenges due to the constraints imposed by small-scale transistors. Moreover, the growing demand for portable consumer electronics necessitates the use of compact energy sources. To address these challenges, heterogeneous 3D IC technology has emerged as a promising solution for the former. Regarding the latter, we propose the concept of distributed batteries within a heterogeneous 3D IC. This approach involves utilizing multiple smaller batteries with different specifications among different modules of 3D ICs. This approach optimizes performance and overcomes limitations associated with both 3D ICs and conventional power delivery methods. Distributed batteries play a vital role in effectively managing the heat generated by energy sources and modules within a 3D IC. Furthermore, they contribute to achieving a uniform distribution of heat throughout the entire structure, which ultimately ensures the optimal performance of the batteries and modules. The simulation results indicate a 40 percent enhancement in achieving a more even distribution of generated heat. Additionally, the proposed distributed battery techniques improve power delivery, enhance reliability, and enable optimized voltage regulation while improving efficiency. In addition to the primary benefits, alternative configurations of the proposed approach can offer extra energy storage capacity and act as efficient electromagnetic shields, resulting in an impressive reduction of external electromagnetic noises by 60 dB.

47 OTHER INSTRUMENTATION↗

DOE OSTI2020

Detailed modeling of the video signal and optimal readout of charge-coupled devices

This paper provides a practical design methodology to calculate an optimal filter for noise reduction in the readout of charge-coupled devices (CCDs) taking into account the charge transfer and feedthroughs due to capacitive coupling in the CCD. A detailed analysis of the dynamics of the video signal and charge transfer is presented, including the circuital modeling of the output stage of the CCD and the dynamics of the electronics in the video chain before the analog-to-digital (AD) converter. This model is used to compute an optimal filter that minimizes the variance of the pixel noise and uses the samples of the charge transfer, before the charge is fully settled. This is necessary to enhance the performance of previous results that also use optimal filters but do not use the transition samples, while also reducing the pixel readout time, resulting in faster readouts. As a proof of concept for the optimal filter, we present in this paper novel experimental results using a Skipper CCD, which has a floating sense node that allows to measure the charge packet an arbitrary number of times. However, this technique can be applied to any CCD that has a readout system that digitally samples the video signal.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2026

Large-scale real-time signal processing in physics experiments: the ALICE TPC FPGA pipeline

For LHC Run 3, the ALICE Time Projection Chamber was upgraded to operate in continuous readout mode. Interaction rates of up to 50 kHz in Pb-Pb collisions require real-time processing of more than 3 TB s -1 of raw detector data. This requirement is met by a custom FPGA-based processing pipeline that performs the complete front-end data treatment fully in-stream, including common-mode correction, pedestal subtraction, ion-tail filtering, zero suppression, and dense data packing. A central element of the design is a highly parallel common-mode correction algorithm operating directly on the streaming data. It robustly identifies signal-free readout channels on a time-bin basis and applies pad-dependent scaling to compensate for local variations in capacitive coupling in the GEM readout. In combination with pedestal subtraction and ion-tail filtering, this enables accurate baseline restoration under extreme high-occupancy conditions, preventing signal loss while efficiently suppressing noise prior to zero suppression. The pipeline operates continuously at the full detector bandwidth and reduces the raw input rate of approximately 3 TB s -1 to about 900 GBps for Pb-Pb collisions at the target interaction rate. Overall, it represents a large-scale FPGA-based real-time signal-processing implementation for high-energy physics detector readout.

Digital signal processing (DSP)↗

DOE OSTI2023

Photon-to-Digital Converters for Neutron Imaging Instruments (Final Report)

Oak Ridge National Laboratory (ORNL) collaborated with the Université de Sherbrooke (UdeS) to design a modular and scalable tile of innovative digital photodetectors called Photon-to-Digital Converters (PDC) and the required subsystems to demonstrate the feasibility of large area single-photon detectors to support high-resolution, depth-of-interaction, fast neutron radiography based on scintillation detectors. The goal is to demonstrate the advantages of using PDC over conventional Silicon Photomultiplier (SiPM) for neutron imaging systems. The basic building blocks of analog SiPM and PDC are Single-Photon Avalanche Photodiodes (SPAD). The main difference between conventional SiPMs and PDCs, is in the fact that analog SiPMs sum the charge produced by individual SPAD passively, while in PDCs each SPAD is read out individually by an active electronic circuit. Hence, PDCs provide a direct photon-to-bit conversion where a logic “1” means that there was a detection in a given SPAD. Conversely, an analog SiPM requires a sophisticated preamplifier (current amplifiers or transimpedance amplifier) followed by a shaping amplifier and an analog-to-digital converter. Moreover, since the charge from each SPAD varies slightly, the passive sum of the analog SiPM will have signal fluctuations for the same amount of photon detected. This is one of many issues that is completely eliminated by individual one-to-one SPAD read out in PDCs. The large area required for scintillator readouts for neutron imaging is such that the output capacitance of a large area of SiPM arrays is very high. This creates a burden on the signal-to-noise optimization with respect to the power budget. For PDC, the power consumption is dictated by rate of the incident photon flux, or in photon-starved environments, the dark noise rate of the SPAD array. In other words, the power consumption in the absence of events is extremely low. Hence, the power consumption of a PDC read out system is much lower than its analog counterpart. Further, the large SiPM capacitance may introduce signal distortions on the scintillator fast rise or decay time with undesired effects on timing and pulse shape discrimination. The problem is absent in PDCs, as their readout is independent on device capacitance. UdeS is the world leader in 3D vertical integration of frontside illuminated SPAD arrays over CMOS readouts. These capabilities allow future production of “3D PDC” with maximum photosensitive fill factor and electronic functionalities tailored to the application. UdeS' vast knowledge of SPADs and CMOS design made the team an ideal collaborator in the development of large area high-resolution fast neutron radiography.

42 ENGINEERING↗

DOE OSTI2025

Unconventional compute methods and future challenges for superconducting digital computing

Superconducting digital computing (SDC) based on Josephson junctions (JJs) offers significant potential for enhancing compute throughput and reducing energy consumption compared to conventional room-temperature CMOS-based approaches. Current superconducting logic families exhibit diverse characteristics in clocking strategies, power management, and information encoding techniques. This paper reviews recent advancements in unconventional computing methods specifically designed for superconducting digital circuits, emphasizing temporal computing and pulse-train representations. Notable techniques include race logic (RL), temporal pulse train computing (U-SFQ), and temporal multipliers, each offering unique performance and area advantages suited to superconducting implementations. Additionally, this paper reviews innovations in superconducting coarse-grain reconfigurable architectures (CGRA), superconducting-specific on-chip communication architectures, cryogenic sensor interfaces, and quantum computing control electronics. Finally, we highlight research challenges that should be addressed to facilitate the widespread adoption of superconducting digital computing.

EDA tools↗

DOE OSTI2022

Multiplexed Readout for an Experiment with a Large Number of Channels Using Single-Electron Sensitivity Skipper-CCDs

This paper presents the implementation of a multiplexed analog readout electronics system that can achieve single-electron counting using Skipper-CCDs with non-destructive readout. The proposed system allows the best performance of the sensors to be maintained, with sub-electron noise-level operation, while maintaining low-bandwidth data transfer, a minimum number of analog-to-digital converters (ADC) and low disk storage requirement with zero added multiplexing time, even for the simultaneous operation of thousands of channels. These features are possible with a combination of analog charge pile-up, sample and hold circuits and analog multiplexing. The implementation also aims to use the minimum number of components in circuits to keep compatibility with high-channel-density experiments using Skipper-CCDs for low-threshold particle detection applications. Performance details and experimental results using a sensor with 16 output stages are presented along with a review of the circuit design considerations.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

DOE OSTI2022

Waveform processing using neural network algorithms on the front-end electronics

In a multi-channel radiation detector readout system, waveform sampling, digitization, and raw data transmission to the data acquisition system constitute a conventional processing chain. The deposited energy on the sensor is estimated by extracting peak amplitudes, area under pulse envelopes from the raw data, and starting times of signals or time of arrivals. However, such quantities can be estimated using machine learning algorithms on the front-end Application-Specific Integrated Circuits (ASICs), often termed as “edge computing”. Edge computation offers enormous benefits, especially when the analytical forms are not fully known or the registered waveform suffers from noise and imperfections of practical implementations. In this work, we aim to predict peak amplitude from a single waveform snippet whose rising and falling edges containing only 3 to 4 samples. We thoroughly studied two well-accepted neural network algorithms, Multi-Layer Perceptron (MLP) and Convolutional Neural Network (CNN) by varying their model sizes. Further, to better fit front-end electronics, neural network model reduction techniques, such as network pruning methods and variable-bit quantization approaches, were also studied. By combining pruning and quantization, our best performing model has the size of 1.5 KB, reduced from 16.6 KB of its full model counterpart. It can reach mean absolute error of 0.034 comparing to that of a naive baseline of 0.135. Such parameter-efficient and predictive neural network models established feasibility and practicality of their deployment on front-end ASICs.

47 OTHER INSTRUMENTATION↗

DOE OSTI2024

A Modular 512-Channel Neural Signal Acquisition ASIC for High-Density 4096 Channel Electrophysiology

The complexity of information processing in the brain requires the development of technologies that can provide spatial and temporal resolution by means of dense electrode arrays paired with high-channel-count signal acquisition electronics. In this work, we present an ultra-low noise modular 512-channel neural recording circuit that is scalable to up to 4096 simultaneously recording channels. The neural readout application-specific integrated circuit (ASIC) uses a dense 8.2 mm × 6.8 mm 2D layout to enable high-channel count, creating an ultra-light 350 mg flexible module. The module can be deployed on headstages for small animals like rodents and songbirds, and it can be integrated with a variety of electrode arrays. The chip was fabricated in a TSMC 0.18 µm 1.8 V CMOS technology and dissipates a total of 125 mW. Each DC-coupled channel features a gain and bandwidth programmable analog front-end along with 14 b analog-to-digital conversion at speeds up to 30 kS/s. Additionally, each front-end includes programmable electrode plating and electrode impedance measurement capability. We present both standalone and in vivo measurements results, demonstrating the readout of spikes and field potentials that are modulated by a sensory input.

47 OTHER INSTRUMENTATION↗

DOE OSTI2021

Graphene nanoribbons for quantum electronics

Graphene nanoribbons (GNRs) are a family of one-dimensional (1D) materials with a graphitic lattice structure. GNRs possess high mobility and current-carrying capability, sizeable bandgap and versatile electronic properties, which make them promising candidates for quantum electronic applications. In the past 5 years, progress has been made towards atomically precise bottom-up synthesis of GNRs and heterojunctions that provide an ideal platform for functional molecular devices, as well as successful production of semiconducting GNR arrays on insulating substrates potentially useful for large-scale digital circuits. With further development, GNRs can be envisioned as a competitive candidate material in future quantum information sciences. In this Perspective, we discuss recent progress in GNR research and identify key challenges and new directions likely to develop in the near future.

36 MATERIALS SCIENCE↗

DOE OSTI2026

Digital Silicon Photomultiplier Chip Testing

Silicon Photomultipliers (SiPMs) are highly sensitive photodetectors. Traditional analog SiPMs require complex external readout electronics. Digital SiPMs (dSiPMs) include digital readout circuitry directly on-chip, offering superior timing resolution, reduced power consumption and compact size, pixel-level masking for active noise reduction. The primary objectives of this study are to, verify digital logic integrity of the shift registers used for controlling the pixel masking circuit, and determine the dark count rate of individual pixels as a function of bias voltage and clock frequency. I observe and explain behavior of the shift register and counting circuit.

Graham, Bennett [U. Chicago (main)]↗

DOE OSTI2023

A superconducting nanowire binary shift register

We present a design for a superconducting nanowire binary shift register, which stores digital states in the form of circulating supercurrents in high-kinetic-inductance loops. Adjacent superconducting loops are connected with nanocryotrons, three-terminal electrothermal switches, and fed with an alternating two-phase clock to synchronously transfer the digital state between the loops. A two-loop serial-input shift register was fabricated with thin-film NbN and a bit error rate of less than 10 –4 was achieved, when operated at a maximum clock frequency of 83 MHz and in an out-of-plane magnetic field of up to 6 mT. A shift register based on this technology offers an integrated solution for low-power readout of superconducting nanowire single photon detector arrays and is capable of interfacing directly with room-temperature electronics and operating unshielded in high magnetic field environments.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2020

Reconfigurable Real-Time Power Grid Emulator for Systems With High Penetration of Renewables

Novel power system control and new utility devices need to be tested before their actual deployment to the power grid. To assist with such a testing need, real-time digital emulators such as RTDS and Opal-RT can be used to connect to the physical world and form a hardware in the loop (HIL) emulation. However, due to the limitations of today's computational resources, the accuracy and fidelity suffer from different levels of model reductions in purely digital simulations. CURENT has developed a reconfigurable electric grid hardware testbed (HTB) to overcome the limitations of digital emulators. The HTB has been used to develop measurement, control, modeling, and actuation techniques for a national grid with a high penetration of renewables. The power electronic-based system includes emulators for synchronous generators; photovoltaics with grid-interfacing inverter; wind turbines; induction motor loads, ZIP loads, power electronic loads; batteries; ac and dc transmission lines; short circuit faults and grid relay protection; and a multiterminal HVDC overlay including power electronics interfaces. The system contains real elements of power flow, measurement, communication, protection, and control that mimic what would be seen in an actual electric grid. This paper presents an overview of the HTB and several scenarios that have been run to determine control and actions needed for the future power grid.

24 POWER TRANSMISSION AND DISTRIBUTION↗

DOE OSTI2021

Compact, low power, high resolution ADC per pixel for large area pixel detectors

A compact ADC circuit can include one or more comparators, and a serial DAC (Digital-to-Analog) circuit that provides a signal to the comparator (or comparators). In addition, the ADC circuit can include a serial DAC redistribution sequencer that can provide a plurality of signals as input to the serial DAC circuit and is subject to a redistribution cycle and which receives as input a signal from a data multiplexer whose input connects electronically to an output of the comparator. The circuit can further include an ADC code register that provides an ADC output that connects electronically to the output of the comparator and the input to the data multiplexer. Shared logic circuitry for sharing common logic between pixels can be included, wherein the shared logic circuitry connects electronically to the data multiplexer and the ADC code register, wherein the shared logic circuitry promotes area and power savings for the pixel detector circuit.

Zimmerman, Tom↗