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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2015

Spin Seebeck devices using local on-chip heating

A micro-patterned spin Seebeck device is fabricated using an on-chip heater. Current is driven through a Au heater layer electrically isolated from a bilayer consisting of Fe{sub 3}O{sub 4} (insulating ferrimagnet) and a spin detector layer. It is shown that through this method it is possible to measure the longitudinal spin Seebeck effect (SSE) for small area magnetic devices, equivalent to traditional macroscopic SSE experiments. Using a lock-in detection technique, it is possible to more sensitively characterize both the SSE and the anomalous Nernst effect (ANE), as well as the inverse spin Hall effect in various spin detector materials. By using the spin detector layer as a thermometer, we can obtain a value for the temperature gradient across the device. These results are well matched to values obtained through electromagnetic/thermal modeling of the device structure and with large area spin Seebeck measurements.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2014

Intermixing at the absorber-buffer layer interface in thin-film solar cells: The electronic effects of point defects in Cu(In,Ga)(Se,S){sub 2} and Cu{sub 2}ZnSn(Se,S){sub 4} devices

We investigate point defects in the buffer layers CdS and ZnS that may arise from intermixing with Cu(In,Ga)(S,Se){sub 2} (CIGS) or Cu{sub 2}ZnSn(S,Se){sub 4} (CZTS) absorber layers in thin-film photovoltaics. Using hybrid functional calculations, we characterize the electrical and optical behavior of Cu, In, Ga, Se, Sn, Zn, Na, and K impurities in the buffer. We find that In and Ga substituted on the cation site act as shallow donors in CdS and tend to enhance the prevailing n-type conductivity at the interface facilitated by Cd incorporation in CIGS, whereas they are deep donors in ZnS and will be less effective dopants. Substitutional In and Ga can favorably form complexes with cation vacancies (A-centers) which may contribute to the “red kink” effect observed in some CIGS-based devices. For CZTS absorbers, we find that Zn and Sn defects substituting on the buffer cation site are electrically inactive in n-type buffers and will not supplement the donor doping at the interface as in CIGS/CdS or ZnS devices. Sn may also preferentially incorporate on the S site as a deep acceptor in n-type ZnS, which suggests possible concerns with absorber-related interfacial compensation in CZTS devices with ZnS-derived buffers. Cu, Na, and K impurities are found to all have the same qualitative behavior, most favorably acting as compensating acceptors when substituting on the cation site. Our results suggest one beneficial role of K and Na incorporation in CIGS or CZTS devices is the partial passivation of vacancy-related centers in CdS and ZnS buffers, rendering them less effective interfacial hole traps and recombination centers.

36 MATERIALS SCIENCE↗
DOE OSTI2016

Wild Band Edges: The Role of Bandgap Grading and Band-Edge Fluctuations in High-Efficiency Chalcogenide Devices

Band-edge effects - including grading, electrostatic fluctuations, bandgap fluctuations, and band tails - affect chalcogenide device efficiency. These effects now require more careful consideration as efficiencies increase beyond 20%. Several aspects of the relationships between band-edge phenomena and device performance for NREL absorbers are examined. For Cu(In, Ga)Se2 devices, recent increases in diffusion length imply changes to the optimum bandgap profile. The origin, impact, and modification of electrostatic and bandgap fluctuations are also discussed. The application of the same principles to devices based on CdTe, kesterites, and emerging absorbers (Cu2SnS3, CuSbS2), considering differences in materials properties, is examined.

14 SOLAR ENERGY↗
DOE OSTI2020

Absence of evidence for chiral Majorana modes in quantum anomalous Hall-superconductor devices

A quantum anomalous Hall (QAH) insulator coupled to an s-wave superconductor is predicted to harbor chiral Majorana modes. A recent experiment interprets the half-quantized two-terminal conductance plateau as evidence for these modes in a millimeter-size QAH-niobium hybrid device. However, non-Majorana mechanisms can also generate similar signatures, especially in disordered samples. Here, we studied similar hybrid devices with a well-controlled and transparent interface between the superconductor and the QAH insulator. When the devices are in the QAH state with well-aligned magnetization, the two-terminal conductance is always half-quantized. Our experiment provides a comprehensive understanding of the superconducting proximity effect observed in QAH-superconductor hybrid devices and shows that the half-quantized conductance plateau is unlikely to be induced by chiral Majorana fermions in samples with a highly transparent interface.

Science & Technology - Other Topics↗
DOE OSTI2014

Method and system for reducing device performance degradation of organic devices

Methods and systems for reducing the deleterious effects of gate bias stress on the drain current of an organic device, such as an organic thin film transistor, are provided. In a particular aspect, the organic layer of an organic device is illuminated with light having characteristics selected to reduce the gate bias voltage effects on the drain current of the organic device. For instance, the wavelength and intensity of the light are selected to provide a desired recovery of drain current of the organic device. If the characteristics of the light are appropriately matched to the organic device, recovery of the deleterious effects caused by gate bias voltage stress effects on the drain current of the organic device can be achieved. In a particular aspect, the organic device is selectively illuminated with light to operate the organic device in multiple modes of operation.

36 MATERIALS SCIENCE↗
DOE OSTI2014

Release strategies for making transferable semiconductor structures, devices and device components

Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

14 SOLAR ENERGY↗
DOE OSTI2016

Release strategies for making transferable semiconductor structures, devices and device components

Provided are methods for making a device or device component by providing a multi layer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

14 SOLAR ENERGY↗
DOE OSTI2020

Modeling Needs for Power Semiconductor Devices and Power Electronics Systems: Preprint

As energy systems move towards wide-spread electrification, penetration of power semiconductor devices and power electronics continues to grow at a rapid pace. This paper attempts to review the state of the art in power semiconductor modeling and the existing state of modeling in general when in it comes to design of devices and systems. The modeling needs for semiconductor devices vary depending on the end goal, and the level of abstraction needed towards model formulation also changes with the size and complexity of system to be designed. Finally, key aspects of thermal design and modeling for power electronics are also discussed.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2017

Impact of Linearity and Write Noise of Analog Resistive Memory Devices in a Neural Algorithm Accelerator

Resistive memory (ReRAM) shows promise for use as an analog synapse element in energy-efficient neural network algorithm accelerators. A particularly important application is the training of neural networks, as this is the most computationally-intensive procedure in using a neural algorithm. However, training a network with analog ReRAM synapses can significantly reduce the accuracy at the algorithm level. In order to assess this degradation, analog properties of ReRAM devices were measured and hand-written digit recognition accuracy was modeled for the training using backpropagation. Bipolar filamentary devices utilizing three material systems were measured and compared: one oxygen vacancy system, Ta-TaO x , and two conducting metallization systems, Cu-SiO 2 , and Ag/chalcogenide. Analog properties and conductance ranges of the devices are optimized by measuring the response to varying voltage pulse characteristics. Key analog device properties which degrade the accuracy are update linearity and write noise. Write noise may improve as a function of device manufacturing maturity, but write nonlinearity appears relatively consistent among the different device material systems and is found to be the most significant factor affecting accuracy. As a result, this suggests that new materials and/or fundamentally different resistive switching mechanisms may be required to improve device linearity and achieve higher algorithm training accuracy.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2015

Graphene device and method of using graphene device

An embodiment of a graphene device includes a layered structure, first and second electrodes, and a dopant island. The layered structure includes a conductive layer, an insulating layer, and a graphene layer. The electrodes are coupled to the graphene layer. The dopant island is coupled to an exposed surface of the graphene layer between the electrodes. An embodiment of a method of using a graphene device includes providing the graphene device. A voltage is applied to the conductive layer of the graphene device. Another embodiment of a method of using a graphene device includes providing the graphene device without the dopant island. A dopant island is placed on an exposed surface of the graphene layer between the electrodes. A voltage is applied to the conductive layer of the graphene device. A response of the dopant island to the voltage is observed.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2017

High voltage semiconductor devices and methods of making the devices

A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.

36 MATERIALS SCIENCE↗
DOE OSTI2018

High voltage semiconductor devices and methods of making the devices

A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.

36 MATERIALS SCIENCE↗
DOE OSTI2019

High voltage semiconductor devices and methods of making the devices

A multi-cell MOSFET device including a MOSFET cell with an integrated Schottky diode is provided. The MOSFET includes n-type source regions formed in p-type well regions which are formed in an n-type drift layer. A p-type body contact region is formed on the periphery of the MOSFET. The source metallization of the device forms a Schottky contact with an n-type semiconductor region adjacent the p-type body contact region of the device. Vias can be formed through a dielectric material covering the source ohmic contacts and/or Schottky region of the device and the source metallization can be formed in the vias. The n-type semiconductor region forming the Schottky contact and/or the n-type source regions can be a single continuous region or a plurality of discontinuous regions alternating with discontinuous p-type body contact regions. The device can be a SiC device. Methods of making the device are also provided.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Blood treatment device priming devices, methods, and systems

Simple-to-use systems, methods, and devices for priming replacement blood treatment devices, for swapping the blood treatment devices out, for replacing swapped-out blood treatment devices, and other related operations are described. In embodiments, a blood treatment device can be primed while a therapy is still running. When the replacement blood treatment device is needed, the therapy can be stopped momentarily (less than a minute) for the rapid and safe swap of the blood treatment device. Blood loss can be minimized. The down time from therapy can be minimized.

Brugger, James M.↗
DOE OSTI2021

Renewable energy integration and system operation challenge: control and optimization of millions of devices

The electric power infrastructure, originally designed and built on large-scale power plants, is evolving into a more resilient power generation and delivery system in which millions of smaller units of distributed energy generation resources units will be installed in sub-transmission and distribution networks. In order to control, manage and optimize the future grid, a hierarchical design is presented in this chapter which enables the distributed control on grid edge while inheriting the existing centralized control structure. This layered design of large-scale power system operation and control uses the following principle: reactive power control is treated as a primary control for voltage stability, and the real power control is primarily a grid-level control but can also be a supplementary control for voltage support in the case of insufficient reactive power control capacity. For the purpose of active control and operation at the distribution level, a recursive power network model is derived from nodal injection and branch power flow models. Based on the model, the proposed algorithms of hierarchical control, grid-edge inference and dynamic hosting allowance are developed and presented for multi-level controlled operation. And, a co-simulation architecture of integrated T&D system is presented to validate and demonstrate the feasibility and scalability of proposed algorithms.

Xu, Ying↗