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At least 37 records · Page 2
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Emerging Computing Architectures: Simulation of Power Electronics in Power Grids

As the penetration of power electronics increases in power grids, new computing architectures needed to be evaluated for the simulation of high-fidelity models of power electronics in power grids in operations. In this paper, emerging computing architectures such as quantum processing units are evaluated for the simulation of power electronics in power grids. A hybrid algorithm based on classical computing and quantum computing is developed and tested for different use cases of electromagnetic transient (EMT) simulation of power electronics (PE)-based systems and simple circuits. The algorithms needed to simulate power electronics in emerging computing architectures are discussed and thereafter, simulation results are shown.

Debnath, Suman↗
DOE OSTI2022

Charaterization of Emerging Computing Architectures for Dynamic Simulation of Future Power Grids with Large-Scale Power Electronics

The increasing penetration of power electronics in power grids significantly raises the computing requirements in a real-time (and/or fast) simulation of the power grid. The real-time simulation is an enabler for evaluating controllers, protection systems, new equipment, and twinning. In this paper, emerging computing architectures such as tensor processing units (TPU), neural/neuromorphic processing units (NPU), and quantum processing units (QPU) are introduced and characterized for the real-time (and/or fast) simulation of power electronics-dominated power grids. The metrics and the process to characterize emerging computing architectures to perform real-time (and/or fast) simulations of future power grids with power electronics are discussed. Three of the emerging computing units are characterized based on these metrics and the process developed. This characterization will enable identification and comparison of emerging computing architectures that can perform real-time (and/or fast) simulation of future power grids.

Choi, Jongchan↗
NASA NTRS1987

Computer architecture for efficient algorithmic executions in real-time systems: New technology for avionics systems and advanced space vehicles

Improvements and advances in the development of computer architecture now provide innovative technology for the recasting of traditional sequential solutions into high-performance, low-cost, parallel system to increase system performance. Research conducted in development of specialized computer architecture for the algorithmic execution of an avionics system, guidance and control problem in real time is described. A comprehensive treatment of both the hardware and software structures of a customized computer which performs real-time computation of guidance commands with updated estimates of target motion and time-to-go is presented. An optimal, real-time allocation algorithm was developed which maps the algorithmic tasks onto the processing elements. This allocation is based on the critical path analysis. The final stage is the design and development of the hardware structures suitable for the efficient execution of the allocated task graph. The processing element is designed for rapid execution of the allocated tasks. Fault tolerance is a key feature of the overall architecture. Parallel numerical integration techniques, tasks definitions, and allocation algorithms are discussed. The parallel implementation is analytically verified and the experimental results are presented. The design of the data-driven computer architecture, customized for the execution of the particular algorithm, is discussed.

Carroll, Chester C.↗
NASA NTRS1992

A computer architecture for intelligent machines

The theory of intelligent machines proposes a hierarchical organization for the functions of an autonomous robot based on the principle of increasing precision with decreasing intelligence. An analytic formulation of this theory using information-theoretic measures of uncertainty for each level of the intelligent machine has been developed. The authors present a computer architecture that implements the lower two levels of the intelligent machine. The architecture supports an event-driven programming paradigm that is independent of the underlying computer architecture and operating system. Execution-level controllers for motion and vision systems are briefly addressed, as well as the Petri net transducer software used to implement coordination-level functions. A case study illustrates how this computer architecture integrates real-time and higher-level control of manipulator and vision systems.

Lefebvre, D. R.↗
NASA NTRS1991

A computer architecture for intelligent machines

The Theory of Intelligent Machines proposes a hierarchical organization for the functions of an autonomous robot based on the Principle of Increasing Precision With Decreasing Intelligence. An analytic formulation of this theory using information-theoretic measures of uncertainty for each level of the intelligent machine has been developed in recent years. A computer architecture that implements the lower two levels of the intelligent machine is presented. The architecture supports an event-driven programming paradigm that is independent of the underlying computer architecture and operating system. Details of Execution Level controllers for motion and vision systems are addressed, as well as the Petri net transducer software used to implement Coordination Level functions. Extensions to UNIX and VxWorks operating systems which enable the development of a heterogeneous, distributed application are described. A case study illustrates how this computer architecture integrates real-time and higher-level control of manipulator and vision systems.

Lefebvre, D. R.↗
NASA NTRS1994

Advanced computer architecture specification for automated weld systems

This report describes the requirements for an advanced automated weld system and the associated computer architecture, and defines the overall system specification from a broad perspective. According to the requirements of welding procedures as they relate to an integrated multiaxis motion control and sensor architecture, the computer system requirements are developed based on a proven multiple-processor architecture with an expandable, distributed-memory, single global bus architecture, containing individual processors which are assigned to specific tasks that support sensor or control processes. The specified architecture is sufficiently flexible to integrate previously developed equipment, be upgradable and allow on-site modifications.

Katsinis, Constantine↗
DOE OSTI2022

Energy Use in Quantum Data Centers: Scaling the Impact of Computer Architecture, Qubit Performance, Size, and Thermal Parameters

As quantum computers increase in size, the total energy used by a quantum data center, including the cooling, will become a greater concern. The cooling requirements of quantum computers, which operate at temperatures near absolute zero, are determined by computing system parameters, including the number and type of physical qubits, the packaging efficiency of the system, and the split between circuits operating at cryogenic temperatures and those operating at room temperature. When combined with thermal system parameters such as cooling efficiency and cryostat heat transfer, the total energy use can be determined using a first-principles energy model. These models show that cooling of quantum computers differs in two fundamental ways from conventional data centers: (1) the energy required for cooling is much greater than the energy required for computation, and (2) the cooling loads are sensitive to the computational architecture. The temperature requirements for different qubit types can change energy requirements by orders of magnitude. Power use and computational power, as quantified by quantum volume, are analytically correlated. Approaches are identified for minimizing energy use in integrated quantum systems relative to computational power. Furthermore, designing a sustainable quantum computer will require both efficient cooling and system design that minimizes cooling requirements.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1987

A synchronized computational architecture for generalized bilateral control of robot arms

This paper describes a computational architecture for an interconnected high speed distributed computing system for generalized bilateral control of robot arms. The key method of the architecture is the use of fully synchronized, interrupt driven software. Since an objective of the development is to utilize the processing resources efficiently, the synchronization is done in the hardware level to reduce system software overhead. The architecture also achieves a balaced load on the communication channel. The paper also describes some architectural relations to trading or sharing manual and automatic control.

Bejczy, Antal K.↗
NASA NTRS1996

Computer Architecture. (Latest Citations from the Aerospace Database)

The bibliography contains citations concerning research and development in the field of computer architecture. Design of computer systems, microcomputer components, and digital networks are among the topics discussed. Multimicroprocessor system performance, software development, and aerospace avionics applications are also included. (Contains 50-250 citations and includes a subject term index and title list.)

BIBLIOGRAPHIES↗
NASA NTRS1977

Methodology of modeling and measuring computer architectures for plasma simulations

A brief introduction to plasma simulation using computers and the difficulties on currently available computers is given. Through the use of an analyzing and measuring methodology - SARA, the control flow and data flow of a particle simulation model REM2-1/2D are exemplified. After recursive refinements the total execution time may be greatly shortened and a fully parallel data flow can be obtained. From this data flow, a matched computer architecture or organization could be configured to achieve the computation bound of an application problem. A sequential type simulation model, an array/pipeline type simulation model, and a fully parallel simulation model of a code REM2-1/2D are proposed and analyzed. This methodology can be applied to other application problems which have implicitly parallel nature.

Wang, L. P. T.↗
DOE OSTI2016

Neuromorphic Computing, Architectures, Models, and Applications. A Beyond-CMOS Approach to Future Computing, June 29-July 1, 2016, Oak Ridge, TN

The White House and Department of Energy have been instrumental in driving the development of a neuromorphic computing program to help the United States continue its lead in basic research into (1) Beyond Exascale—high performance computing beyond Moore’s Law and von Neumann architectures, (2) Scientific Discovery—new paradigms for understanding increasingly large and complex scientific data, and (3) Emerging Architectures—assessing the potential of neuromorphic and quantum architectures. Neuromorphic computing spans a broad range of scientific disciplines from materials science to devices, to computer science, to neuroscience, all of which are required to solve the neuromorphic computing grand challenge. In our workshop we focus on the computer science aspects, specifically from a neuromorphic device through an application. Neuromorphic devices present a very different paradigm to the computer science community from traditional von Neumann architectures, which raises six major questions about building a neuromorphic application from the device level. We used these fundamental questions to organize the workshop program and to direct the workshop panels and discussions. From the white papers, presentations, panels, and discussions, there emerged several recommendations on how to proceed.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1987

Computing architecture for telerobots in earth orbit

Based on generic operational and computational requirements associated with the control of telerobots in earth orbit, a multibus-based distributed but integrated computing architecture is proposed. An experimental system of that kind under development at the Jet Propulsion Laboratory (JPL) is briefly described. It uses Intel Multibus I at both control station and remote robot (telerobot) computing nodes. An essential element within each multibus is a Unified (or Universal) Computer Control Subsystem (UCCS) for telerobot and control station motor components. The two multibus-based computing nodes can be linked by parallel or high speed serial links for real-time data transmission and for closing the real-time bilateral (force-reflecting) control loop between telerobot and control station. The experimental system is briefly commented, followed by a brief discussion of future development plans and possibilities.

Bejczy, A. K.↗
NASA NTRS2012

Real-Time Cognitive Computing Architecture for Data Fusion in a Dynamic Environment

A novel cognitive computing architecture is conceptualized for processing multiple channels of multi-modal sensory data streams simultaneously, and fusing the information in real time to generate intelligent reaction sequences. This unique architecture is capable of assimilating parallel data streams that could be analog, digital, synchronous/asynchronous, and could be programmed to act as a knowledge synthesizer and/or an "intelligent perception" processor. In this architecture, the bio-inspired models of visual pathway and olfactory receptor processing are combined as processing components, to achieve the composite function of "searching for a source of food while avoiding the predator." The architecture is particularly suited for scene analysis from visual data and odorant.

Duong, Tuan A.↗
DOE OSTI2016

Developing Materials Processing to Performance Modeling Capabilities and the Need for Exascale Computing Architectures (and Beyond)

Additive Manufacturing techniques are presenting the Department of Energy and the NNSA Laboratories with new opportunities to consider novel component production and repair processes, and to manufacture materials with tailored response and optimized performance characteristics. Additive Manufacturing technologies already are being applied to primary NNSA mission areas, including Nuclear Weapons. These mission areas are adapting to these new manufacturing methods, because of potential advantages, such as smaller manufacturing footprints, reduced needs for specialized tooling, an ability to embed sensing, novel part repair options, an ability to accommodate complex geometries, and lighter weight materials. To realize the full potential of Additive Manufacturing as a game-changing technology for the NNSA’s national security missions; however, significant progress must be made in several key technical areas. In addition to advances in engineering design, process optimization and automation, and accelerated feedstock design and manufacture, significant progress must be made in modeling and simulation. First and foremost, a more mature understanding of the process-structure-property-performance relationships must be developed. Because Additive Manufacturing processes change the nature of a material’s structure below the engineering scale, new models are required to predict materials response across the spectrum of relevant length scales, from the atomistic to the continuum. New diagnostics will be required to characterize materials response across these scales. And not just models, but advanced algorithms, next-generation codes, and advanced computer architectures will be required to complement the associated modeling activities. Based on preliminary work in each of these areas, a strong argument for the need for Exascale computing architectures can be made, if a legitimate predictive capability is to be developed.

36 MATERIALS SCIENCE↗
NASA NTRS1989

Computational architecture for integrated controls and structures design

To facilitate the development of control structure interaction (CSI) design methodology, a computational architecture for interdisciplinary design of active structures is presented. The emphasis of the computational procedure is to exploit existing sparse matrix structural analysis techniques, in-core data transfer with control synthesis programs, and versatility in the optimization methodology to avoid unnecessary structural or control calculations. The architecture is designed such that all required structure, control and optimization analyses are performed within one program. Hence, the optimization strategy is not unduly constrained by cold starts of existing structural analysis and control synthesis packages.

Belvin, W. Keith↗
NASA NTRS1990

Multi-level Hierarchical Poly Tree computer architectures

Based on the concept of hierarchical substructuring, this paper develops an optimal multi-level Hierarchical Poly Tree (HPT) parallel computer architecture scheme which is applicable to the solution of finite element and difference simulations. Emphasis is given to minimizing computational effort, in-core/out-of-core memory requirements, and the data transfer between processors. In addition, a simplified communications network that reduces the number of I/O channels between processors is presented. HPT configurations that yield optimal superlinearities are also demonstrated. Moreover, to generalize the scope of applicability, special attention is given to developing: (1) multi-level reduction trees which provide an orderly/optimal procedure by which model densification/simplification can be achieved, as well as (2) methodologies enabling processor grading that yields architectures with varying types of multi-level granularity.

Padovan, Joe↗
DOE OSTI2019

Software for Sparse Tensor Decomposition on Emerging Computing Architectures

In this paper, we develop software for decomposing sparse tensors that is portable to and performant on a variety of multicore, manycore, and GPU computing architectures. The result is a single code whose performance matches optimized architecture-specific implementations. The key to a portable approach is to determine multiple levels of parallelism that can be mapped in different ways to different architectures, and we explain how to do this for the matricized tensor times Khatri--Rao product (MTTKRP), which is the key kernel in canonical polyadic tensor decomposition. Our implementation leverages the Kokkos framework, which enables a single code to achieve high performance across multiple architectures that differ in how they approach fine-grained parallelism. We also introduce a new construct for portable thread-local arrays, which we call compile-time polymorphic arrays. Not only are the specifics of our approaches and implementation interesting for tuning tensor computations, but they also provide a roadmap for developing other portable high-performance codes. As a last step in optimizing performance, we modify the MTTKRP algorithm itself to do a permuted traversal of tensor nonzeros to reduce atomic-write contention. Lastly, we test the performance of our implementation on 16- and 68-core Intel CPUs and the K80 and P100 NVIDIA GPUs, showing that we are competitive with state-of-the-art architecture-specific codes while having the advantage of being able to run on a variety of architectures.

97 MATHEMATICS AND COMPUTING↗